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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [dpMem_dc_simlib.v] - Blame information for rev 534

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1 408 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// dpMem_dc.v                                                 ////
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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//// Synchronous dual port memory with dual clocks
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module dpMem_dc_simlib(  addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut);
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  //FIFO_DEPTH = ADDR_WIDTH^2
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  parameter FIFO_WIDTH = 8;
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  parameter FIFO_DEPTH = 64;
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  parameter ADDR_WIDTH = 6;
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input wrClk;
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input rdClk;
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input [FIFO_WIDTH-1:0] dataIn;
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output [FIFO_WIDTH-1:0] dataOut;
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input writeEn;
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input readEn;
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input [ADDR_WIDTH-1:0] addrIn;
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input [ADDR_WIDTH-1:0] addrOut;
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wire wrClk;
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wire rdClk;
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wire [FIFO_WIDTH-1:0] dataIn;
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reg [FIFO_WIDTH-1:0] dataOut;
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wire writeEn;
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wire readEn;
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wire [ADDR_WIDTH-1:0] addrIn;
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wire [ADDR_WIDTH-1:0] addrOut;
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reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
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// synchronous read. Introduces one clock cycle delay
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always @(posedge rdClk) begin
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  dataOut <= buffer[addrOut];
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end
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// synchronous write
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always @(posedge wrClk) begin
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  if (writeEn == 1'b1)
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    buffer[addrIn] <= dataIn;
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end
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endmodule

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