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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [endpMux_simlib.v] - Blame information for rev 509

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1 408 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// endpMux.v                                                    ////
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbSlaveControl_h.v"
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module endpMux_simlib (
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  clk,
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  rst,
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  currEndP,
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  NAKSent,
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  stallSent,
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  CRCError,
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  bitStuffError,
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  RxOverflow,
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  RxTimeOut,
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  dataSequence,
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  ACKRxed,
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  transType,
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  transTypeNAK,
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  endPControlReg,
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  clrEPRdy,
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  endPMuxErrorsWEn,
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  endP0ControlReg,
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  endP1ControlReg,
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  endP2ControlReg,
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  endP3ControlReg,
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  endP0StatusReg,
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  endP1StatusReg,
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  endP2StatusReg,
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  endP3StatusReg,
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  endP0TransTypeReg,
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  endP1TransTypeReg,
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  endP2TransTypeReg,
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  endP3TransTypeReg,
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  endP0NAKTransTypeReg,
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  endP1NAKTransTypeReg,
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  endP2NAKTransTypeReg,
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  endP3NAKTransTypeReg,
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  clrEP0Rdy,
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  clrEP1Rdy,
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  clrEP2Rdy,
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  clrEP3Rdy);
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input clk;
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input rst;
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input [3:0] currEndP;
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input NAKSent;
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input stallSent;
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input CRCError;
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input bitStuffError;
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input RxOverflow;
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input RxTimeOut;
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input dataSequence;
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input ACKRxed;
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input [1:0] transType;
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input [1:0] transTypeNAK;
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output [4:0] endPControlReg;
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input clrEPRdy;
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input endPMuxErrorsWEn;
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input [4:0] endP0ControlReg;
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input [4:0] endP1ControlReg;
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input [4:0] endP2ControlReg;
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input [4:0] endP3ControlReg;
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output [7:0] endP0StatusReg;
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output [7:0] endP1StatusReg;
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output [7:0] endP2StatusReg;
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output [7:0] endP3StatusReg;
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output [1:0] endP0TransTypeReg;
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output [1:0] endP1TransTypeReg;
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output [1:0] endP2TransTypeReg;
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output [1:0] endP3TransTypeReg;
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output [1:0] endP0NAKTransTypeReg;
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output [1:0] endP1NAKTransTypeReg;
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output [1:0] endP2NAKTransTypeReg;
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output [1:0] endP3NAKTransTypeReg;
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output clrEP0Rdy;
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output clrEP1Rdy;
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output clrEP2Rdy;
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output clrEP3Rdy;
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wire clk;
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wire rst;
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wire [3:0] currEndP;
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wire NAKSent;
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wire stallSent;
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wire CRCError;
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wire bitStuffError;
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wire RxOverflow;
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wire RxTimeOut;
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wire dataSequence;
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wire ACKRxed;
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wire [1:0] transType;
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wire [1:0] transTypeNAK;
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reg [4:0] endPControlReg;
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wire clrEPRdy;
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wire endPMuxErrorsWEn;
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wire [4:0] endP0ControlReg;
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wire [4:0] endP1ControlReg;
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wire [4:0] endP2ControlReg;
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wire [4:0] endP3ControlReg;
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reg [7:0] endP0StatusReg;
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reg [7:0] endP1StatusReg;
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reg [7:0] endP2StatusReg;
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reg [7:0] endP3StatusReg;
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reg [1:0] endP0TransTypeReg;
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reg [1:0] endP1TransTypeReg;
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reg [1:0] endP2TransTypeReg;
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reg [1:0] endP3TransTypeReg;
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reg [1:0] endP0NAKTransTypeReg;
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reg [1:0] endP1NAKTransTypeReg;
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reg [1:0] endP2NAKTransTypeReg;
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reg [1:0] endP3NAKTransTypeReg;
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reg clrEP0Rdy;
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reg clrEP1Rdy;
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reg clrEP2Rdy;
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reg clrEP3Rdy;
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//internal wires and regs
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reg [7:0] endPStatusCombine;
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//mux endPControlReg and clrEPRdy
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always @(posedge clk)
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begin
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  case (currEndP[1:0])
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    2'b00: begin
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      endPControlReg <= endP0ControlReg;
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      clrEP0Rdy <= clrEPRdy;
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    end
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    2'b01: begin
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      endPControlReg <= endP1ControlReg;
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      clrEP1Rdy <= clrEPRdy;
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    end
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    2'b10: begin
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      endPControlReg <= endP2ControlReg;
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      clrEP2Rdy <= clrEPRdy;
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    end
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    2'b11: begin
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      endPControlReg <= endP3ControlReg;
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      clrEP3Rdy <= clrEPRdy;
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    end
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  endcase
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end
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//mux endPNAKTransType, endPTransType, endPStatusReg
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//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
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//else update the entire status reg
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always @(posedge clk)
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begin
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  if (rst) begin
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    endP0NAKTransTypeReg <= 2'b00;
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    endP1NAKTransTypeReg <= 2'b00;
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    endP2NAKTransTypeReg <= 2'b00;
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    endP3NAKTransTypeReg <= 2'b00;
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    endP0TransTypeReg <= 2'b00;
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    endP1TransTypeReg <= 2'b00;
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    endP2TransTypeReg <= 2'b00;
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    endP3TransTypeReg <= 2'b00;
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    endP0StatusReg <= 4'h0;
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    endP1StatusReg <= 4'h0;
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    endP2StatusReg <= 4'h0;
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    endP3StatusReg <= 4'h0;
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  end
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  else begin
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    if (endPMuxErrorsWEn == 1'b1) begin
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      if (NAKSent == 1'b1) begin
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        case (currEndP[1:0])
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          2'b00: begin
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            endP0NAKTransTypeReg <= transTypeNAK;
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            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK;
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          end
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          2'b01: begin
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            endP1NAKTransTypeReg <= transTypeNAK;
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            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK;
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          end
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          2'b10: begin
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            endP2NAKTransTypeReg <= transTypeNAK;
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            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK;
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          end
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          2'b11: begin
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            endP3NAKTransTypeReg <= transTypeNAK;
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            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK;
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          end
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        endcase
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      end
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      else begin
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        case (currEndP[1:0])
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          2'b00: begin
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            endP0TransTypeReg <= transType;
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            endP0StatusReg <= endPStatusCombine;
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          end
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          2'b01: begin
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            endP1TransTypeReg <= transType;
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            endP1StatusReg <= endPStatusCombine;
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          end
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          2'b10: begin
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            endP2TransTypeReg <= transType;
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            endP2StatusReg <= endPStatusCombine;
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          end
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          2'b11: begin
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            endP3TransTypeReg <= transType;
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            endP3StatusReg <= endPStatusCombine;
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          end
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        endcase
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      end
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    end
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  end
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end
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//combine status bits into a single word
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always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
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begin
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  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
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end
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endmodule

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