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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [hostcontroller_simlib.v] - Blame information for rev 541

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// hostController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostControl_h.v"
`include "usbConstants_h.v"
 
 
module hostcontroller_simlib (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, isoEn, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
input   [7:0] RXStatus;
input   clk;
input   getPacketRdy;
input   isoEn;
input   rst;
input   sendPacketArbiterGnt;
input   sendPacketRdy;
input   transReq;
input   [1:0] transType;
output  clearTXReq;
output  getPacketREn;
output  sendPacketArbiterReq;
output  [3:0] sendPacketPID;
output  sendPacketWEn;
output  transDone;
 
wire    [7:0] RXStatus;
reg     clearTXReq, next_clearTXReq;
wire    clk;
reg     getPacketREn, next_getPacketREn;
wire    getPacketRdy;
wire    isoEn;
wire    rst;
wire    sendPacketArbiterGnt;
reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
reg     [3:0] sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     transDone, next_transDone;
wire    transReq;
wire    [1:0] transType;
 
// diagram signals declarations
reg  [3:0]delCnt, next_delCnt;
 
// BINARY ENCODED state machine: hstCntrl
// State codes definitions:
`define START_HC 6'b000000
`define TX_REQ 6'b000001
`define CHK_TYPE 6'b000010
`define FLAG 6'b000011
`define IN_WAIT_DATA_RXED 6'b000100
`define IN_CHK_FOR_ERROR 6'b000101
`define IN_CLR_SP_WEN2 6'b000110
`define SETUP_CLR_SP_WEN1 6'b000111
`define SETUP_CLR_SP_WEN2 6'b001000
`define FIN 6'b001001
`define WAIT_GNT 6'b001010
`define SETUP_WAIT_PKT_RXED 6'b001011
`define IN_WAIT_IN_SENT 6'b001100
`define OUT0_WAIT_RX_DATA 6'b001101
`define OUT0_WAIT_DATA0_SENT 6'b001110
`define OUT0_WAIT_OUT_SENT 6'b001111
`define SETUP_HC_WAIT_RDY 6'b010000
`define IN_WAIT_SP_RDY1 6'b010001
`define IN_WAIT_SP_RDY2 6'b010010
`define OUT0_WAIT_SP_RDY1 6'b010011
`define SETUP_WAIT_SETUP_SENT 6'b010100
`define SETUP_WAIT_DATA_SENT 6'b010101
`define IN_CLR_SP_WEN1 6'b010110
`define IN_WAIT_ACK_SENT 6'b010111
`define OUT0_CLR_WEN1 6'b011000
`define OUT0_CLR_WEN2 6'b011001
`define OUT1_WAIT_RX_DATA 6'b011010
`define OUT1_WAIT_OUT_SENT 6'b011011
`define OUT1_WAIT_DATA1_SENT 6'b011100
`define OUT1_WAIT_SP_RDY1 6'b011101
`define OUT1_CLR_WEN1 6'b011110
`define OUT1_CLR_WEN2 6'b011111
`define OUT0_CHK_ISO 6'b100000
 
reg [5:0] CurrState_hstCntrl;
reg [5:0] NextState_hstCntrl;
 
 
//--------------------------------------------------------------------
// Machine: hstCntrl
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (delCnt or transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
begin : hstCntrl_NextState
  NextState_hstCntrl <= CurrState_hstCntrl;
  // Set default values for outputs and signals
  next_sendPacketArbiterReq <= sendPacketArbiterReq;
  next_transDone <= transDone;
  next_clearTXReq <= clearTXReq;
  next_delCnt <= delCnt;
  next_sendPacketWEn <= sendPacketWEn;
  next_getPacketREn <= getPacketREn;
  next_sendPacketPID <= sendPacketPID;
  case (CurrState_hstCntrl) // synopsys parallel_case full_case
    `START_HC:
      NextState_hstCntrl <= `TX_REQ;
    `TX_REQ:
      if (transReq == 1'b1)
      begin
        NextState_hstCntrl <= `WAIT_GNT;
        next_sendPacketArbiterReq <= 1'b1;
      end
    `CHK_TYPE:
      if (transType == `IN_TRANS)
        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
      else if (transType == `OUTDATA0_TRANS)
        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
      else if (transType == `OUTDATA1_TRANS)
        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
      else if (transType == `SETUP_TRANS)
        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
    `FLAG:
    begin
      next_transDone <= 1'b1;
      next_clearTXReq <= 1'b1;
      next_sendPacketArbiterReq <= 1'b0;
      next_delCnt <= 4'h0;
      NextState_hstCntrl <= `FIN;
    end
    `FIN:
    begin
      next_clearTXReq <= 1'b0;
      next_transDone <= 1'b0;
      next_delCnt <= delCnt + 1'b1;
      //now wait for 'transReq' to clear
      if (delCnt == 4'hf)
        NextState_hstCntrl <= `TX_REQ;
    end
    `WAIT_GNT:
      if (sendPacketArbiterGnt == 1'b1)
        NextState_hstCntrl <= `CHK_TYPE;
    `SETUP_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
    end
    `SETUP_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
    end
    `SETUP_WAIT_PKT_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
        NextState_hstCntrl <= `FLAG;
    end
    `SETUP_HC_WAIT_RDY:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `SETUP;
      end
    `SETUP_WAIT_SETUP_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    `SETUP_WAIT_DATA_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
        next_getPacketREn <= 1'b1;
      end
    `IN_WAIT_DATA_RXED:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
    end
    `IN_CHK_FOR_ERROR:
      if (isoEn == 1'b1)
        NextState_hstCntrl <= `FLAG;
      else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
      else
        NextState_hstCntrl <= `FLAG;
    `IN_CLR_SP_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
    end
    `IN_WAIT_IN_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
        next_getPacketREn <= 1'b1;
      end
    `IN_WAIT_SP_RDY1:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `IN;
      end
    `IN_WAIT_SP_RDY2:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    `IN_CLR_SP_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
    end
    `IN_WAIT_ACK_SENT:
      if (sendPacketRdy == 1'b1)
        NextState_hstCntrl <= `FLAG;
    `OUT0_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
        NextState_hstCntrl <= `FLAG;
    end
    `OUT0_WAIT_DATA0_SENT:
      if (sendPacketRdy == 1'b1)
        NextState_hstCntrl <= `OUT0_CHK_ISO;
    `OUT0_WAIT_OUT_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
    `OUT0_WAIT_SP_RDY1:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT0_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    `OUT0_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
    end
    `OUT0_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
    end
    `OUT0_CHK_ISO:
      if (isoEn == 1'b0)
      begin
        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
      else
        NextState_hstCntrl <= `FLAG;
    `OUT1_WAIT_RX_DATA:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
        NextState_hstCntrl <= `FLAG;
    end
    `OUT1_WAIT_OUT_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN2;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    `OUT1_WAIT_DATA1_SENT:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
        next_getPacketREn <= 1'b1;
      end
    `OUT1_WAIT_SP_RDY1:
      if (sendPacketRdy == 1'b1)
      begin
        NextState_hstCntrl <= `OUT1_CLR_WEN1;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `OUT;
      end
    `OUT1_CLR_WEN1:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
    end
    `OUT1_CLR_WEN2:
    begin
      next_sendPacketWEn <= 1'b0;
      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
    end
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : hstCntrl_CurrentState
  if (rst)
    CurrState_hstCntrl <= `START_HC;
  else
    CurrState_hstCntrl <= NextState_hstCntrl;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : hstCntrl_RegOutput
  if (rst)
  begin
    delCnt <= 4'h0;
    transDone <= 1'b0;
    clearTXReq <= 1'b0;
    getPacketREn <= 1'b0;
    sendPacketArbiterReq <= 1'b0;
    sendPacketWEn <= 1'b0;
    sendPacketPID <= 4'b0;
  end
  else
  begin
    delCnt <= next_delCnt;
    transDone <= next_transDone;
    clearTXReq <= next_clearTXReq;
    getPacketREn <= next_getPacketREn;
    sendPacketArbiterReq <= next_sendPacketArbiterReq;
    sendPacketWEn <= next_sendPacketWEn;
    sendPacketPID <= next_sendPacketPID;
  end
end
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [hostcontroller_simlib.v] - Blame information for rev 541

Line No.	Rev	Author	Line
1	408	julius
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// hostController`
5			`//// ////`
6			`//// This file is part of the usbhostslave opencores effort.`
7			`//// http://www.opencores.org/cores/usbhostslave/ ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`////`
11			`//// ////`
12			`//// To Do: ////`
13			`////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Steve Fielding, sfielding@base2designs.com ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`include "timescale.v"
46			`include "usbHostControl_h.v"
47			`include "usbConstants_h.v"
48
49
50			`module hostcontroller_simlib (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, isoEn, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);`
51			`input [7:0] RXStatus;`
52			`input clk;`
53			`input getPacketRdy;`
54			`input isoEn;`
55			`input rst;`
56			`input sendPacketArbiterGnt;`
57			`input sendPacketRdy;`
58			`input transReq;`
59			`input [1:0] transType;`
60			`output clearTXReq;`
61			`output getPacketREn;`
62			`output sendPacketArbiterReq;`
63			`output [3:0] sendPacketPID;`
64			`output sendPacketWEn;`
65			`output transDone;`
66
67			`wire [7:0] RXStatus;`
68			`reg clearTXReq, next_clearTXReq;`
69			`wire clk;`
70			`reg getPacketREn, next_getPacketREn;`
71			`wire getPacketRdy;`
72			`wire isoEn;`
73			`wire rst;`
74			`wire sendPacketArbiterGnt;`
75			`reg sendPacketArbiterReq, next_sendPacketArbiterReq;`
76			`reg [3:0] sendPacketPID, next_sendPacketPID;`
77			`wire sendPacketRdy;`
78			`reg sendPacketWEn, next_sendPacketWEn;`
79			`reg transDone, next_transDone;`
80			`wire transReq;`
81			`wire [1:0] transType;`
82
83			`// diagram signals declarations`
84			`reg [3:0]delCnt, next_delCnt;`
85
86			`// BINARY ENCODED state machine: hstCntrl`
87			`// State codes definitions:`
88			`define START_HC 6'b000000
89			`define TX_REQ 6'b000001
90			`define CHK_TYPE 6'b000010
91			`define FLAG 6'b000011
92			`define IN_WAIT_DATA_RXED 6'b000100
93			`define IN_CHK_FOR_ERROR 6'b000101
94			`define IN_CLR_SP_WEN2 6'b000110
95			`define SETUP_CLR_SP_WEN1 6'b000111
96			`define SETUP_CLR_SP_WEN2 6'b001000
97			`define FIN 6'b001001
98			`define WAIT_GNT 6'b001010
99			`define SETUP_WAIT_PKT_RXED 6'b001011
100			`define IN_WAIT_IN_SENT 6'b001100
101			`define OUT0_WAIT_RX_DATA 6'b001101
102			`define OUT0_WAIT_DATA0_SENT 6'b001110
103			`define OUT0_WAIT_OUT_SENT 6'b001111
104			`define SETUP_HC_WAIT_RDY 6'b010000
105			`define IN_WAIT_SP_RDY1 6'b010001
106			`define IN_WAIT_SP_RDY2 6'b010010
107			`define OUT0_WAIT_SP_RDY1 6'b010011
108			`define SETUP_WAIT_SETUP_SENT 6'b010100
109			`define SETUP_WAIT_DATA_SENT 6'b010101
110			`define IN_CLR_SP_WEN1 6'b010110
111			`define IN_WAIT_ACK_SENT 6'b010111
112			`define OUT0_CLR_WEN1 6'b011000
113			`define OUT0_CLR_WEN2 6'b011001
114			`define OUT1_WAIT_RX_DATA 6'b011010
115			`define OUT1_WAIT_OUT_SENT 6'b011011
116			`define OUT1_WAIT_DATA1_SENT 6'b011100
117			`define OUT1_WAIT_SP_RDY1 6'b011101
118			`define OUT1_CLR_WEN1 6'b011110
119			`define OUT1_CLR_WEN2 6'b011111
120			`define OUT0_CHK_ISO 6'b100000
121
122			`reg [5:0] CurrState_hstCntrl;`
123			`reg [5:0] NextState_hstCntrl;`
124
125
126			`//--------------------------------------------------------------------`
127			`// Machine: hstCntrl`
128			`//--------------------------------------------------------------------`
129			`//----------------------------------`
130			`// Next State Logic (combinatorial)`
131			`//----------------------------------`
132			`always @ (delCnt or transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)`
133			`begin : hstCntrl_NextState`
134			`NextState_hstCntrl <= CurrState_hstCntrl;`
135			`// Set default values for outputs and signals`
136			`next_sendPacketArbiterReq <= sendPacketArbiterReq;`
137			`next_transDone <= transDone;`
138			`next_clearTXReq <= clearTXReq;`
139			`next_delCnt <= delCnt;`
140			`next_sendPacketWEn <= sendPacketWEn;`
141			`next_getPacketREn <= getPacketREn;`
142			`next_sendPacketPID <= sendPacketPID;`
143			`case (CurrState_hstCntrl) // synopsys parallel_case full_case`
144			`START_HC:
145			NextState_hstCntrl <= `TX_REQ;
146			`TX_REQ:
147			`if (transReq == 1'b1)`
148			`begin`
149			NextState_hstCntrl <= `WAIT_GNT;
150			`next_sendPacketArbiterReq <= 1'b1;`
151			`end`
152			`CHK_TYPE:
153			if (transType == `IN_TRANS)
154			NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
155			else if (transType == `OUTDATA0_TRANS)
156			NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
157			else if (transType == `OUTDATA1_TRANS)
158			NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
159			else if (transType == `SETUP_TRANS)
160			NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
161			`FLAG:
162			`begin`
163			`next_transDone <= 1'b1;`
164			`next_clearTXReq <= 1'b1;`
165			`next_sendPacketArbiterReq <= 1'b0;`
166			`next_delCnt <= 4'h0;`
167			NextState_hstCntrl <= `FIN;
168			`end`
169			`FIN:
170			`begin`
171			`next_clearTXReq <= 1'b0;`
172			`next_transDone <= 1'b0;`
173			`next_delCnt <= delCnt + 1'b1;`
174			`//now wait for 'transReq' to clear`
175			`if (delCnt == 4'hf)`
176			NextState_hstCntrl <= `TX_REQ;
177			`end`
178			`WAIT_GNT:
179			`if (sendPacketArbiterGnt == 1'b1)`
180			NextState_hstCntrl <= `CHK_TYPE;
181			`SETUP_CLR_SP_WEN1:
182			`begin`
183			`next_sendPacketWEn <= 1'b0;`
184			NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
185			`end`
186			`SETUP_CLR_SP_WEN2:
187			`begin`
188			`next_sendPacketWEn <= 1'b0;`
189			NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
190			`end`
191			`SETUP_WAIT_PKT_RXED:
192			`begin`
193			`next_getPacketREn <= 1'b0;`
194			`if (getPacketRdy == 1'b1)`
195			NextState_hstCntrl <= `FLAG;
196			`end`
197			`SETUP_HC_WAIT_RDY:
198			`if (sendPacketRdy == 1'b1)`
199			`begin`
200			NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
201			`next_sendPacketWEn <= 1'b1;`
202			next_sendPacketPID <= `SETUP;
203			`end`
204			`SETUP_WAIT_SETUP_SENT:
205			`if (sendPacketRdy == 1'b1)`
206			`begin`
207			NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
208			`next_sendPacketWEn <= 1'b1;`
209			next_sendPacketPID <= `DATA0;
210			`end`
211			`SETUP_WAIT_DATA_SENT:
212			`if (sendPacketRdy == 1'b1)`
213			`begin`
214			NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
215			`next_getPacketREn <= 1'b1;`
216			`end`
217			`IN_WAIT_DATA_RXED:
218			`begin`
219			`next_getPacketREn <= 1'b0;`
220			`if (getPacketRdy == 1'b1)`
221			NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
222			`end`
223			`IN_CHK_FOR_ERROR:
224			`if (isoEn == 1'b1)`
225			NextState_hstCntrl <= `FLAG;
226			else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
227			RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
228			RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
229			RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
230			RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
231			RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
232			NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
233			`else`
234			NextState_hstCntrl <= `FLAG;
235			`IN_CLR_SP_WEN2:
236			`begin`
237			`next_sendPacketWEn <= 1'b0;`
238			NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
239			`end`
240			`IN_WAIT_IN_SENT:
241			`if (sendPacketRdy == 1'b1)`
242			`begin`
243			NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
244			`next_getPacketREn <= 1'b1;`
245			`end`
246			`IN_WAIT_SP_RDY1:
247			`if (sendPacketRdy == 1'b1)`
248			`begin`
249			NextState_hstCntrl <= `IN_CLR_SP_WEN1;
250			`next_sendPacketWEn <= 1'b1;`
251			next_sendPacketPID <= `IN;
252			`end`
253			`IN_WAIT_SP_RDY2:
254			`if (sendPacketRdy == 1'b1)`
255			`begin`
256			NextState_hstCntrl <= `IN_CLR_SP_WEN2;
257			`next_sendPacketWEn <= 1'b1;`
258			next_sendPacketPID <= `ACK;
259			`end`
260			`IN_CLR_SP_WEN1:
261			`begin`
262			`next_sendPacketWEn <= 1'b0;`
263			NextState_hstCntrl <= `IN_WAIT_IN_SENT;
264			`end`
265			`IN_WAIT_ACK_SENT:
266			`if (sendPacketRdy == 1'b1)`
267			NextState_hstCntrl <= `FLAG;
268			`OUT0_WAIT_RX_DATA:
269			`begin`
270			`next_getPacketREn <= 1'b0;`
271			`if (getPacketRdy == 1'b1)`
272			NextState_hstCntrl <= `FLAG;
273			`end`
274			`OUT0_WAIT_DATA0_SENT:
275			`if (sendPacketRdy == 1'b1)`
276			NextState_hstCntrl <= `OUT0_CHK_ISO;
277			`OUT0_WAIT_OUT_SENT:
278			`if (sendPacketRdy == 1'b1)`
279			`begin`
280			NextState_hstCntrl <= `OUT0_CLR_WEN2;
281			`next_sendPacketWEn <= 1'b1;`
282			next_sendPacketPID <= `DATA0;
283			`end`
284			`OUT0_WAIT_SP_RDY1:
285			`if (sendPacketRdy == 1'b1)`
286			`begin`
287			NextState_hstCntrl <= `OUT0_CLR_WEN1;
288			`next_sendPacketWEn <= 1'b1;`
289			next_sendPacketPID <= `OUT;
290			`end`
291			`OUT0_CLR_WEN1:
292			`begin`
293			`next_sendPacketWEn <= 1'b0;`
294			NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
295			`end`
296			`OUT0_CLR_WEN2:
297			`begin`
298			`next_sendPacketWEn <= 1'b0;`
299			NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
300			`end`
301			`OUT0_CHK_ISO:
302			`if (isoEn == 1'b0)`
303			`begin`
304			NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
305			`next_getPacketREn <= 1'b1;`
306			`end`
307			`else`
308			NextState_hstCntrl <= `FLAG;
309			`OUT1_WAIT_RX_DATA:
310			`begin`
311			`next_getPacketREn <= 1'b0;`
312			`if (getPacketRdy == 1'b1)`
313			NextState_hstCntrl <= `FLAG;
314			`end`
315			`OUT1_WAIT_OUT_SENT:
316			`if (sendPacketRdy == 1'b1)`
317			`begin`
318			NextState_hstCntrl <= `OUT1_CLR_WEN2;
319			`next_sendPacketWEn <= 1'b1;`
320			next_sendPacketPID <= `DATA1;
321			`end`
322			`OUT1_WAIT_DATA1_SENT:
323			`if (sendPacketRdy == 1'b1)`
324			`begin`
325			NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
326			`next_getPacketREn <= 1'b1;`
327			`end`
328			`OUT1_WAIT_SP_RDY1:
329			`if (sendPacketRdy == 1'b1)`
330			`begin`
331			NextState_hstCntrl <= `OUT1_CLR_WEN1;
332			`next_sendPacketWEn <= 1'b1;`
333			next_sendPacketPID <= `OUT;
334			`end`
335			`OUT1_CLR_WEN1:
336			`begin`
337			`next_sendPacketWEn <= 1'b0;`
338			NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
339			`end`
340			`OUT1_CLR_WEN2:
341			`begin`
342			`next_sendPacketWEn <= 1'b0;`
343			NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
344			`end`
345			`endcase`
346			`end`
347
348			`//----------------------------------`
349			`// Current State Logic (sequential)`
350			`//----------------------------------`
351			`always @ (posedge clk)`
352			`begin : hstCntrl_CurrentState`
353			`if (rst)`
354			CurrState_hstCntrl <= `START_HC;
355			`else`
356			`CurrState_hstCntrl <= NextState_hstCntrl;`
357			`end`
358
359			`//----------------------------------`
360			`// Registered outputs logic`
361			`//----------------------------------`
362			`always @ (posedge clk)`
363			`begin : hstCntrl_RegOutput`
364			`if (rst)`
365			`begin`
366			`delCnt <= 4'h0;`
367			`transDone <= 1'b0;`
368			`clearTXReq <= 1'b0;`
369			`getPacketREn <= 1'b0;`
370			`sendPacketArbiterReq <= 1'b0;`
371			`sendPacketWEn <= 1'b0;`
372			`sendPacketPID <= 4'b0;`
373			`end`
374			`else`
375			`begin`
376			`delCnt <= next_delCnt;`
377			`transDone <= next_transDone;`
378			`clearTXReq <= next_clearTXReq;`
379			`getPacketREn <= next_getPacketREn;`
380			`sendPacketArbiterReq <= next_sendPacketArbiterReq;`
381			`sendPacketWEn <= next_sendPacketWEn;`
382			`sendPacketPID <= next_sendPacketPID;`
383			`end`
384			`end`
385
386			`endmodule`