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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [processRxBit_simlib.v] - Blame information for rev 673

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// File        : ../RTL/serialInterfaceEngine/processRxBit.v
// Generated   : 11/10/06 05:37:22
// From        : ../RTL/serialInterfaceEngine/processRxBit.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processrxbit
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
 
 
module processRxBit_simlib (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
input   [1:0] JBit;
input   [1:0] KBit;
input   [1:0] RxBitsIn;
input   RxWireActive;
input   clk;
input   processRxBitsWEn;
input   processRxByteRdy;
input   rst;
output  [7:0] RxCtrlOut;
output  [7:0] RxDataOut;
output  processRxBitRdy;
output  processRxByteWEn;
output  resumeDetected;
 
wire    [1:0] JBit;
wire    [1:0] KBit;
wire    [1:0] RxBitsIn;
reg     [7:0] RxCtrlOut, next_RxCtrlOut;
reg     [7:0] RxDataOut, next_RxDataOut;
wire    RxWireActive;
wire    clk;
reg     processRxBitRdy, next_processRxBitRdy;
wire    processRxBitsWEn;
wire    processRxByteRdy;
reg     processRxByteWEn, next_processRxByteWEn;
reg     resumeDetected, next_resumeDetected;
wire    rst;
 
// diagram signals declarations
reg  [3:0]RXBitCount, next_RXBitCount;
reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
reg  [7:0]RXByte, next_RXByte;
reg  [3:0]RXSameBitCount, next_RXSameBitCount;
reg  [1:0]RxBits, next_RxBits;
reg  bitStuffError, next_bitStuffError;
reg  [1:0]oldRXBits, next_oldRXBits;
reg  [4:0]resumeWaitCnt, next_resumeWaitCnt;
 
// BINARY ENCODED state machine: prRxBit
// State codes definitions:
`define START 4'b0000
`define IDLE_FIRST_BIT 4'b0001
`define WAIT_BITS 4'b0010
`define IDLE_CHK_KBIT 4'b0011
`define DATA_RX_LAST_BIT 4'b0100
`define DATA_RX_CHK_SE0 4'b0101
`define DATA_RX_DATA_DESTUFF 4'b0110
`define DATA_RX_BYTE_SEND2 4'b0111
`define DATA_RX_BYTE_WAIT_RDY 4'b1000
`define RES_RX_CHK 4'b1001
`define DATA_RX_ERROR_CHK_RES 4'b1010
`define RES_END_CHK1 4'b1011
`define IDLE_WAIT_PRB_RDY 4'b1100
`define DATA_RX_WAIT_PRB_RDY 4'b1101
`define DATA_RX_ERROR_WAIT_RDY 4'b1110
 
reg [3:0] CurrState_prRxBit;
reg [3:0] NextState_prRxBit;
 
 
//--------------------------------------------------------------------
// Machine: prRxBit
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
begin : prRxBit_NextState
  NextState_prRxBit <= CurrState_prRxBit;
  // Set default values for outputs and signals
  next_processRxByteWEn <= processRxByteWEn;
  next_RxCtrlOut <= RxCtrlOut;
  next_RxDataOut <= RxDataOut;
  next_resumeDetected <= resumeDetected;
  next_RXBitStMachCurrState <= RXBitStMachCurrState;
  next_RxBits <= RxBits;
  next_RXSameBitCount <= RXSameBitCount;
  next_RXBitCount <= RXBitCount;
  next_oldRXBits <= oldRXBits;
  next_RXByte <= RXByte;
  next_bitStuffError <= bitStuffError;
  next_resumeWaitCnt <= resumeWaitCnt;
  next_processRxBitRdy <= processRxBitRdy;
  case (CurrState_prRxBit)
    `START:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RxCtrlOut <= 8'h00;
      next_RxDataOut <= 8'h00;
      next_resumeDetected <= 1'b0;
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      next_RxBits <= 2'b00;
      next_RXSameBitCount <= 4'h0;
      next_RXBitCount <= 4'h0;
      next_oldRXBits <= 2'b00;
      next_RXByte <= 8'h00;
      next_bitStuffError <= 1'b0;
      next_resumeWaitCnt <= 5'h0;
      next_processRxBitRdy <= 1'b1;
      NextState_prRxBit <= `WAIT_BITS;
    end
    `WAIT_BITS:
      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
      begin
        NextState_prRxBit <= `RES_RX_CHK;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
      begin
        NextState_prRxBit <= `DATA_RX_CHK_SE0;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
      begin
        NextState_prRxBit <= `IDLE_CHK_KBIT;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
      begin
        NextState_prRxBit <= `RES_END_CHK1;
        next_RxBits <= RxBitsIn;
        next_processRxBitRdy <= 1'b0;
      end
    `IDLE_FIRST_BIT:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
      next_RXSameBitCount <= 4'h0;
      next_RXBitCount <= 4'h1;
      next_oldRXBits <= RxBits;
      //zero is always the first RZ data bit of a new packet
      next_RXByte <= 8'h00;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `IDLE_CHK_KBIT:
      if ((RxBits == KBit) && (RxWireActive == 1'b1))
        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
      else
      begin
        NextState_prRxBit <= `WAIT_BITS;
        next_processRxBitRdy <= 1'b1;
      end
    `IDLE_WAIT_PRB_RDY:
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `IDLE_FIRST_BIT;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_START;
        //start of packet
        next_processRxByteWEn <= 1'b1;
      end
    `DATA_RX_LAST_BIT:
    begin
      next_processRxByteWEn <= 1'b0;
      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_CHK_SE0:
    begin
      next_bitStuffError <= 1'b0;
      if (RxBits == `SE0)
        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
      else
      begin
        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
        begin
          next_RXSameBitCount <= RXSameBitCount + 1'b1;
            //inc 'RXSameBitCount'
            if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
            next_bitStuffError <= 1'b1;
                //flag 'bitStuffError'
            else                                          //else no bit stuffing error
            begin
            next_RXBitCount <= RXBitCount + 1'b1;
                if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
              next_processRxBitRdy <= 1'b1;
                    //early indication of ready
                        end
            next_RXByte <= { 1'b1, RXByte[7:1]};
                //RZ bit = 1 (ie no change in 'RxBits')
            end
        end
        else                                            //else current 'RxBits' are different from old 'RxBits'
        begin
            if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
            begin
            next_RXBitCount <= RXBitCount + 1'b1;
                if (RXBitCount != 4'h7) begin
              next_processRxBitRdy <= 1'b1;
                    //early indication of ready
                        end
            next_RXByte <= {1'b0, RXByte[7:1]};
                //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
            end
           next_RXSameBitCount <= 4'h0;
              //reset 'RXSameBitCount'
        end
        next_oldRXBits <= RxBits;
      end
    end
    `DATA_RX_WAIT_PRB_RDY:
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_LAST_BIT;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_STOP;
        //end of packet
        next_processRxByteWEn <= 1'b1;
      end
    `DATA_RX_DATA_DESTUFF:
      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
      else if (bitStuffError == 1'b1)
        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
      else
      begin
        NextState_prRxBit <= `WAIT_BITS;
        next_processRxBitRdy <= 1'b1;
      end
    `DATA_RX_BYTE_SEND2:
    begin
      next_processRxByteWEn <= 1'b0;
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_BYTE_WAIT_RDY:
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
        next_RXBitCount <= 4'h0;
        next_RxDataOut <= RXByte;
        next_RxCtrlOut <= `DATA_STREAM;
        next_processRxByteWEn <= 1'b1;
      end
    `DATA_RX_ERROR_CHK_RES:
    begin
      next_processRxByteWEn <= 1'b0;
      if (RxBits == JBit)                           //if current bit is a JBit, then
        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
          //next state is idle
      else                                          //else
      begin
        next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
          //check for resume
        next_resumeWaitCnt <= 5'h0;
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `DATA_RX_ERROR_WAIT_RDY:
      if (processRxByteRdy == 1'b1)
      begin
        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
        next_RxDataOut <= 8'h00;
        //redundant data
        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
        next_processRxByteWEn <= 1'b1;
      end
    `RES_RX_CHK:
    begin
      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
      else
      begin
        next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
          //if we've waited long enough, then
          if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
          begin
          next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
          next_resumeDetected <= 1'b1;
              //report resume detected
          end
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
    `RES_END_CHK1:
    begin
      if (RxBits != KBit)  //line must leave KBit state for the end of resume
      begin
        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
        next_resumeDetected <= 1'b0;
          //clear resume detected flag
      end
      NextState_prRxBit <= `WAIT_BITS;
      next_processRxBitRdy <= 1'b1;
    end
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prRxBit_CurrentState
  if (rst)
    CurrState_prRxBit <= `START;
  else
    CurrState_prRxBit <= NextState_prRxBit;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prRxBit_RegOutput
  if (rst)
  begin
    RXBitStMachCurrState <= `IDLE_BIT_ST;
    RxBits <= 2'b00;
    RXSameBitCount <= 4'h0;
    RXBitCount <= 4'h0;
    oldRXBits <= 2'b00;
    RXByte <= 8'h00;
    bitStuffError <= 1'b0;
    resumeWaitCnt <= 5'h0;
    processRxByteWEn <= 1'b0;
    RxCtrlOut <= 8'h00;
    RxDataOut <= 8'h00;
    resumeDetected <= 1'b0;
    processRxBitRdy <= 1'b1;
  end
  else
  begin
    RXBitStMachCurrState <= next_RXBitStMachCurrState;
    RxBits <= next_RxBits;
    RXSameBitCount <= next_RXSameBitCount;
    RXBitCount <= next_RXBitCount;
    oldRXBits <= next_oldRXBits;
    RXByte <= next_RXByte;
    bitStuffError <= next_bitStuffError;
    resumeWaitCnt <= next_resumeWaitCnt;
    processRxByteWEn <= next_processRxByteWEn;
    RxCtrlOut <= next_RxCtrlOut;
    RxDataOut <= next_RxDataOut;
    resumeDetected <= next_resumeDetected;
    processRxBitRdy <= next_processRxBitRdy;
  end
end
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [processRxBit_simlib.v] - Blame information for rev 673

Line No.	Rev	Author	Line
1	408	julius
2			`// File : ../RTL/serialInterfaceEngine/processRxBit.v`
3			`// Generated : 11/10/06 05:37:22`
4			`// From : ../RTL/serialInterfaceEngine/processRxBit.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// processrxbit`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`include "timescale.v"
51			`include "usbSerialInterfaceEngine_h.v"
52
53
54			`module processRxBit_simlib (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);`
55			`input [1:0] JBit;`
56			`input [1:0] KBit;`
57			`input [1:0] RxBitsIn;`
58			`input RxWireActive;`
59			`input clk;`
60			`input processRxBitsWEn;`
61			`input processRxByteRdy;`
62			`input rst;`
63			`output [7:0] RxCtrlOut;`
64			`output [7:0] RxDataOut;`
65			`output processRxBitRdy;`
66			`output processRxByteWEn;`
67			`output resumeDetected;`
68
69			`wire [1:0] JBit;`
70			`wire [1:0] KBit;`
71			`wire [1:0] RxBitsIn;`
72			`reg [7:0] RxCtrlOut, next_RxCtrlOut;`
73			`reg [7:0] RxDataOut, next_RxDataOut;`
74			`wire RxWireActive;`
75			`wire clk;`
76			`reg processRxBitRdy, next_processRxBitRdy;`
77			`wire processRxBitsWEn;`
78			`wire processRxByteRdy;`
79			`reg processRxByteWEn, next_processRxByteWEn;`
80			`reg resumeDetected, next_resumeDetected;`
81			`wire rst;`
82
83			`// diagram signals declarations`
84			`reg [3:0]RXBitCount, next_RXBitCount;`
85			`reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;`
86			`reg [7:0]RXByte, next_RXByte;`
87			`reg [3:0]RXSameBitCount, next_RXSameBitCount;`
88			`reg [1:0]RxBits, next_RxBits;`
89			`reg bitStuffError, next_bitStuffError;`
90			`reg [1:0]oldRXBits, next_oldRXBits;`
91			`reg [4:0]resumeWaitCnt, next_resumeWaitCnt;`
92
93			`// BINARY ENCODED state machine: prRxBit`
94			`// State codes definitions:`
95			`define START 4'b0000
96			`define IDLE_FIRST_BIT 4'b0001
97			`define WAIT_BITS 4'b0010
98			`define IDLE_CHK_KBIT 4'b0011
99			`define DATA_RX_LAST_BIT 4'b0100
100			`define DATA_RX_CHK_SE0 4'b0101
101			`define DATA_RX_DATA_DESTUFF 4'b0110
102			`define DATA_RX_BYTE_SEND2 4'b0111
103			`define DATA_RX_BYTE_WAIT_RDY 4'b1000
104			`define RES_RX_CHK 4'b1001
105			`define DATA_RX_ERROR_CHK_RES 4'b1010
106			`define RES_END_CHK1 4'b1011
107			`define IDLE_WAIT_PRB_RDY 4'b1100
108			`define DATA_RX_WAIT_PRB_RDY 4'b1101
109			`define DATA_RX_ERROR_WAIT_RDY 4'b1110
110
111			`reg [3:0] CurrState_prRxBit;`
112			`reg [3:0] NextState_prRxBit;`
113
114
115			`//--------------------------------------------------------------------`
116			`// Machine: prRxBit`
117			`//--------------------------------------------------------------------`
118			`//----------------------------------`
119			`// Next State Logic (combinatorial)`
120			`//----------------------------------`
121			`always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)`
122			`begin : prRxBit_NextState`
123			`NextState_prRxBit <= CurrState_prRxBit;`
124			`// Set default values for outputs and signals`
125			`next_processRxByteWEn <= processRxByteWEn;`
126			`next_RxCtrlOut <= RxCtrlOut;`
127			`next_RxDataOut <= RxDataOut;`
128			`next_resumeDetected <= resumeDetected;`
129			`next_RXBitStMachCurrState <= RXBitStMachCurrState;`
130			`next_RxBits <= RxBits;`
131			`next_RXSameBitCount <= RXSameBitCount;`
132			`next_RXBitCount <= RXBitCount;`
133			`next_oldRXBits <= oldRXBits;`
134			`next_RXByte <= RXByte;`
135			`next_bitStuffError <= bitStuffError;`
136			`next_resumeWaitCnt <= resumeWaitCnt;`
137			`next_processRxBitRdy <= processRxBitRdy;`
138			`case (CurrState_prRxBit)`
139			`START:
140			`begin`
141			`next_processRxByteWEn <= 1'b0;`
142			`next_RxCtrlOut <= 8'h00;`
143			`next_RxDataOut <= 8'h00;`
144			`next_resumeDetected <= 1'b0;`
145			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
146			`next_RxBits <= 2'b00;`
147			`next_RXSameBitCount <= 4'h0;`
148			`next_RXBitCount <= 4'h0;`
149			`next_oldRXBits <= 2'b00;`
150			`next_RXByte <= 8'h00;`
151			`next_bitStuffError <= 1'b0;`
152			`next_resumeWaitCnt <= 5'h0;`
153			`next_processRxBitRdy <= 1'b1;`
154			NextState_prRxBit <= `WAIT_BITS;
155			`end`
156			`WAIT_BITS:
157			if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
158			`begin`
159			NextState_prRxBit <= `RES_RX_CHK;
160			`next_RxBits <= RxBitsIn;`
161			`next_processRxBitRdy <= 1'b0;`
162			`end`
163			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
164			`begin`
165			NextState_prRxBit <= `DATA_RX_CHK_SE0;
166			`next_RxBits <= RxBitsIn;`
167			`next_processRxBitRdy <= 1'b0;`
168			`end`
169			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
170			`begin`
171			NextState_prRxBit <= `IDLE_CHK_KBIT;
172			`next_RxBits <= RxBitsIn;`
173			`next_processRxBitRdy <= 1'b0;`
174			`end`
175			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
176			`begin`
177			NextState_prRxBit <= `RES_END_CHK1;
178			`next_RxBits <= RxBitsIn;`
179			`next_processRxBitRdy <= 1'b0;`
180			`end`
181			`IDLE_FIRST_BIT:
182			`begin`
183			`next_processRxByteWEn <= 1'b0;`
184			next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
185			`next_RXSameBitCount <= 4'h0;`
186			`next_RXBitCount <= 4'h1;`
187			`next_oldRXBits <= RxBits;`
188			`//zero is always the first RZ data bit of a new packet`
189			`next_RXByte <= 8'h00;`
190			NextState_prRxBit <= `WAIT_BITS;
191			`next_processRxBitRdy <= 1'b1;`
192			`end`
193			`IDLE_CHK_KBIT:
194			`if ((RxBits == KBit) && (RxWireActive == 1'b1))`
195			NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
196			`else`
197			`begin`
198			NextState_prRxBit <= `WAIT_BITS;
199			`next_processRxBitRdy <= 1'b1;`
200			`end`
201			`IDLE_WAIT_PRB_RDY:
202			`if (processRxByteRdy == 1'b1)`
203			`begin`
204			NextState_prRxBit <= `IDLE_FIRST_BIT;
205			`next_RxDataOut <= 8'h00;`
206			`//redundant data`
207			next_RxCtrlOut <= `DATA_START;
208			`//start of packet`
209			`next_processRxByteWEn <= 1'b1;`
210			`end`
211			`DATA_RX_LAST_BIT:
212			`begin`
213			`next_processRxByteWEn <= 1'b0;`
214			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
215			NextState_prRxBit <= `WAIT_BITS;
216			`next_processRxBitRdy <= 1'b1;`
217			`end`
218			`DATA_RX_CHK_SE0:
219			`begin`
220			`next_bitStuffError <= 1'b0;`
221			if (RxBits == `SE0)
222			NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
223			`else`
224			`begin`
225			NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
226			`if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then`
227			`begin`
228			`next_RXSameBitCount <= RXSameBitCount + 1'b1;`
229			`//inc 'RXSameBitCount'`
230			if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
231			`next_bitStuffError <= 1'b1;`
232			`//flag 'bitStuffError'`
233			`else //else no bit stuffing error`
234			`begin`
235			`next_RXBitCount <= RXBitCount + 1'b1;`
236			if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
237			`next_processRxBitRdy <= 1'b1;`
238			`//early indication of ready`
239			`end`
240			`next_RXByte <= { 1'b1, RXByte[7:1]};`
241			`//RZ bit = 1 (ie no change in 'RxBits')`
242			`end`
243			`end`
244			`else //else current 'RxBits' are different from old 'RxBits'`
245			`begin`
246			if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
247			`begin`
248			`next_RXBitCount <= RXBitCount + 1'b1;`
249			`if (RXBitCount != 4'h7) begin`
250			`next_processRxBitRdy <= 1'b1;`
251			`//early indication of ready`
252			`end`
253			`next_RXByte <= {1'b0, RXByte[7:1]};`
254			`//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')`
255			`end`
256			`next_RXSameBitCount <= 4'h0;`
257			`//reset 'RXSameBitCount'`
258			`end`
259			`next_oldRXBits <= RxBits;`
260			`end`
261			`end`
262			`DATA_RX_WAIT_PRB_RDY:
263			`if (processRxByteRdy == 1'b1)`
264			`begin`
265			NextState_prRxBit <= `DATA_RX_LAST_BIT;
266			`next_RxDataOut <= 8'h00;`
267			`//redundant data`
268			next_RxCtrlOut <= `DATA_STOP;
269			`//end of packet`
270			`next_processRxByteWEn <= 1'b1;`
271			`end`
272			`DATA_RX_DATA_DESTUFF:
273			`if (RXBitCount == 4'h8 & bitStuffError == 1'b0)`
274			NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
275			`else if (bitStuffError == 1'b1)`
276			NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
277			`else`
278			`begin`
279			NextState_prRxBit <= `WAIT_BITS;
280			`next_processRxBitRdy <= 1'b1;`
281			`end`
282			`DATA_RX_BYTE_SEND2:
283			`begin`
284			`next_processRxByteWEn <= 1'b0;`
285			NextState_prRxBit <= `WAIT_BITS;
286			`next_processRxBitRdy <= 1'b1;`
287			`end`
288			`DATA_RX_BYTE_WAIT_RDY:
289			`if (processRxByteRdy == 1'b1)`
290			`begin`
291			NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
292			`next_RXBitCount <= 4'h0;`
293			`next_RxDataOut <= RXByte;`
294			next_RxCtrlOut <= `DATA_STREAM;
295			`next_processRxByteWEn <= 1'b1;`
296			`end`
297			`DATA_RX_ERROR_CHK_RES:
298			`begin`
299			`next_processRxByteWEn <= 1'b0;`
300			`if (RxBits == JBit) //if current bit is a JBit, then`
301			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
302			`//next state is idle`
303			`else //else`
304			`begin`
305			next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
306			`//check for resume`
307			`next_resumeWaitCnt <= 5'h0;`
308			`end`
309			NextState_prRxBit <= `WAIT_BITS;
310			`next_processRxBitRdy <= 1'b1;`
311			`end`
312			`DATA_RX_ERROR_WAIT_RDY:
313			`if (processRxByteRdy == 1'b1)`
314			`begin`
315			NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
316			`next_RxDataOut <= 8'h00;`
317			`//redundant data`
318			next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
319			`next_processRxByteWEn <= 1'b1;`
320			`end`
321			`RES_RX_CHK:
322			`begin`
323			`if (RxBits != KBit) //can only be a resume if line remains in Kbit state`
324			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
325			`else`
326			`begin`
327			`next_resumeWaitCnt <= resumeWaitCnt + 1'b1;`
328			`//if we've waited long enough, then`
329			if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
330			`begin`
331			next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
332			`next_resumeDetected <= 1'b1;`
333			`//report resume detected`
334			`end`
335			`end`
336			NextState_prRxBit <= `WAIT_BITS;
337			`next_processRxBitRdy <= 1'b1;`
338			`end`
339			`RES_END_CHK1:
340			`begin`
341			`if (RxBits != KBit) //line must leave KBit state for the end of resume`
342			`begin`
343			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
344			`next_resumeDetected <= 1'b0;`
345			`//clear resume detected flag`
346			`end`
347			NextState_prRxBit <= `WAIT_BITS;
348			`next_processRxBitRdy <= 1'b1;`
349			`end`
350			`endcase`
351			`end`
352
353			`//----------------------------------`
354			`// Current State Logic (sequential)`
355			`//----------------------------------`
356			`always @ (posedge clk)`
357			`begin : prRxBit_CurrentState`
358			`if (rst)`
359			CurrState_prRxBit <= `START;
360			`else`
361			`CurrState_prRxBit <= NextState_prRxBit;`
362			`end`
363
364			`//----------------------------------`
365			`// Registered outputs logic`
366			`//----------------------------------`
367			`always @ (posedge clk)`
368			`begin : prRxBit_RegOutput`
369			`if (rst)`
370			`begin`
371			RXBitStMachCurrState <= `IDLE_BIT_ST;
372			`RxBits <= 2'b00;`
373			`RXSameBitCount <= 4'h0;`
374			`RXBitCount <= 4'h0;`
375			`oldRXBits <= 2'b00;`
376			`RXByte <= 8'h00;`
377			`bitStuffError <= 1'b0;`
378			`resumeWaitCnt <= 5'h0;`
379			`processRxByteWEn <= 1'b0;`
380			`RxCtrlOut <= 8'h00;`
381			`RxDataOut <= 8'h00;`
382			`resumeDetected <= 1'b0;`
383			`processRxBitRdy <= 1'b1;`
384			`end`
385			`else`
386			`begin`
387			`RXBitStMachCurrState <= next_RXBitStMachCurrState;`
388			`RxBits <= next_RxBits;`
389			`RXSameBitCount <= next_RXSameBitCount;`
390			`RXBitCount <= next_RXBitCount;`
391			`oldRXBits <= next_oldRXBits;`
392			`RXByte <= next_RXByte;`
393			`bitStuffError <= next_bitStuffError;`
394			`resumeWaitCnt <= next_resumeWaitCnt;`
395			`processRxByteWEn <= next_processRxByteWEn;`
396			`RxCtrlOut <= next_RxCtrlOut;`
397			`RxDataOut <= next_RxDataOut;`
398			`resumeDetected <= next_resumeDetected;`
399			`processRxBitRdy <= next_processRxBitRdy;`
400			`end`
401			`end`
402
403			`endmodule`