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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [processRxByte_simlib.v] - Blame information for rev 476

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// File        : ../RTL/serialInterfaceEngine/processRxByte.v
// Generated   : 11/10/06 05:37:22
// From        : ../RTL/serialInterfaceEngine/processRxByte.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processRxByte
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module processRxByte_simlib (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC);
input   [15:0] CRC16Result;
input   CRC16UpdateRdy;
input   [4:0] CRC5Result;
input   CRC5UpdateRdy;
input   [7:0] RxByteIn;
input   [7:0] RxCtrlIn;
input   clk;
input   processRxDataInWEn;
input   rst;
output  CRC16En;
output  CRC5En;
output  CRC5_8Bit;
output  [7:0] CRCData;
output  [7:0] RxCtrlOut;
output  RxDataOutWEn;
output  [7:0] RxDataOut;
output  processRxByteRdy;
output  rstCRC;
 
reg     CRC16En, next_CRC16En;
wire    [15:0] CRC16Result;
wire    CRC16UpdateRdy;
reg     CRC5En, next_CRC5En;
wire    [4:0] CRC5Result;
wire    CRC5UpdateRdy;
reg     CRC5_8Bit, next_CRC5_8Bit;
reg     [7:0] CRCData, next_CRCData;
wire    [7:0] RxByteIn;
wire    [7:0] RxCtrlIn;
reg     [7:0] RxCtrlOut, next_RxCtrlOut;
reg     RxDataOutWEn, next_RxDataOutWEn;
reg     [7:0] RxDataOut, next_RxDataOut;
wire    clk;
reg     processRxByteRdy, next_processRxByteRdy;
wire    processRxDataInWEn;
wire    rst;
reg     rstCRC, next_rstCRC;
 
// diagram signals declarations
reg  ACKRxed, next_ACKRxed;
reg  CRCError, next_CRCError;
reg  NAKRxed, next_NAKRxed;
reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
reg  [7:0]RxByte, next_RxByte;
reg  [7:0]RxCtrl, next_RxCtrl;
reg  RxOverflow, next_RxOverflow;
reg  [7:0]RxStatus;
reg  RxTimeOut, next_RxTimeOut;
reg  Signal1, next_Signal1;
reg  bitStuffError, next_bitStuffError;
reg  dataSequence, next_dataSequence;
reg  stallRxed, next_stallRxed;
 
// BINARY ENCODED state machine: prRxByte
// State codes definitions:
`define CHK_ST 4'b0000
`define START_PRBY 4'b0001
`define WAIT_BYTE 4'b0010
`define IDLE_CHK_START 4'b0011
`define CHK_SYNC_DO 4'b0100
`define CHK_PID_DO_CHK 4'b0101
`define CHK_PID_FIRST_BYTE_PROC 4'b0110
`define HSHAKE_FIN 4'b0111
`define HSHAKE_CHK 4'b1000
`define TOKEN_CHK_STRM 4'b1001
`define TOKEN_FIN 4'b1010
`define DATA_FIN 4'b1011
`define DATA_CHK_STRM 4'b1100
`define TOKEN_WAIT_CRC 4'b1101
`define DATA_WAIT_CRC 4'b1110
 
reg [3:0] CurrState_prRxByte;
reg [3:0] NextState_prRxByte;
 
// Diagram actions (continuous assignments allowed only: assign ...)
 
always @
(next_CRCError or next_bitStuffError or
  next_RxOverflow or next_NAKRxed or
  next_stallRxed or next_ACKRxed or
  next_dataSequence)
begin
    RxStatus <=
    {1'b0, next_dataSequence,
    next_ACKRxed,
    next_stallRxed, next_NAKRxed,
    next_RxOverflow,
    next_bitStuffError, next_CRCError };
end
 
//--------------------------------------------------------------------
// Machine: prRxByte
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
begin : prRxByte_NextState
  NextState_prRxByte <= CurrState_prRxByte;
  // Set default values for outputs and signals
  next_RxByte <= RxByte;
  next_RxCtrl <= RxCtrl;
  next_RXByteStMachCurrState <= RXByteStMachCurrState;
  next_CRCError <= CRCError;
  next_bitStuffError <= bitStuffError;
  next_RxOverflow <= RxOverflow;
  next_RxTimeOut <= RxTimeOut;
  next_NAKRxed <= NAKRxed;
  next_stallRxed <= stallRxed;
  next_ACKRxed <= ACKRxed;
  next_dataSequence <= dataSequence;
  next_RxDataOut <= RxDataOut;
  next_RxCtrlOut <= RxCtrlOut;
  next_RxDataOutWEn <= RxDataOutWEn;
  next_rstCRC <= rstCRC;
  next_CRCData <= CRCData;
  next_CRC5En <= CRC5En;
  next_CRC5_8Bit <= CRC5_8Bit;
  next_CRC16En <= CRC16En;
  next_RXDataByteCnt <= RXDataByteCnt;
  next_processRxByteRdy <= processRxByteRdy;
  case (CurrState_prRxByte)
    `CHK_ST:
      if (RXByteStMachCurrState == `HS_BYTE_ST)
        NextState_prRxByte <= `HSHAKE_CHK;
      else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
        NextState_prRxByte <= `TOKEN_WAIT_CRC;
      else if (RXByteStMachCurrState == `DATA_BYTE_ST)
        NextState_prRxByte <= `DATA_WAIT_CRC;
      else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
        NextState_prRxByte <= `IDLE_CHK_START;
      else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
        NextState_prRxByte <= `CHK_SYNC_DO;
      else if (RXByteStMachCurrState == `CHECK_PID_ST)
        NextState_prRxByte <= `CHK_PID_DO_CHK;
    `START_PRBY:
    begin
      next_RxByte <= 8'h00;
      next_RxCtrl <= 8'h00;
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      next_CRCError <= 1'b0;
      next_bitStuffError <= 1'b0;
      next_RxOverflow <= 1'b0;
      next_RxTimeOut <= 1'b0;
      next_NAKRxed <= 1'b0;
      next_stallRxed <= 1'b0;
      next_ACKRxed <= 1'b0;
      next_dataSequence <= 1'b0;
      next_RxDataOut <= 8'h00;
      next_RxCtrlOut <= 8'h00;
      next_RxDataOutWEn <= 1'b0;
      next_rstCRC <= 1'b0;
      next_CRCData <= 8'h00;
      next_CRC5En <= 1'b0;
      next_CRC5_8Bit <= 1'b0;
      next_CRC16En <= 1'b0;
      next_RXDataByteCnt <= 10'h00;
      next_processRxByteRdy <= 1'b1;
      NextState_prRxByte <= `WAIT_BYTE;
    end
    `WAIT_BYTE:
      if (processRxDataInWEn == 1'b1)
      begin
        NextState_prRxByte <= `CHK_ST;
        next_RxByte <= RxByteIn;
        next_RxCtrl <= RxCtrlIn;
        next_processRxByteRdy <= 1'b0;
      end
    `HSHAKE_FIN:
    begin
      next_RxDataOutWEn <= 1'b0;
      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `HSHAKE_CHK:
    begin
      NextState_prRxByte <= `HSHAKE_FIN;
      if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
        next_RxOverflow <= 1'b1;
      next_RxDataOut <= RxStatus;
      next_RxCtrlOut <= `RX_PACKET_STOP;
      next_RxDataOutWEn <= 1'b1;
    end
    `CHK_PID_DO_CHK:
      if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
      begin
        NextState_prRxByte <= `WAIT_BYTE;
        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
        next_processRxByteRdy <= 1'b1;
      end
      else
      begin
        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
        next_CRCError <= 1'b0;
        next_bitStuffError <= 1'b0;
        next_RxOverflow <= 1'b0;
        next_NAKRxed <= 1'b0;
        next_stallRxed <= 1'b0;
        next_ACKRxed <= 1'b0;
        next_dataSequence <= 1'b0;
        next_RxTimeOut <= 1'b0;
        next_RXDataByteCnt <= 10'h000;
        next_RxDataOut <= RxByte;
        next_RxCtrlOut <= `RX_PACKET_START;
        next_RxDataOutWEn <= 1'b1;
        next_rstCRC <= 1'b1;
      end
    `CHK_PID_FIRST_BYTE_PROC:
    begin
      next_rstCRC <= 1'b0;
      next_RxDataOutWEn <= 1'b0;
      case (RxByte[1:0] )
          `SPECIAL:                              //Special PID.
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          `TOKEN:                                //Token PID
          begin
          next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
          next_RXDataByteCnt <= 0;
          end
          `HANDSHAKE:                            //Handshake PID
          begin
              case (RxByte[3:2] )
                  2'b00:
              next_ACKRxed <= 1'b1;
                  2'b10:
              next_NAKRxed <= 1'b1;
                  2'b11:
              next_stallRxed <= 1'b1;
                  default:
                  begin
                      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
                  end
              endcase
          next_RXByteStMachCurrState <= `HS_BYTE_ST;
          end
          `DATA:                                  //Data PID
          begin
              case (RxByte[3:2] )
                  2'b00:
              next_dataSequence <= 1'b0;
                  2'b10:
              next_dataSequence <= 1'b1;
                  default:
                      $display ("Invalid DATA PID detected in ProcessRXByte\n");
              endcase
          next_RXByteStMachCurrState <= `DATA_BYTE_ST;
          next_RXDataByteCnt <= 0;
          end
      endcase
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `DATA_FIN:
    begin
      next_CRC16En <= 1'b0;
      next_RxDataOutWEn <= 1'b0;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `DATA_CHK_STRM:
    begin
      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
      case (RxCtrl)
          `DATA_STOP:
          begin
              if (CRC16Result != 16'hb001)
            next_CRCError <= 1'b1;
          next_RxDataOut <= RxStatus;
          next_RxCtrlOut <= `RX_PACKET_STOP;
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
          `DATA_BIT_STUFF_ERROR:
          begin
          next_bitStuffError <= 1'b1;
          next_RxDataOut <= RxStatus;
          next_RxCtrlOut <= `RX_PACKET_STOP;
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
          `DATA_STREAM:
          begin
          next_RxDataOut <= RxByte;
          next_RxCtrlOut <= `RX_PACKET_STREAM;
          next_CRCData <= RxByte;
          next_CRC16En <= 1'b1;
          end
          default:
          begin
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
      endcase
      next_RxDataOutWEn <= 1'b1;
      NextState_prRxByte <= `DATA_FIN;
    end
    `DATA_WAIT_CRC:
      if (CRC16UpdateRdy == 1'b1)
        NextState_prRxByte <= `DATA_CHK_STRM;
    `TOKEN_CHK_STRM:
    begin
      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
      case (RxCtrl)
          `DATA_STOP:
          begin
              if (CRC5Result != 5'h6)
            next_CRCError <= 1'b1;
          next_RxDataOut <= RxStatus;
          next_RxCtrlOut <= `RX_PACKET_STOP;
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
          `DATA_BIT_STUFF_ERROR:
          begin
          next_bitStuffError <= 1'b1;
          next_RxDataOut <= RxStatus;
          next_RxCtrlOut <= `RX_PACKET_STOP;
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
          `DATA_STREAM:
          begin
              if (RXDataByteCnt > 10'h2)
              begin
            next_RxOverflow <= 1'b1;
            next_RxDataOut <= RxStatus;
            next_RxCtrlOut <= `RX_PACKET_STOP;
            next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
              end
              else
              begin
            next_RxDataOut <= RxByte;
            next_RxCtrlOut <= `RX_PACKET_STREAM;
            next_CRCData <= RxByte;
            next_CRC5_8Bit <= 1'b1;
            next_CRC5En <= 1'b1;
              end
          end
          default:
          begin
          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
          end
      endcase
      next_RxDataOutWEn <= 1'b1;
      NextState_prRxByte <= `TOKEN_FIN;
    end
    `TOKEN_FIN:
    begin
      next_CRC5En <= 1'b0;
      next_RxDataOutWEn <= 1'b0;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `TOKEN_WAIT_CRC:
      if (CRC5UpdateRdy == 1'b1)
        NextState_prRxByte <= `TOKEN_CHK_STRM;
    `CHK_SYNC_DO:
    begin
      if (RxByte == `SYNC_BYTE)
        next_RXByteStMachCurrState <= `CHECK_PID_ST;
      else
        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
    `IDLE_CHK_START:
    begin
      if (RxCtrl == `DATA_START)
        next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
      NextState_prRxByte <= `WAIT_BYTE;
      next_processRxByteRdy <= 1'b1;
    end
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prRxByte_CurrentState
  if (rst)
    CurrState_prRxByte <= `START_PRBY;
  else
    CurrState_prRxByte <= NextState_prRxByte;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prRxByte_RegOutput
  if (rst)
  begin
    RxByte <= 8'h00;
    RxCtrl <= 8'h00;
    RXByteStMachCurrState <= `IDLE_BYTE_ST;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    RxOverflow <= 1'b0;
    RxTimeOut <= 1'b0;
    NAKRxed <= 1'b0;
    stallRxed <= 1'b0;
    ACKRxed <= 1'b0;
    dataSequence <= 1'b0;
    RXDataByteCnt <= 10'h00;
    RxDataOut <= 8'h00;
    RxCtrlOut <= 8'h00;
    RxDataOutWEn <= 1'b0;
    rstCRC <= 1'b0;
    CRCData <= 8'h00;
    CRC5En <= 1'b0;
    CRC5_8Bit <= 1'b0;
    CRC16En <= 1'b0;
    processRxByteRdy <= 1'b1;
  end
  else
  begin
    RxByte <= next_RxByte;
    RxCtrl <= next_RxCtrl;
    RXByteStMachCurrState <= next_RXByteStMachCurrState;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    RxOverflow <= next_RxOverflow;
    RxTimeOut <= next_RxTimeOut;
    NAKRxed <= next_NAKRxed;
    stallRxed <= next_stallRxed;
    ACKRxed <= next_ACKRxed;
    dataSequence <= next_dataSequence;
    RXDataByteCnt <= next_RXDataByteCnt;
    RxDataOut <= next_RxDataOut;
    RxCtrlOut <= next_RxCtrlOut;
    RxDataOutWEn <= next_RxDataOutWEn;
    rstCRC <= next_rstCRC;
    CRCData <= next_CRCData;
    CRC5En <= next_CRC5En;
    CRC5_8Bit <= next_CRC5_8Bit;
    CRC16En <= next_CRC16En;
    processRxByteRdy <= next_processRxByteRdy;
  end
end
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [processRxByte_simlib.v] - Blame information for rev 476

Line No.	Rev	Author	Line
1	408	julius
2			`// File : ../RTL/serialInterfaceEngine/processRxByte.v`
3			`// Generated : 11/10/06 05:37:22`
4			`// From : ../RTL/serialInterfaceEngine/processRxByte.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// processRxByte`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`include "timescale.v"
51			`include "usbSerialInterfaceEngine_h.v"
52			`include "usbConstants_h.v"
53
54			`module processRxByte_simlib (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC);`
55			`input [15:0] CRC16Result;`
56			`input CRC16UpdateRdy;`
57			`input [4:0] CRC5Result;`
58			`input CRC5UpdateRdy;`
59			`input [7:0] RxByteIn;`
60			`input [7:0] RxCtrlIn;`
61			`input clk;`
62			`input processRxDataInWEn;`
63			`input rst;`
64			`output CRC16En;`
65			`output CRC5En;`
66			`output CRC5_8Bit;`
67			`output [7:0] CRCData;`
68			`output [7:0] RxCtrlOut;`
69			`output RxDataOutWEn;`
70			`output [7:0] RxDataOut;`
71			`output processRxByteRdy;`
72			`output rstCRC;`
73
74			`reg CRC16En, next_CRC16En;`
75			`wire [15:0] CRC16Result;`
76			`wire CRC16UpdateRdy;`
77			`reg CRC5En, next_CRC5En;`
78			`wire [4:0] CRC5Result;`
79			`wire CRC5UpdateRdy;`
80			`reg CRC5_8Bit, next_CRC5_8Bit;`
81			`reg [7:0] CRCData, next_CRCData;`
82			`wire [7:0] RxByteIn;`
83			`wire [7:0] RxCtrlIn;`
84			`reg [7:0] RxCtrlOut, next_RxCtrlOut;`
85			`reg RxDataOutWEn, next_RxDataOutWEn;`
86			`reg [7:0] RxDataOut, next_RxDataOut;`
87			`wire clk;`
88			`reg processRxByteRdy, next_processRxByteRdy;`
89			`wire processRxDataInWEn;`
90			`wire rst;`
91			`reg rstCRC, next_rstCRC;`
92
93			`// diagram signals declarations`
94			`reg ACKRxed, next_ACKRxed;`
95			`reg CRCError, next_CRCError;`
96			`reg NAKRxed, next_NAKRxed;`
97			`reg [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;`
98			`reg [9:0]RXDataByteCnt, next_RXDataByteCnt;`
99			`reg [7:0]RxByte, next_RxByte;`
100			`reg [7:0]RxCtrl, next_RxCtrl;`
101			`reg RxOverflow, next_RxOverflow;`
102			`reg [7:0]RxStatus;`
103			`reg RxTimeOut, next_RxTimeOut;`
104			`reg Signal1, next_Signal1;`
105			`reg bitStuffError, next_bitStuffError;`
106			`reg dataSequence, next_dataSequence;`
107			`reg stallRxed, next_stallRxed;`
108
109			`// BINARY ENCODED state machine: prRxByte`
110			`// State codes definitions:`
111			`define CHK_ST 4'b0000
112			`define START_PRBY 4'b0001
113			`define WAIT_BYTE 4'b0010
114			`define IDLE_CHK_START 4'b0011
115			`define CHK_SYNC_DO 4'b0100
116			`define CHK_PID_DO_CHK 4'b0101
117			`define CHK_PID_FIRST_BYTE_PROC 4'b0110
118			`define HSHAKE_FIN 4'b0111
119			`define HSHAKE_CHK 4'b1000
120			`define TOKEN_CHK_STRM 4'b1001
121			`define TOKEN_FIN 4'b1010
122			`define DATA_FIN 4'b1011
123			`define DATA_CHK_STRM 4'b1100
124			`define TOKEN_WAIT_CRC 4'b1101
125			`define DATA_WAIT_CRC 4'b1110
126
127			`reg [3:0] CurrState_prRxByte;`
128			`reg [3:0] NextState_prRxByte;`
129
130			`// Diagram actions (continuous assignments allowed only: assign ...)`
131
132			`always @`
133			`(next_CRCError or next_bitStuffError or`
134			`next_RxOverflow or next_NAKRxed or`
135			`next_stallRxed or next_ACKRxed or`
136			`next_dataSequence)`
137			`begin`
138			`RxStatus <=`
139			`{1'b0, next_dataSequence,`
140			`next_ACKRxed,`
141			`next_stallRxed, next_NAKRxed,`
142			`next_RxOverflow,`
143			`next_bitStuffError, next_CRCError };`
144			`end`
145
146			`//--------------------------------------------------------------------`
147			`// Machine: prRxByte`
148			`//--------------------------------------------------------------------`
149			`//----------------------------------`
150			`// Next State Logic (combinatorial)`
151			`//----------------------------------`
152			`always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)`
153			`begin : prRxByte_NextState`
154			`NextState_prRxByte <= CurrState_prRxByte;`
155			`// Set default values for outputs and signals`
156			`next_RxByte <= RxByte;`
157			`next_RxCtrl <= RxCtrl;`
158			`next_RXByteStMachCurrState <= RXByteStMachCurrState;`
159			`next_CRCError <= CRCError;`
160			`next_bitStuffError <= bitStuffError;`
161			`next_RxOverflow <= RxOverflow;`
162			`next_RxTimeOut <= RxTimeOut;`
163			`next_NAKRxed <= NAKRxed;`
164			`next_stallRxed <= stallRxed;`
165			`next_ACKRxed <= ACKRxed;`
166			`next_dataSequence <= dataSequence;`
167			`next_RxDataOut <= RxDataOut;`
168			`next_RxCtrlOut <= RxCtrlOut;`
169			`next_RxDataOutWEn <= RxDataOutWEn;`
170			`next_rstCRC <= rstCRC;`
171			`next_CRCData <= CRCData;`
172			`next_CRC5En <= CRC5En;`
173			`next_CRC5_8Bit <= CRC5_8Bit;`
174			`next_CRC16En <= CRC16En;`
175			`next_RXDataByteCnt <= RXDataByteCnt;`
176			`next_processRxByteRdy <= processRxByteRdy;`
177			`case (CurrState_prRxByte)`
178			`CHK_ST:
179			if (RXByteStMachCurrState == `HS_BYTE_ST)
180			NextState_prRxByte <= `HSHAKE_CHK;
181			else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
182			NextState_prRxByte <= `TOKEN_WAIT_CRC;
183			else if (RXByteStMachCurrState == `DATA_BYTE_ST)
184			NextState_prRxByte <= `DATA_WAIT_CRC;
185			else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
186			NextState_prRxByte <= `IDLE_CHK_START;
187			else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
188			NextState_prRxByte <= `CHK_SYNC_DO;
189			else if (RXByteStMachCurrState == `CHECK_PID_ST)
190			NextState_prRxByte <= `CHK_PID_DO_CHK;
191			`START_PRBY:
192			`begin`
193			`next_RxByte <= 8'h00;`
194			`next_RxCtrl <= 8'h00;`
195			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
196			`next_CRCError <= 1'b0;`
197			`next_bitStuffError <= 1'b0;`
198			`next_RxOverflow <= 1'b0;`
199			`next_RxTimeOut <= 1'b0;`
200			`next_NAKRxed <= 1'b0;`
201			`next_stallRxed <= 1'b0;`
202			`next_ACKRxed <= 1'b0;`
203			`next_dataSequence <= 1'b0;`
204			`next_RxDataOut <= 8'h00;`
205			`next_RxCtrlOut <= 8'h00;`
206			`next_RxDataOutWEn <= 1'b0;`
207			`next_rstCRC <= 1'b0;`
208			`next_CRCData <= 8'h00;`
209			`next_CRC5En <= 1'b0;`
210			`next_CRC5_8Bit <= 1'b0;`
211			`next_CRC16En <= 1'b0;`
212			`next_RXDataByteCnt <= 10'h00;`
213			`next_processRxByteRdy <= 1'b1;`
214			NextState_prRxByte <= `WAIT_BYTE;
215			`end`
216			`WAIT_BYTE:
217			`if (processRxDataInWEn == 1'b1)`
218			`begin`
219			NextState_prRxByte <= `CHK_ST;
220			`next_RxByte <= RxByteIn;`
221			`next_RxCtrl <= RxCtrlIn;`
222			`next_processRxByteRdy <= 1'b0;`
223			`end`
224			`HSHAKE_FIN:
225			`begin`
226			`next_RxDataOutWEn <= 1'b0;`
227			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
228			NextState_prRxByte <= `WAIT_BYTE;
229			`next_processRxByteRdy <= 1'b1;`
230			`end`
231			`HSHAKE_CHK:
232			`begin`
233			NextState_prRxByte <= `HSHAKE_FIN;
234			if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
235			`next_RxOverflow <= 1'b1;`
236			`next_RxDataOut <= RxStatus;`
237			next_RxCtrlOut <= `RX_PACKET_STOP;
238			`next_RxDataOutWEn <= 1'b1;`
239			`end`
240			`CHK_PID_DO_CHK:
241			`if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)`
242			`begin`
243			NextState_prRxByte <= `WAIT_BYTE;
244			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
245			`next_processRxByteRdy <= 1'b1;`
246			`end`
247			`else`
248			`begin`
249			NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
250			`next_CRCError <= 1'b0;`
251			`next_bitStuffError <= 1'b0;`
252			`next_RxOverflow <= 1'b0;`
253			`next_NAKRxed <= 1'b0;`
254			`next_stallRxed <= 1'b0;`
255			`next_ACKRxed <= 1'b0;`
256			`next_dataSequence <= 1'b0;`
257			`next_RxTimeOut <= 1'b0;`
258			`next_RXDataByteCnt <= 10'h000;`
259			`next_RxDataOut <= RxByte;`
260			next_RxCtrlOut <= `RX_PACKET_START;
261			`next_RxDataOutWEn <= 1'b1;`
262			`next_rstCRC <= 1'b1;`
263			`end`
264			`CHK_PID_FIRST_BYTE_PROC:
265			`begin`
266			`next_rstCRC <= 1'b0;`
267			`next_RxDataOutWEn <= 1'b0;`
268			`case (RxByte[1:0] )`
269			`SPECIAL: //Special PID.
270			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
271			`TOKEN: //Token PID
272			`begin`
273			next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
274			`next_RXDataByteCnt <= 0;`
275			`end`
276			`HANDSHAKE: //Handshake PID
277			`begin`
278			`case (RxByte[3:2] )`
279			`2'b00:`
280			`next_ACKRxed <= 1'b1;`
281			`2'b10:`
282			`next_NAKRxed <= 1'b1;`
283			`2'b11:`
284			`next_stallRxed <= 1'b1;`
285			`default:`
286			`begin`
287			`$display ("Invalid Handshake PID detected in ProcessRXByte\n");`
288			`end`
289			`endcase`
290			next_RXByteStMachCurrState <= `HS_BYTE_ST;
291			`end`
292			`DATA: //Data PID
293			`begin`
294			`case (RxByte[3:2] )`
295			`2'b00:`
296			`next_dataSequence <= 1'b0;`
297			`2'b10:`
298			`next_dataSequence <= 1'b1;`
299			`default:`
300			`$display ("Invalid DATA PID detected in ProcessRXByte\n");`
301			`endcase`
302			next_RXByteStMachCurrState <= `DATA_BYTE_ST;
303			`next_RXDataByteCnt <= 0;`
304			`end`
305			`endcase`
306			NextState_prRxByte <= `WAIT_BYTE;
307			`next_processRxByteRdy <= 1'b1;`
308			`end`
309			`DATA_FIN:
310			`begin`
311			`next_CRC16En <= 1'b0;`
312			`next_RxDataOutWEn <= 1'b0;`
313			NextState_prRxByte <= `WAIT_BYTE;
314			`next_processRxByteRdy <= 1'b1;`
315			`end`
316			`DATA_CHK_STRM:
317			`begin`
318			`next_RXDataByteCnt <= RXDataByteCnt + 1'b1;`
319			`case (RxCtrl)`
320			`DATA_STOP:
321			`begin`
322			`if (CRC16Result != 16'hb001)`
323			`next_CRCError <= 1'b1;`
324			`next_RxDataOut <= RxStatus;`
325			next_RxCtrlOut <= `RX_PACKET_STOP;
326			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
327			`end`
328			`DATA_BIT_STUFF_ERROR:
329			`begin`
330			`next_bitStuffError <= 1'b1;`
331			`next_RxDataOut <= RxStatus;`
332			next_RxCtrlOut <= `RX_PACKET_STOP;
333			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
334			`end`
335			`DATA_STREAM:
336			`begin`
337			`next_RxDataOut <= RxByte;`
338			next_RxCtrlOut <= `RX_PACKET_STREAM;
339			`next_CRCData <= RxByte;`
340			`next_CRC16En <= 1'b1;`
341			`end`
342			`default:`
343			`begin`
344			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
345			`end`
346			`endcase`
347			`next_RxDataOutWEn <= 1'b1;`
348			NextState_prRxByte <= `DATA_FIN;
349			`end`
350			`DATA_WAIT_CRC:
351			`if (CRC16UpdateRdy == 1'b1)`
352			NextState_prRxByte <= `DATA_CHK_STRM;
353			`TOKEN_CHK_STRM:
354			`begin`
355			`next_RXDataByteCnt <= RXDataByteCnt + 1'b1;`
356			`case (RxCtrl)`
357			`DATA_STOP:
358			`begin`
359			`if (CRC5Result != 5'h6)`
360			`next_CRCError <= 1'b1;`
361			`next_RxDataOut <= RxStatus;`
362			next_RxCtrlOut <= `RX_PACKET_STOP;
363			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
364			`end`
365			`DATA_BIT_STUFF_ERROR:
366			`begin`
367			`next_bitStuffError <= 1'b1;`
368			`next_RxDataOut <= RxStatus;`
369			next_RxCtrlOut <= `RX_PACKET_STOP;
370			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
371			`end`
372			`DATA_STREAM:
373			`begin`
374			`if (RXDataByteCnt > 10'h2)`
375			`begin`
376			`next_RxOverflow <= 1'b1;`
377			`next_RxDataOut <= RxStatus;`
378			next_RxCtrlOut <= `RX_PACKET_STOP;
379			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
380			`end`
381			`else`
382			`begin`
383			`next_RxDataOut <= RxByte;`
384			next_RxCtrlOut <= `RX_PACKET_STREAM;
385			`next_CRCData <= RxByte;`
386			`next_CRC5_8Bit <= 1'b1;`
387			`next_CRC5En <= 1'b1;`
388			`end`
389			`end`
390			`default:`
391			`begin`
392			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
393			`end`
394			`endcase`
395			`next_RxDataOutWEn <= 1'b1;`
396			NextState_prRxByte <= `TOKEN_FIN;
397			`end`
398			`TOKEN_FIN:
399			`begin`
400			`next_CRC5En <= 1'b0;`
401			`next_RxDataOutWEn <= 1'b0;`
402			NextState_prRxByte <= `WAIT_BYTE;
403			`next_processRxByteRdy <= 1'b1;`
404			`end`
405			`TOKEN_WAIT_CRC:
406			`if (CRC5UpdateRdy == 1'b1)`
407			NextState_prRxByte <= `TOKEN_CHK_STRM;
408			`CHK_SYNC_DO:
409			`begin`
410			if (RxByte == `SYNC_BYTE)
411			next_RXByteStMachCurrState <= `CHECK_PID_ST;
412			`else`
413			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
414			NextState_prRxByte <= `WAIT_BYTE;
415			`next_processRxByteRdy <= 1'b1;`
416			`end`
417			`IDLE_CHK_START:
418			`begin`
419			if (RxCtrl == `DATA_START)
420			next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
421			NextState_prRxByte <= `WAIT_BYTE;
422			`next_processRxByteRdy <= 1'b1;`
423			`end`
424			`endcase`
425			`end`
426
427			`//----------------------------------`
428			`// Current State Logic (sequential)`
429			`//----------------------------------`
430			`always @ (posedge clk)`
431			`begin : prRxByte_CurrentState`
432			`if (rst)`
433			CurrState_prRxByte <= `START_PRBY;
434			`else`
435			`CurrState_prRxByte <= NextState_prRxByte;`
436			`end`
437
438			`//----------------------------------`
439			`// Registered outputs logic`
440			`//----------------------------------`
441			`always @ (posedge clk)`
442			`begin : prRxByte_RegOutput`
443			`if (rst)`
444			`begin`
445			`RxByte <= 8'h00;`
446			`RxCtrl <= 8'h00;`
447			RXByteStMachCurrState <= `IDLE_BYTE_ST;
448			`CRCError <= 1'b0;`
449			`bitStuffError <= 1'b0;`
450			`RxOverflow <= 1'b0;`
451			`RxTimeOut <= 1'b0;`
452			`NAKRxed <= 1'b0;`
453			`stallRxed <= 1'b0;`
454			`ACKRxed <= 1'b0;`
455			`dataSequence <= 1'b0;`
456			`RXDataByteCnt <= 10'h00;`
457			`RxDataOut <= 8'h00;`
458			`RxCtrlOut <= 8'h00;`
459			`RxDataOutWEn <= 1'b0;`
460			`rstCRC <= 1'b0;`
461			`CRCData <= 8'h00;`
462			`CRC5En <= 1'b0;`
463			`CRC5_8Bit <= 1'b0;`
464			`CRC16En <= 1'b0;`
465			`processRxByteRdy <= 1'b1;`
466			`end`
467			`else`
468			`begin`
469			`RxByte <= next_RxByte;`
470			`RxCtrl <= next_RxCtrl;`
471			`RXByteStMachCurrState <= next_RXByteStMachCurrState;`
472			`CRCError <= next_CRCError;`
473			`bitStuffError <= next_bitStuffError;`
474			`RxOverflow <= next_RxOverflow;`
475			`RxTimeOut <= next_RxTimeOut;`
476			`NAKRxed <= next_NAKRxed;`
477			`stallRxed <= next_stallRxed;`
478			`ACKRxed <= next_ACKRxed;`
479			`dataSequence <= next_dataSequence;`
480			`RXDataByteCnt <= next_RXDataByteCnt;`
481			`RxDataOut <= next_RxDataOut;`
482			`RxCtrlOut <= next_RxCtrlOut;`
483			`RxDataOutWEn <= next_RxDataOutWEn;`
484			`rstCRC <= next_rstCRC;`
485			`CRCData <= next_CRCData;`
486			`CRC5En <= next_CRC5En;`
487			`CRC5_8Bit <= next_CRC5_8Bit;`
488			`CRC16En <= next_CRC16En;`
489			`processRxByteRdy <= next_processRxByteRdy;`
490			`end`
491			`end`
492
493			`endmodule`