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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [sendPacket_simlib.v] - Blame information for rev 408

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// File        : ../RTL/hostController/sendpacket.v
// Generated   : 11/10/06 05:37:20
// From        : ../RTL/hostController/sendpacket.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// sendPacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
 
 
module sendPacket_simlib (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, rst, sendPacketRdy, sendPacketWEn);
input   HCTxPortGnt;
input   HCTxPortRdy;
input   [3:0] PID;
input   [6:0] TxAddr;
input   [3:0] TxEndP;
input   clk;
input   [7:0] fifoData;
input   fifoEmpty;
input   fullSpeedPolarity;
input   rst;
input   sendPacketWEn;
output  [7:0] HCTxPortCntl;
output  [7:0] HCTxPortData;
output  HCTxPortReq;
output  HCTxPortWEn;
output  fifoReadEn;
output  [10:0] frameNum;
output  sendPacketRdy;
 
reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
reg     [7:0] HCTxPortData, next_HCTxPortData;
wire    HCTxPortGnt;
wire    HCTxPortRdy;
reg     HCTxPortReq, next_HCTxPortReq;
reg     HCTxPortWEn, next_HCTxPortWEn;
wire    [3:0] PID;
wire    [6:0] TxAddr;
wire    [3:0] TxEndP;
wire    clk;
wire    [7:0] fifoData;
wire    fifoEmpty;
reg     fifoReadEn, next_fifoReadEn;
reg     [10:0] frameNum, next_frameNum;
wire    fullSpeedPolarity;
wire    rst;
reg     sendPacketRdy, next_sendPacketRdy;
wire    sendPacketWEn;
 
// diagram signals declarations
reg  [7:0]PIDNotPID;
 
// BINARY ENCODED state machine: sndPkt
// State codes definitions:
`define START_SP 5'b00000
`define WAIT_ENABLE 5'b00001
`define SP_WAIT_GNT 5'b00010
`define SEND_PID_WAIT_RDY 5'b00011
`define SEND_PID_FIN 5'b00100
`define FIN_SP 5'b00101
`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
`define OUT_IN_SETUP_FIN 5'b01000
`define SEND_SOF_FIN1 5'b01001
`define SEND_SOF_WAIT_RDY3 5'b01010
`define SEND_SOF_WAIT_RDY4 5'b01011
`define DATA0_DATA1_READ_FIFO 5'b01100
`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
`define DATA0_DATA1_FIFO_EMPTY 5'b01110
`define DATA0_DATA1_FIN 5'b01111
`define DATA0_DATA1_TERM_BYTE 5'b10000
`define OUT_IN_SETUP_CLR_WEN1 5'b10001
`define SEND_SOF_CLR_WEN1 5'b10010
`define DATA0_DATA1_CLR_WEN 5'b10011
`define DATA0_DATA1_CLR_REN 5'b10100
`define LS_EOP_WAIT_RDY 5'b10101
`define LS_EOP_FIN 5'b10110
 
reg [4:0] CurrState_sndPkt;
reg [4:0] NextState_sndPkt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
 
always @(PID)
begin
    PIDNotPID <=  { (PID ^ 4'hf), PID };
end
 
//--------------------------------------------------------------------
// Machine: sndPkt
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or PID or fullSpeedPolarity or HCTxPortRdy or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt)
begin : sndPkt_NextState
  NextState_sndPkt <= CurrState_sndPkt;
  // Set default values for outputs and signals
  next_sendPacketRdy <= sendPacketRdy;
  next_HCTxPortReq <= HCTxPortReq;
  next_HCTxPortWEn <= HCTxPortWEn;
  next_HCTxPortData <= HCTxPortData;
  next_HCTxPortCntl <= HCTxPortCntl;
  next_frameNum <= frameNum;
  next_fifoReadEn <= fifoReadEn;
  case (CurrState_sndPkt)
    `START_SP:
      NextState_sndPkt <= `WAIT_ENABLE;
    `WAIT_ENABLE:
      if (sendPacketWEn == 1'b1)
      begin
        NextState_sndPkt <= `SP_WAIT_GNT;
        next_sendPacketRdy <= 1'b0;
        next_HCTxPortReq <= 1'b1;
      end
    `SP_WAIT_GNT:
      if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
        NextState_sndPkt <= `LS_EOP_WAIT_RDY;
      else if (HCTxPortGnt == 1'b1)
        NextState_sndPkt <= `SEND_PID_WAIT_RDY;
    `FIN_SP:
    begin
      NextState_sndPkt <= `WAIT_ENABLE;
      next_sendPacketRdy <= 1'b1;
      next_HCTxPortReq <= 1'b0;
    end
    `SEND_PID_WAIT_RDY:
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `SEND_PID_FIN;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= PIDNotPID;
        next_HCTxPortCntl <= `TX_PACKET_START;
      end
    `SEND_PID_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      if (PID == `DATA0 || PID == `DATA1)
        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
      else if (PID == `SOF)
        NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
      else if (PID == `OUT ||
        PID == `IN ||
        PID == `SETUP)
        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
      else
        NextState_sndPkt <= `FIN_SP;
    end
    `OUT_IN_SETUP_WAIT_RDY1:
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
        next_HCTxPortCntl <= `TX_PACKET_STREAM;
      end
    `OUT_IN_SETUP_WAIT_RDY2:
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `OUT_IN_SETUP_FIN;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
        next_HCTxPortCntl <= `TX_PACKET_STREAM;
      end
    `OUT_IN_SETUP_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `FIN_SP;
    end
    `OUT_IN_SETUP_CLR_WEN1:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
    end
    `SEND_SOF_FIN1:
    begin
      next_HCTxPortWEn <= 1'b0;
      next_frameNum <= frameNum + 1'b1;
      NextState_sndPkt <= `FIN_SP;
    end
    `SEND_SOF_WAIT_RDY3:
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= frameNum[7:0];
        next_HCTxPortCntl <= `TX_PACKET_STREAM;
      end
    `SEND_SOF_WAIT_RDY4:
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `SEND_SOF_FIN1;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= {5'b00000, frameNum[10:8]};
        next_HCTxPortCntl <= `TX_PACKET_STREAM;
      end
    `SEND_SOF_CLR_WEN1:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
    end
    `DATA0_DATA1_READ_FIFO:
    begin
      next_HCTxPortWEn <= 1'b1;
      next_HCTxPortData <= fifoData;
      next_HCTxPortCntl <= `TX_PACKET_STREAM;
      NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
    end
    `DATA0_DATA1_WAIT_READ_FIFO:
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
        next_fifoReadEn <= 1'b1;
      end
    `DATA0_DATA1_FIFO_EMPTY:
      if (fifoEmpty == 1'b0)
        NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
      else
        NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
    `DATA0_DATA1_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `FIN_SP;
    end
    `DATA0_DATA1_TERM_BYTE:
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `DATA0_DATA1_FIN;
        //Last byte is not valid data,
        //but the 'TX_PACKET_STOP' flag is required
        //by the SIE state machine to detect end of data packet
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= 8'h00;
        next_HCTxPortCntl <= `TX_PACKET_STOP;
      end
    `DATA0_DATA1_CLR_WEN:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
    end
    `DATA0_DATA1_CLR_REN:
    begin
      next_fifoReadEn <= 1'b0;
      NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
    end
    `LS_EOP_WAIT_RDY:
      if (HCTxPortRdy == 1'b1)
      begin
        NextState_sndPkt <= `LS_EOP_FIN;
        next_HCTxPortWEn <= 1'b1;
        next_HCTxPortData <= 8'h00;
        next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
      end
    `LS_EOP_FIN:
    begin
      next_HCTxPortWEn <= 1'b0;
      NextState_sndPkt <= `FIN_SP;
    end
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : sndPkt_CurrentState
  if (rst)
    CurrState_sndPkt <= `START_SP;
  else
    CurrState_sndPkt <= NextState_sndPkt;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : sndPkt_RegOutput
  if (rst)
  begin
    sendPacketRdy <= 1'b1;
    HCTxPortReq <= 1'b0;
    HCTxPortWEn <= 1'b0;
    HCTxPortData <= 8'h00;
    HCTxPortCntl <= 8'h00;
    frameNum <= 11'h000;
    fifoReadEn <= 1'b0;
  end
  else
  begin
    sendPacketRdy <= next_sendPacketRdy;
    HCTxPortReq <= next_HCTxPortReq;
    HCTxPortWEn <= next_HCTxPortWEn;
    HCTxPortData <= next_HCTxPortData;
    HCTxPortCntl <= next_HCTxPortCntl;
    frameNum <= next_frameNum;
    fifoReadEn <= next_fifoReadEn;
  end
end
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [sendPacket_simlib.v] - Blame information for rev 408

Line No.	Rev	Author	Line
1	408	julius
2			`// File : ../RTL/hostController/sendpacket.v`
3			`// Generated : 11/10/06 05:37:20`
4			`// From : ../RTL/hostController/sendpacket.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// sendPacket`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`include "timescale.v"
51			`include "usbSerialInterfaceEngine_h.v"
52			`include "usbConstants_h.v"
53
54
55
56			`module sendPacket_simlib (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, rst, sendPacketRdy, sendPacketWEn);`
57			`input HCTxPortGnt;`
58			`input HCTxPortRdy;`
59			`input [3:0] PID;`
60			`input [6:0] TxAddr;`
61			`input [3:0] TxEndP;`
62			`input clk;`
63			`input [7:0] fifoData;`
64			`input fifoEmpty;`
65			`input fullSpeedPolarity;`
66			`input rst;`
67			`input sendPacketWEn;`
68			`output [7:0] HCTxPortCntl;`
69			`output [7:0] HCTxPortData;`
70			`output HCTxPortReq;`
71			`output HCTxPortWEn;`
72			`output fifoReadEn;`
73			`output [10:0] frameNum;`
74			`output sendPacketRdy;`
75
76			`reg [7:0] HCTxPortCntl, next_HCTxPortCntl;`
77			`reg [7:0] HCTxPortData, next_HCTxPortData;`
78			`wire HCTxPortGnt;`
79			`wire HCTxPortRdy;`
80			`reg HCTxPortReq, next_HCTxPortReq;`
81			`reg HCTxPortWEn, next_HCTxPortWEn;`
82			`wire [3:0] PID;`
83			`wire [6:0] TxAddr;`
84			`wire [3:0] TxEndP;`
85			`wire clk;`
86			`wire [7:0] fifoData;`
87			`wire fifoEmpty;`
88			`reg fifoReadEn, next_fifoReadEn;`
89			`reg [10:0] frameNum, next_frameNum;`
90			`wire fullSpeedPolarity;`
91			`wire rst;`
92			`reg sendPacketRdy, next_sendPacketRdy;`
93			`wire sendPacketWEn;`
94
95			`// diagram signals declarations`
96			`reg [7:0]PIDNotPID;`
97
98			`// BINARY ENCODED state machine: sndPkt`
99			`// State codes definitions:`
100			`define START_SP 5'b00000
101			`define WAIT_ENABLE 5'b00001
102			`define SP_WAIT_GNT 5'b00010
103			`define SEND_PID_WAIT_RDY 5'b00011
104			`define SEND_PID_FIN 5'b00100
105			`define FIN_SP 5'b00101
106			`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
107			`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
108			`define OUT_IN_SETUP_FIN 5'b01000
109			`define SEND_SOF_FIN1 5'b01001
110			`define SEND_SOF_WAIT_RDY3 5'b01010
111			`define SEND_SOF_WAIT_RDY4 5'b01011
112			`define DATA0_DATA1_READ_FIFO 5'b01100
113			`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
114			`define DATA0_DATA1_FIFO_EMPTY 5'b01110
115			`define DATA0_DATA1_FIN 5'b01111
116			`define DATA0_DATA1_TERM_BYTE 5'b10000
117			`define OUT_IN_SETUP_CLR_WEN1 5'b10001
118			`define SEND_SOF_CLR_WEN1 5'b10010
119			`define DATA0_DATA1_CLR_WEN 5'b10011
120			`define DATA0_DATA1_CLR_REN 5'b10100
121			`define LS_EOP_WAIT_RDY 5'b10101
122			`define LS_EOP_FIN 5'b10110
123
124			`reg [4:0] CurrState_sndPkt;`
125			`reg [4:0] NextState_sndPkt;`
126
127			`// Diagram actions (continuous assignments allowed only: assign ...)`
128
129			`always @(PID)`
130			`begin`
131			`PIDNotPID <= { (PID ^ 4'hf), PID };`
132			`end`
133
134			`//--------------------------------------------------------------------`
135			`// Machine: sndPkt`
136			`//--------------------------------------------------------------------`
137			`//----------------------------------`
138			`// Next State Logic (combinatorial)`
139			`//----------------------------------`
140			`always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or PID or fullSpeedPolarity or HCTxPortRdy or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt)`
141			`begin : sndPkt_NextState`
142			`NextState_sndPkt <= CurrState_sndPkt;`
143			`// Set default values for outputs and signals`
144			`next_sendPacketRdy <= sendPacketRdy;`
145			`next_HCTxPortReq <= HCTxPortReq;`
146			`next_HCTxPortWEn <= HCTxPortWEn;`
147			`next_HCTxPortData <= HCTxPortData;`
148			`next_HCTxPortCntl <= HCTxPortCntl;`
149			`next_frameNum <= frameNum;`
150			`next_fifoReadEn <= fifoReadEn;`
151			`case (CurrState_sndPkt)`
152			`START_SP:
153			NextState_sndPkt <= `WAIT_ENABLE;
154			`WAIT_ENABLE:
155			`if (sendPacketWEn == 1'b1)`
156			`begin`
157			NextState_sndPkt <= `SP_WAIT_GNT;
158			`next_sendPacketRdy <= 1'b0;`
159			`next_HCTxPortReq <= 1'b1;`
160			`end`
161			`SP_WAIT_GNT:
162			if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
163			NextState_sndPkt <= `LS_EOP_WAIT_RDY;
164			`else if (HCTxPortGnt == 1'b1)`
165			NextState_sndPkt <= `SEND_PID_WAIT_RDY;
166			`FIN_SP:
167			`begin`
168			NextState_sndPkt <= `WAIT_ENABLE;
169			`next_sendPacketRdy <= 1'b1;`
170			`next_HCTxPortReq <= 1'b0;`
171			`end`
172			`SEND_PID_WAIT_RDY:
173			`if (HCTxPortRdy == 1'b1)`
174			`begin`
175			NextState_sndPkt <= `SEND_PID_FIN;
176			`next_HCTxPortWEn <= 1'b1;`
177			`next_HCTxPortData <= PIDNotPID;`
178			next_HCTxPortCntl <= `TX_PACKET_START;
179			`end`
180			`SEND_PID_FIN:
181			`begin`
182			`next_HCTxPortWEn <= 1'b0;`
183			if (PID == `DATA0 \|\| PID == `DATA1)
184			NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
185			else if (PID == `SOF)
186			NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
187			else if (PID == `OUT \|\|
188			PID == `IN \|\|
189			PID == `SETUP)
190			NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
191			`else`
192			NextState_sndPkt <= `FIN_SP;
193			`end`
194			`OUT_IN_SETUP_WAIT_RDY1:
195			`if (HCTxPortRdy == 1'b1)`
196			`begin`
197			NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
198			`next_HCTxPortWEn <= 1'b1;`
199			`next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};`
200			next_HCTxPortCntl <= `TX_PACKET_STREAM;
201			`end`
202			`OUT_IN_SETUP_WAIT_RDY2:
203			`if (HCTxPortRdy == 1'b1)`
204			`begin`
205			NextState_sndPkt <= `OUT_IN_SETUP_FIN;
206			`next_HCTxPortWEn <= 1'b1;`
207			`next_HCTxPortData <= {5'b00000, TxEndP[3:1]};`
208			next_HCTxPortCntl <= `TX_PACKET_STREAM;
209			`end`
210			`OUT_IN_SETUP_FIN:
211			`begin`
212			`next_HCTxPortWEn <= 1'b0;`
213			NextState_sndPkt <= `FIN_SP;
214			`end`
215			`OUT_IN_SETUP_CLR_WEN1:
216			`begin`
217			`next_HCTxPortWEn <= 1'b0;`
218			NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
219			`end`
220			`SEND_SOF_FIN1:
221			`begin`
222			`next_HCTxPortWEn <= 1'b0;`
223			`next_frameNum <= frameNum + 1'b1;`
224			NextState_sndPkt <= `FIN_SP;
225			`end`
226			`SEND_SOF_WAIT_RDY3:
227			`if (HCTxPortRdy == 1'b1)`
228			`begin`
229			NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
230			`next_HCTxPortWEn <= 1'b1;`
231			`next_HCTxPortData <= frameNum[7:0];`
232			next_HCTxPortCntl <= `TX_PACKET_STREAM;
233			`end`
234			`SEND_SOF_WAIT_RDY4:
235			`if (HCTxPortRdy == 1'b1)`
236			`begin`
237			NextState_sndPkt <= `SEND_SOF_FIN1;
238			`next_HCTxPortWEn <= 1'b1;`
239			`next_HCTxPortData <= {5'b00000, frameNum[10:8]};`
240			next_HCTxPortCntl <= `TX_PACKET_STREAM;
241			`end`
242			`SEND_SOF_CLR_WEN1:
243			`begin`
244			`next_HCTxPortWEn <= 1'b0;`
245			NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
246			`end`
247			`DATA0_DATA1_READ_FIFO:
248			`begin`
249			`next_HCTxPortWEn <= 1'b1;`
250			`next_HCTxPortData <= fifoData;`
251			next_HCTxPortCntl <= `TX_PACKET_STREAM;
252			NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
253			`end`
254			`DATA0_DATA1_WAIT_READ_FIFO:
255			`if (HCTxPortRdy == 1'b1)`
256			`begin`
257			NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
258			`next_fifoReadEn <= 1'b1;`
259			`end`
260			`DATA0_DATA1_FIFO_EMPTY:
261			`if (fifoEmpty == 1'b0)`
262			NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
263			`else`
264			NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
265			`DATA0_DATA1_FIN:
266			`begin`
267			`next_HCTxPortWEn <= 1'b0;`
268			NextState_sndPkt <= `FIN_SP;
269			`end`
270			`DATA0_DATA1_TERM_BYTE:
271			`if (HCTxPortRdy == 1'b1)`
272			`begin`
273			NextState_sndPkt <= `DATA0_DATA1_FIN;
274			`//Last byte is not valid data,`
275			`//but the 'TX_PACKET_STOP' flag is required`
276			`//by the SIE state machine to detect end of data packet`
277			`next_HCTxPortWEn <= 1'b1;`
278			`next_HCTxPortData <= 8'h00;`
279			next_HCTxPortCntl <= `TX_PACKET_STOP;
280			`end`
281			`DATA0_DATA1_CLR_WEN:
282			`begin`
283			`next_HCTxPortWEn <= 1'b0;`
284			NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
285			`end`
286			`DATA0_DATA1_CLR_REN:
287			`begin`
288			`next_fifoReadEn <= 1'b0;`
289			NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
290			`end`
291			`LS_EOP_WAIT_RDY:
292			`if (HCTxPortRdy == 1'b1)`
293			`begin`
294			NextState_sndPkt <= `LS_EOP_FIN;
295			`next_HCTxPortWEn <= 1'b1;`
296			`next_HCTxPortData <= 8'h00;`
297			next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
298			`end`
299			`LS_EOP_FIN:
300			`begin`
301			`next_HCTxPortWEn <= 1'b0;`
302			NextState_sndPkt <= `FIN_SP;
303			`end`
304			`endcase`
305			`end`
306
307			`//----------------------------------`
308			`// Current State Logic (sequential)`
309			`//----------------------------------`
310			`always @ (posedge clk)`
311			`begin : sndPkt_CurrentState`
312			`if (rst)`
313			CurrState_sndPkt <= `START_SP;
314			`else`
315			`CurrState_sndPkt <= NextState_sndPkt;`
316			`end`
317
318			`//----------------------------------`
319			`// Registered outputs logic`
320			`//----------------------------------`
321			`always @ (posedge clk)`
322			`begin : sndPkt_RegOutput`
323			`if (rst)`
324			`begin`
325			`sendPacketRdy <= 1'b1;`
326			`HCTxPortReq <= 1'b0;`
327			`HCTxPortWEn <= 1'b0;`
328			`HCTxPortData <= 8'h00;`
329			`HCTxPortCntl <= 8'h00;`
330			`frameNum <= 11'h000;`
331			`fifoReadEn <= 1'b0;`
332			`end`
333			`else`
334			`begin`
335			`sendPacketRdy <= next_sendPacketRdy;`
336			`HCTxPortReq <= next_HCTxPortReq;`
337			`HCTxPortWEn <= next_HCTxPortWEn;`
338			`HCTxPortData <= next_HCTxPortData;`
339			`HCTxPortCntl <= next_HCTxPortCntl;`
340			`frameNum <= next_frameNum;`
341			`fifoReadEn <= next_fifoReadEn;`
342			`end`
343			`end`
344
345			`endmodule`