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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [slaveGetPacket_simlib.v] - Blame information for rev 476

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// File        : ../RTL/slaveController/slaveGetpacket.v
// Generated   : 11/10/06 05:37:25
// From        : ../RTL/slaveController/slaveGetpacket.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveGetPacket
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
 
module slaveGetPacket_simlib (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst);
input   [7:0] RXDataIn;
input   RXDataValid;
input   RXFifoFull;
input   [7:0] RXStreamStatusIn;
input   SIERxTimeOut;           // Single cycle pulse
input   clk;
input   endPointReady;
input   getPacketEn;
input   rst;
output  ACKRxed;
output  CRCError;
output  [7:0] RXFifoData;
output  RXFifoWEn;
output  RXOverflow;
output  RXPacketRdy;
output  RXTimeOut;
output  [3:0] RxPID;
output  SIERxTimeOutEn;
output  bitStuffError;
output  dataSequence;
 
reg     ACKRxed, next_ACKRxed;
reg     CRCError, next_CRCError;
wire    [7:0] RXDataIn;
wire    RXDataValid;
reg     [7:0] RXFifoData, next_RXFifoData;
wire    RXFifoFull;
reg     RXFifoWEn, next_RXFifoWEn;
reg     RXOverflow, next_RXOverflow;
reg     RXPacketRdy, next_RXPacketRdy;
wire    [7:0] RXStreamStatusIn;
reg     RXTimeOut, next_RXTimeOut;
reg     [3:0] RxPID, next_RxPID;
wire    SIERxTimeOut;
reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
reg     bitStuffError, next_bitStuffError;
wire    clk;
reg     dataSequence, next_dataSequence;
wire    endPointReady;
wire    getPacketEn;
wire    rst;
 
// diagram signals declarations
reg  [7:0]RXByteOld, next_RXByteOld;
reg  [7:0]RXByteOldest, next_RXByteOldest;
reg  [7:0]RXByte, next_RXByte;
reg  [7:0]RXStreamStatus, next_RXStreamStatus;
 
// BINARY ENCODED state machine: slvGetPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
 
reg [4:0] CurrState_slvGetPkt;
reg [4:0] NextState_slvGetPkt;
 
 
//--------------------------------------------------------------------
// Machine: slvGetPkt
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
begin : slvGetPkt_NextState
  NextState_slvGetPkt <= CurrState_slvGetPkt;
  // Set default values for outputs and signals
  next_CRCError <= CRCError;
  next_bitStuffError <= bitStuffError;
  next_RXOverflow <= RXOverflow;
  next_RXTimeOut <= RXTimeOut;
  next_ACKRxed <= ACKRxed;
  next_dataSequence <= dataSequence;
  next_SIERxTimeOutEn <= SIERxTimeOutEn;
  next_RXByte <= RXByte;
  next_RXStreamStatus <= RXStreamStatus;
  next_RxPID <= RxPID;
  next_RXPacketRdy <= RXPacketRdy;
  next_RXByteOldest <= RXByteOldest;
  next_RXByteOld <= RXByteOld;
  next_RXFifoWEn <= RXFifoWEn;
  next_RXFifoData <= RXFifoData;
  case (CurrState_slvGetPkt)
    `START_GP:
      NextState_slvGetPkt <= `WAIT_EN;
    `WAIT_PKT:
    begin
      next_CRCError <= 1'b0;
      next_bitStuffError <= 1'b0;
      next_RXOverflow <= 1'b0;
      next_RXTimeOut <= 1'b0;
      next_ACKRxed <= 1'b0;
      next_dataSequence <= 1'b0;
      next_SIERxTimeOutEn <= 1'b1;
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `CHK_PKT_START;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
      else if (SIERxTimeOut == 1'b1)
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    end
    `CHK_PKT_START:
      if (RXStreamStatus == `RX_PACKET_START)
      begin
        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
        next_RxPID <= RXByte[3:0];
      end
      else
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXTimeOut <= 1'b1;
      end
    `WAIT_EN:
    begin
      next_RXPacketRdy <= 1'b0;
      next_SIERxTimeOutEn <= 1'b0;
      if (getPacketEn == 1'b1)
        NextState_slvGetPkt <= `WAIT_PKT;
    end
    `PKT_RDY:
    begin
      next_RXPacketRdy <= 1'b1;
      NextState_slvGetPkt <= `WAIT_EN;
    end
    `PROC_PKT_CHK_PID:
      if (RXByte[1:0] == `HANDSHAKE)
        NextState_slvGetPkt <= `PROC_PKT_HS;
      else if (RXByte[1:0] == `DATA)
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
      else
        NextState_slvGetPkt <= `PKT_RDY;
    `PROC_PKT_HS:
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PKT_RDY;
        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
      end
    `PROC_PKT_DATA_W_D1:
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    `PROC_PKT_DATA_CHK_D1:
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
        next_RXByteOldest <= RXByte;
      end
      else
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
    `PROC_PKT_DATA_W_D2:
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    `PROC_PKT_DATA_FIN:
    begin
      next_CRCError <= RXByte[`CRC_ERROR_BIT];
      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
      NextState_slvGetPkt <= `PKT_RDY;
    end
    `PROC_PKT_DATA_CHK_D2:
      if (RXStreamStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
        next_RXByteOld <= RXByte;
      end
      else
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
    `PROC_PKT_DATA_W_D3:
      if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
        next_RXByte <= RXDataIn;
        next_RXStreamStatus <= RXStreamStatusIn;
      end
    `PROC_PKT_DATA_CHK_D3:
      if (RXStreamStatus == `RX_PACKET_STREAM)
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
      else
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
    `PROC_PKT_DATA_LOOP_CHK_FIFO:
      if (endPointReady == 1'b0)
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
      else if (RXFifoFull == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
        next_RXOverflow <= 1'b1;
      end
      else
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
        next_RXFifoWEn <= 1'b1;
        next_RXFifoData <= RXByteOldest;
        next_RXByteOldest <= RXByteOld;
        next_RXByteOld <= RXByte;
      end
    `PROC_PKT_DATA_LOOP_FIFO_FULL:
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
    `PROC_PKT_DATA_LOOP_W_D:
    begin
      next_RXFifoWEn <= 1'b0;
      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
        next_RXByte <= RXDataIn;
      end
      else if (RXDataValid == 1'b1)
      begin
        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
        next_RXByte <= RXDataIn;
      end
    end
    `PROC_PKT_DATA_LOOP_DELAY:
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
    `PROC_PKT_DATA_LOOP_EP_N_RDY:    // Discard data
      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : slvGetPkt_CurrentState
  if (rst)
    CurrState_slvGetPkt <= `START_GP;
  else
    CurrState_slvGetPkt <= NextState_slvGetPkt;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : slvGetPkt_RegOutput
  if (rst)
  begin
    RXByteOld <= 8'h00;
    RXByteOldest <= 8'h00;
    RXByte <= 8'h00;
    RXStreamStatus <= 8'h00;
    RXPacketRdy <= 1'b0;
    RXFifoWEn <= 1'b0;
    RXFifoData <= 8'h00;
    CRCError <= 1'b0;
    bitStuffError <= 1'b0;
    RXOverflow <= 1'b0;
    RXTimeOut <= 1'b0;
    ACKRxed <= 1'b0;
    dataSequence <= 1'b0;
    SIERxTimeOutEn <= 1'b0;
    RxPID <= 4'h0;
  end
  else
  begin
    RXByteOld <= next_RXByteOld;
    RXByteOldest <= next_RXByteOldest;
    RXByte <= next_RXByte;
    RXStreamStatus <= next_RXStreamStatus;
    RXPacketRdy <= next_RXPacketRdy;
    RXFifoWEn <= next_RXFifoWEn;
    RXFifoData <= next_RXFifoData;
    CRCError <= next_CRCError;
    bitStuffError <= next_bitStuffError;
    RXOverflow <= next_RXOverflow;
    RXTimeOut <= next_RXTimeOut;
    ACKRxed <= next_ACKRxed;
    dataSequence <= next_dataSequence;
    SIERxTimeOutEn <= next_SIERxTimeOutEn;
    RxPID <= next_RxPID;
  end
end
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [slaveGetPacket_simlib.v] - Blame information for rev 476

Line No.	Rev	Author	Line
1	408	julius
2			`// File : ../RTL/slaveController/slaveGetpacket.v`
3			`// Generated : 11/10/06 05:37:25`
4			`// From : ../RTL/slaveController/slaveGetpacket.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// slaveGetPacket`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`include "timescale.v"
51			`include "usbSerialInterfaceEngine_h.v"
52			`include "usbConstants_h.v"
53
54			`module slaveGetPacket_simlib (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst);`
55			`input [7:0] RXDataIn;`
56			`input RXDataValid;`
57			`input RXFifoFull;`
58			`input [7:0] RXStreamStatusIn;`
59			`input SIERxTimeOut; // Single cycle pulse`
60			`input clk;`
61			`input endPointReady;`
62			`input getPacketEn;`
63			`input rst;`
64			`output ACKRxed;`
65			`output CRCError;`
66			`output [7:0] RXFifoData;`
67			`output RXFifoWEn;`
68			`output RXOverflow;`
69			`output RXPacketRdy;`
70			`output RXTimeOut;`
71			`output [3:0] RxPID;`
72			`output SIERxTimeOutEn;`
73			`output bitStuffError;`
74			`output dataSequence;`
75
76			`reg ACKRxed, next_ACKRxed;`
77			`reg CRCError, next_CRCError;`
78			`wire [7:0] RXDataIn;`
79			`wire RXDataValid;`
80			`reg [7:0] RXFifoData, next_RXFifoData;`
81			`wire RXFifoFull;`
82			`reg RXFifoWEn, next_RXFifoWEn;`
83			`reg RXOverflow, next_RXOverflow;`
84			`reg RXPacketRdy, next_RXPacketRdy;`
85			`wire [7:0] RXStreamStatusIn;`
86			`reg RXTimeOut, next_RXTimeOut;`
87			`reg [3:0] RxPID, next_RxPID;`
88			`wire SIERxTimeOut;`
89			`reg SIERxTimeOutEn, next_SIERxTimeOutEn;`
90			`reg bitStuffError, next_bitStuffError;`
91			`wire clk;`
92			`reg dataSequence, next_dataSequence;`
93			`wire endPointReady;`
94			`wire getPacketEn;`
95			`wire rst;`
96
97			`// diagram signals declarations`
98			`reg [7:0]RXByteOld, next_RXByteOld;`
99			`reg [7:0]RXByteOldest, next_RXByteOldest;`
100			`reg [7:0]RXByte, next_RXByte;`
101			`reg [7:0]RXStreamStatus, next_RXStreamStatus;`
102
103			`// BINARY ENCODED state machine: slvGetPkt`
104			`// State codes definitions:`
105			`define PROC_PKT_CHK_PID 5'b00000
106			`define PROC_PKT_HS 5'b00001
107			`define PROC_PKT_DATA_W_D1 5'b00010
108			`define PROC_PKT_DATA_CHK_D1 5'b00011
109			`define PROC_PKT_DATA_W_D2 5'b00100
110			`define PROC_PKT_DATA_FIN 5'b00101
111			`define PROC_PKT_DATA_CHK_D2 5'b00110
112			`define PROC_PKT_DATA_W_D3 5'b00111
113			`define PROC_PKT_DATA_CHK_D3 5'b01000
114			`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
115			`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
116			`define PROC_PKT_DATA_LOOP_W_D 5'b01011
117			`define START_GP 5'b01100
118			`define WAIT_PKT 5'b01101
119			`define CHK_PKT_START 5'b01110
120			`define WAIT_EN 5'b01111
121			`define PKT_RDY 5'b10000
122			`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
123			`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
124
125			`reg [4:0] CurrState_slvGetPkt;`
126			`reg [4:0] NextState_slvGetPkt;`
127
128
129			`//--------------------------------------------------------------------`
130			`// Machine: slvGetPkt`
131			`//--------------------------------------------------------------------`
132			`//----------------------------------`
133			`// Next State Logic (combinatorial)`
134			`//----------------------------------`
135			`always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)`
136			`begin : slvGetPkt_NextState`
137			`NextState_slvGetPkt <= CurrState_slvGetPkt;`
138			`// Set default values for outputs and signals`
139			`next_CRCError <= CRCError;`
140			`next_bitStuffError <= bitStuffError;`
141			`next_RXOverflow <= RXOverflow;`
142			`next_RXTimeOut <= RXTimeOut;`
143			`next_ACKRxed <= ACKRxed;`
144			`next_dataSequence <= dataSequence;`
145			`next_SIERxTimeOutEn <= SIERxTimeOutEn;`
146			`next_RXByte <= RXByte;`
147			`next_RXStreamStatus <= RXStreamStatus;`
148			`next_RxPID <= RxPID;`
149			`next_RXPacketRdy <= RXPacketRdy;`
150			`next_RXByteOldest <= RXByteOldest;`
151			`next_RXByteOld <= RXByteOld;`
152			`next_RXFifoWEn <= RXFifoWEn;`
153			`next_RXFifoData <= RXFifoData;`
154			`case (CurrState_slvGetPkt)`
155			`START_GP:
156			NextState_slvGetPkt <= `WAIT_EN;
157			`WAIT_PKT:
158			`begin`
159			`next_CRCError <= 1'b0;`
160			`next_bitStuffError <= 1'b0;`
161			`next_RXOverflow <= 1'b0;`
162			`next_RXTimeOut <= 1'b0;`
163			`next_ACKRxed <= 1'b0;`
164			`next_dataSequence <= 1'b0;`
165			`next_SIERxTimeOutEn <= 1'b1;`
166			`if (RXDataValid == 1'b1)`
167			`begin`
168			NextState_slvGetPkt <= `CHK_PKT_START;
169			`next_RXByte <= RXDataIn;`
170			`next_RXStreamStatus <= RXStreamStatusIn;`
171			`end`
172			`else if (SIERxTimeOut == 1'b1)`
173			`begin`
174			NextState_slvGetPkt <= `PKT_RDY;
175			`next_RXTimeOut <= 1'b1;`
176			`end`
177			`end`
178			`CHK_PKT_START:
179			if (RXStreamStatus == `RX_PACKET_START)
180			`begin`
181			NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
182			`next_RxPID <= RXByte[3:0];`
183			`end`
184			`else`
185			`begin`
186			NextState_slvGetPkt <= `PKT_RDY;
187			`next_RXTimeOut <= 1'b1;`
188			`end`
189			`WAIT_EN:
190			`begin`
191			`next_RXPacketRdy <= 1'b0;`
192			`next_SIERxTimeOutEn <= 1'b0;`
193			`if (getPacketEn == 1'b1)`
194			NextState_slvGetPkt <= `WAIT_PKT;
195			`end`
196			`PKT_RDY:
197			`begin`
198			`next_RXPacketRdy <= 1'b1;`
199			NextState_slvGetPkt <= `WAIT_EN;
200			`end`
201			`PROC_PKT_CHK_PID:
202			if (RXByte[1:0] == `HANDSHAKE)
203			NextState_slvGetPkt <= `PROC_PKT_HS;
204			else if (RXByte[1:0] == `DATA)
205			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
206			`else`
207			NextState_slvGetPkt <= `PKT_RDY;
208			`PROC_PKT_HS:
209			`if (RXDataValid == 1'b1)`
210			`begin`
211			NextState_slvGetPkt <= `PKT_RDY;
212			next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
213			next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
214			`end`
215			`PROC_PKT_DATA_W_D1:
216			`if (RXDataValid == 1'b1)`
217			`begin`
218			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
219			`next_RXByte <= RXDataIn;`
220			`next_RXStreamStatus <= RXStreamStatusIn;`
221			`end`
222			`PROC_PKT_DATA_CHK_D1:
223			if (RXStreamStatus == `RX_PACKET_STREAM)
224			`begin`
225			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
226			`next_RXByteOldest <= RXByte;`
227			`end`
228			`else`
229			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
230			`PROC_PKT_DATA_W_D2:
231			`if (RXDataValid == 1'b1)`
232			`begin`
233			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
234			`next_RXByte <= RXDataIn;`
235			`next_RXStreamStatus <= RXStreamStatusIn;`
236			`end`
237			`PROC_PKT_DATA_FIN:
238			`begin`
239			next_CRCError <= RXByte[`CRC_ERROR_BIT];
240			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
241			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
242			NextState_slvGetPkt <= `PKT_RDY;
243			`end`
244			`PROC_PKT_DATA_CHK_D2:
245			if (RXStreamStatus == `RX_PACKET_STREAM)
246			`begin`
247			NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
248			`next_RXByteOld <= RXByte;`
249			`end`
250			`else`
251			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
252			`PROC_PKT_DATA_W_D3:
253			`if (RXDataValid == 1'b1)`
254			`begin`
255			NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
256			`next_RXByte <= RXDataIn;`
257			`next_RXStreamStatus <= RXStreamStatusIn;`
258			`end`
259			`PROC_PKT_DATA_CHK_D3:
260			if (RXStreamStatus == `RX_PACKET_STREAM)
261			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
262			`else`
263			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
264			`PROC_PKT_DATA_LOOP_CHK_FIFO:
265			`if (endPointReady == 1'b0)`
266			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
267			`else if (RXFifoFull == 1'b1)`
268			`begin`
269			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
270			`next_RXOverflow <= 1'b1;`
271			`end`
272			`else`
273			`begin`
274			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
275			`next_RXFifoWEn <= 1'b1;`
276			`next_RXFifoData <= RXByteOldest;`
277			`next_RXByteOldest <= RXByteOld;`
278			`next_RXByteOld <= RXByte;`
279			`end`
280			`PROC_PKT_DATA_LOOP_FIFO_FULL:
281			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
282			`PROC_PKT_DATA_LOOP_W_D:
283			`begin`
284			`next_RXFifoWEn <= 1'b0;`
285			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
286			`begin`
287			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
288			`next_RXByte <= RXDataIn;`
289			`end`
290			`else if (RXDataValid == 1'b1)`
291			`begin`
292			NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
293			`next_RXByte <= RXDataIn;`
294			`end`
295			`end`
296			`PROC_PKT_DATA_LOOP_DELAY:
297			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
298			`PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
299			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
300			`endcase`
301			`end`
302
303			`//----------------------------------`
304			`// Current State Logic (sequential)`
305			`//----------------------------------`
306			`always @ (posedge clk)`
307			`begin : slvGetPkt_CurrentState`
308			`if (rst)`
309			CurrState_slvGetPkt <= `START_GP;
310			`else`
311			`CurrState_slvGetPkt <= NextState_slvGetPkt;`
312			`end`
313
314			`//----------------------------------`
315			`// Registered outputs logic`
316			`//----------------------------------`
317			`always @ (posedge clk)`
318			`begin : slvGetPkt_RegOutput`
319			`if (rst)`
320			`begin`
321			`RXByteOld <= 8'h00;`
322			`RXByteOldest <= 8'h00;`
323			`RXByte <= 8'h00;`
324			`RXStreamStatus <= 8'h00;`
325			`RXPacketRdy <= 1'b0;`
326			`RXFifoWEn <= 1'b0;`
327			`RXFifoData <= 8'h00;`
328			`CRCError <= 1'b0;`
329			`bitStuffError <= 1'b0;`
330			`RXOverflow <= 1'b0;`
331			`RXTimeOut <= 1'b0;`
332			`ACKRxed <= 1'b0;`
333			`dataSequence <= 1'b0;`
334			`SIERxTimeOutEn <= 1'b0;`
335			`RxPID <= 4'h0;`
336			`end`
337			`else`
338			`begin`
339			`RXByteOld <= next_RXByteOld;`
340			`RXByteOldest <= next_RXByteOldest;`
341			`RXByte <= next_RXByte;`
342			`RXStreamStatus <= next_RXStreamStatus;`
343			`RXPacketRdy <= next_RXPacketRdy;`
344			`RXFifoWEn <= next_RXFifoWEn;`
345			`RXFifoData <= next_RXFifoData;`
346			`CRCError <= next_CRCError;`
347			`bitStuffError <= next_bitStuffError;`
348			`RXOverflow <= next_RXOverflow;`
349			`RXTimeOut <= next_RXTimeOut;`
350			`ACKRxed <= next_ACKRxed;`
351			`dataSequence <= next_dataSequence;`
352			`SIERxTimeOutEn <= next_SIERxTimeOutEn;`
353			`RxPID <= next_RxPID;`
354			`end`
355			`end`
356
357			`endmodule`