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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [slaveSendPacket_simlib.v] - Blame information for rev 408

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// File        : ../RTL/slaveController/slaveSendpacket.v
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// Generated   : 11/10/06 05:37:26
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// From        : ../RTL/slaveController/slaveSendpacket.asf
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// By          : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// slaveSendPacket
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/                 ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbConstants_h.v"
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module slaveSendPacket_simlib (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn);
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input   [3:0] PID;
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input   SCTxPortGnt;
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input   SCTxPortRdy;
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input   clk;
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input   [7:0] fifoData;
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input   fifoEmpty;
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input   rst;
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input   sendPacketWEn;
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output  [7:0] SCTxPortCntl;
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output  [7:0] SCTxPortData;
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output  SCTxPortReq;
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output  SCTxPortWEn;
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output  fifoReadEn;
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output  sendPacketRdy;
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wire    [3:0] PID;
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reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
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reg     [7:0] SCTxPortData, next_SCTxPortData;
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wire    SCTxPortGnt;
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wire    SCTxPortRdy;
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reg     SCTxPortReq, next_SCTxPortReq;
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reg     SCTxPortWEn, next_SCTxPortWEn;
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wire    clk;
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wire    [7:0] fifoData;
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wire    fifoEmpty;
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reg     fifoReadEn, next_fifoReadEn;
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wire    rst;
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reg     sendPacketRdy, next_sendPacketRdy;
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wire    sendPacketWEn;
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// diagram signals declarations
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reg  [7:0]PIDNotPID;
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// BINARY ENCODED state machine: slvSndPkt
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// State codes definitions:
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`define START_SP1 4'b0000
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`define SP_WAIT_ENABLE 4'b0001
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`define SP1_WAIT_GNT 4'b0010
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`define SP_SEND_PID_WAIT_RDY 4'b0011
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`define SP_SEND_PID_FIN 4'b0100
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`define FIN_SP1 4'b0101
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`define SP_D0_D1_READ_FIFO 4'b0110
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`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
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`define SP_D0_D1_FIFO_EMPTY 4'b1000
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`define SP_D0_D1_FIN 4'b1001
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`define SP_D0_D1_TERM_BYTE 4'b1010
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`define SP_NOT_DATA 4'b1011
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`define SP_D0_D1_CLR_WEN 4'b1100
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`define SP_D0_D1_CLR_REN 4'b1101
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reg [3:0] CurrState_slvSndPkt;
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reg [3:0] NextState_slvSndPkt;
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// Diagram actions (continuous assignments allowed only: assign ...)
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always @(PID)
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begin
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    PIDNotPID <=  { (PID ^ 4'hf), PID };
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end
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//--------------------------------------------------------------------
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// Machine: slvSndPkt
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//--------------------------------------------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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//----------------------------------
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always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt)
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begin : slvSndPkt_NextState
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  NextState_slvSndPkt <= CurrState_slvSndPkt;
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  // Set default values for outputs and signals
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  next_sendPacketRdy <= sendPacketRdy;
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  next_SCTxPortReq <= SCTxPortReq;
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  next_SCTxPortWEn <= SCTxPortWEn;
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  next_SCTxPortData <= SCTxPortData;
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  next_SCTxPortCntl <= SCTxPortCntl;
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  next_fifoReadEn <= fifoReadEn;
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  case (CurrState_slvSndPkt)
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    `START_SP1:
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      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
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    `SP_WAIT_ENABLE:
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      if (sendPacketWEn == 1'b1)
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      begin
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        NextState_slvSndPkt <= `SP1_WAIT_GNT;
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        next_sendPacketRdy <= 1'b0;
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        next_SCTxPortReq <= 1'b1;
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      end
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    `SP1_WAIT_GNT:
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      if (SCTxPortGnt == 1'b1)
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        NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
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    `FIN_SP1:
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    begin
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      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
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      next_sendPacketRdy <= 1'b1;
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      next_SCTxPortReq <= 1'b0;
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    end
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    `SP_NOT_DATA:
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      NextState_slvSndPkt <= `FIN_SP1;
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    `SP_SEND_PID_WAIT_RDY:
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      if (SCTxPortRdy == 1'b1)
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      begin
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        NextState_slvSndPkt <= `SP_SEND_PID_FIN;
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        next_SCTxPortWEn <= 1'b1;
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        next_SCTxPortData <= PIDNotPID;
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        next_SCTxPortCntl <= `TX_PACKET_START;
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      end
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    `SP_SEND_PID_FIN:
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    begin
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      next_SCTxPortWEn <= 1'b0;
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      if (PID == `DATA0 || PID == `DATA1)
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        NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
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      else
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        NextState_slvSndPkt <= `SP_NOT_DATA;
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    end
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    `SP_D0_D1_READ_FIFO:
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    begin
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      next_SCTxPortWEn <= 1'b1;
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      next_SCTxPortData <= fifoData;
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      next_SCTxPortCntl <= `TX_PACKET_STREAM;
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      NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
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    end
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    `SP_D0_D1_WAIT_READ_FIFO:
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      if (SCTxPortRdy == 1'b1)
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      begin
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        NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
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        next_fifoReadEn <= 1'b1;
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      end
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    `SP_D0_D1_FIFO_EMPTY:
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      if (fifoEmpty == 1'b0)
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        NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
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      else
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        NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
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    `SP_D0_D1_FIN:
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    begin
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      next_SCTxPortWEn <= 1'b0;
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      NextState_slvSndPkt <= `FIN_SP1;
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    end
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    `SP_D0_D1_TERM_BYTE:
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      if (SCTxPortRdy == 1'b1)
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      begin
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        NextState_slvSndPkt <= `SP_D0_D1_FIN;
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        //Last byte is not valid data,
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        //but the 'TX_PACKET_STOP' flag is required
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        //by the SIE state machine to detect end of data packet
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        next_SCTxPortWEn <= 1'b1;
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        next_SCTxPortData <= 8'h00;
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        next_SCTxPortCntl <= `TX_PACKET_STOP;
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      end
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    `SP_D0_D1_CLR_WEN:
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    begin
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      next_SCTxPortWEn <= 1'b0;
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      NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
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    end
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    `SP_D0_D1_CLR_REN:
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    begin
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      next_fifoReadEn <= 1'b0;
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      NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
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    end
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  endcase
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end
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//----------------------------------
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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begin : slvSndPkt_CurrentState
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  if (rst)
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    CurrState_slvSndPkt <= `START_SP1;
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  else
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    CurrState_slvSndPkt <= NextState_slvSndPkt;
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end
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//----------------------------------
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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begin : slvSndPkt_RegOutput
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  if (rst)
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  begin
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    sendPacketRdy <= 1'b1;
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    SCTxPortReq <= 1'b0;
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    SCTxPortWEn <= 1'b0;
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    SCTxPortData <= 8'h00;
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    SCTxPortCntl <= 8'h00;
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    fifoReadEn <= 1'b0;
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  end
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  else
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  begin
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    sendPacketRdy <= next_sendPacketRdy;
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    SCTxPortReq <= next_SCTxPortReq;
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    SCTxPortWEn <= next_SCTxPortWEn;
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    SCTxPortData <= next_SCTxPortData;
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    SCTxPortCntl <= next_SCTxPortCntl;
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    fifoReadEn <= next_fifoReadEn;
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  end
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end
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endmodule

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