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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [slavecontroller_simlib.v] - Blame information for rev 449

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// File        : ../RTL/slaveController/slavecontroller.v
// Generated   : 11/10/06 05:37:25
// From        : ../RTL/slaveController/slavecontroller.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// slaveController
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbSlaveControl_h.v"
`include "usbConstants_h.v"
 
 
module slavecontroller_simlib (CRCError, NAKSent, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, SOFRxed, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBEndP, USBTgtAddress, bitStuffError, clk, clrEPRdy, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketREn, getPacketRdy, rst, sendPacketPID, sendPacketRdy, sendPacketWEn, stallSent, transDone);
input   CRCError;
input   [7:0] RxByte;
input   RxDataWEn;
input   RxOverflow;
input   [7:0] RxStatus;
input   RxTimeOut;
input   SCGlobalEn;
input   [4:0] USBEndPControlReg;
input   [6:0] USBTgtAddress;
input   bitStuffError;
input   clk;
input   getPacketRdy;
input   rst;
input   sendPacketRdy;
output  NAKSent;
output  SOFRxed;
output  [1:0] USBEndPNakTransTypeReg;
output  [1:0] USBEndPTransTypeReg;
output  [3:0] USBEndP;
output  clrEPRdy;
output  endPMuxErrorsWEn;
output  endPointReadyToGetPkt;
output  [10:0] frameNum;
output  getPacketREn;
output  [3:0] sendPacketPID;
output  sendPacketWEn;
output  stallSent;
output  transDone;
 
wire    CRCError;
reg     NAKSent, next_NAKSent;
wire    [7:0] RxByte;
wire    RxDataWEn;
wire    RxOverflow;
wire    [7:0] RxStatus;
wire    RxTimeOut;
wire    SCGlobalEn;
reg     SOFRxed, next_SOFRxed;
wire    [4:0] USBEndPControlReg;
reg     [1:0] USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
reg     [1:0] USBEndPTransTypeReg, next_USBEndPTransTypeReg;
reg     [3:0] USBEndP, next_USBEndP;
wire    [6:0] USBTgtAddress;
wire    bitStuffError;
wire    clk;
reg     clrEPRdy, next_clrEPRdy;
reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
reg     endPointReadyToGetPkt, next_endPointReadyToGetPkt;
reg     [10:0] frameNum, next_frameNum;
reg     getPacketREn, next_getPacketREn;
wire    getPacketRdy;
wire    rst;
reg     [3:0] sendPacketPID, next_sendPacketPID;
wire    sendPacketRdy;
reg     sendPacketWEn, next_sendPacketWEn;
reg     stallSent, next_stallSent;
reg     transDone, next_transDone;
 
// diagram signals declarations
reg  [7:0]PIDByte, next_PIDByte;
reg  [6:0]USBAddress, next_USBAddress;
reg  [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;
reg  [7:0]addrEndPTemp, next_addrEndPTemp;
reg  [7:0]endpCRCTemp, next_endpCRCTemp;
reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
 
// BINARY ENCODED state machine: slvCntrl
// State codes definitions:
`define WAIT_RX1 5'b00000
`define FIN_SC 5'b00001
`define GET_TOKEN_WAIT_CRC 5'b00010
`define GET_TOKEN_WAIT_ADDR 5'b00011
`define GET_TOKEN_WAIT_STOP 5'b00100
`define CHK_PID 5'b00101
`define GET_TOKEN_CHK_SOF 5'b00110
`define PID_ERROR 5'b00111
`define CHK_RDY 5'b01000
`define IN_NAK_STALL 5'b01001
`define IN_CHK_RDY 5'b01010
`define SETUP_OUT_CHK 5'b01011
`define SETUP_OUT_SEND 5'b01100
`define SETUP_OUT_GET_PKT 5'b01101
`define START_S1 5'b01110
`define GET_TOKEN_DELAY 5'b01111
`define GET_TOKEN_CHK_ADDR 5'b10000
`define IN_RESP_GET_RESP 5'b10001
`define IN_RESP_DATA 5'b10010
`define IN_RESP_CHK_ISO 5'b10011
 
reg [4:0] CurrState_slvCntrl;
reg [4:0] NextState_slvCntrl;
 
 
//--------------------------------------------------------------------
// Machine: slvCntrl
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RxByte or tempUSBEndPTransTypeReg or endpCRCTemp or addrEndPTemp or USBEndPControlReg or RxDataWEn or RxStatus or PIDByte or USBEndPControlRegCopy or NAKSent or sendPacketRdy or getPacketRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or getPacketREn or sendPacketWEn or sendPacketPID or USBEndPTransTypeReg or USBEndPNakTransTypeReg or frameNum or endPointReadyToGetPkt or CurrState_slvCntrl)
begin : slvCntrl_NextState
  NextState_slvCntrl <= CurrState_slvCntrl;
  // Set default values for outputs and signals
  next_stallSent <= stallSent;
  next_NAKSent <= NAKSent;
  next_SOFRxed <= SOFRxed;
  next_PIDByte <= PIDByte;
  next_transDone <= transDone;
  next_clrEPRdy <= clrEPRdy;
  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
  next_getPacketREn <= getPacketREn;
  next_sendPacketWEn <= sendPacketWEn;
  next_sendPacketPID <= sendPacketPID;
  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
  next_endpCRCTemp <= endpCRCTemp;
  next_addrEndPTemp <= addrEndPTemp;
  next_frameNum <= frameNum;
  next_USBAddress <= USBAddress;
  next_USBEndP <= USBEndP;
  next_USBEndPControlRegCopy <= USBEndPControlRegCopy;
  next_endPointReadyToGetPkt <= endPointReadyToGetPkt;
  case (CurrState_slvCntrl)
    `WAIT_RX1:
    begin
      next_stallSent <= 1'b0;
      next_NAKSent <= 1'b0;
      next_SOFRxed <= 1'b0;
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_START &&
        RxByte[1:0] == `TOKEN)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
        next_PIDByte <= RxByte;
      end
    end
    `FIN_SC:
    begin
      next_transDone <= 1'b0;
      next_clrEPRdy <= 1'b0;
      next_endPMuxErrorsWEn <= 1'b0;
      NextState_slvCntrl <= `WAIT_RX1;
    end
    `CHK_PID:
      if (PIDByte[3:0] == `SETUP)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if (PIDByte[3:0] == `OUT)
      begin
        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
        next_getPacketREn <= 1'b1;
      end
      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `IN_CHK_RDY;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
      end
      else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
      else if (PIDByte[3:0] == `IN)
      begin
        NextState_slvCntrl <= `CHK_RDY;
        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
      end
      else
        NextState_slvCntrl <= `PID_ERROR;
    `PID_ERROR:
      NextState_slvCntrl <= `WAIT_RX1;
    `CHK_RDY:
      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_transDone <= 1'b1;
        next_clrEPRdy <= 1'b1;
        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else if (NAKSent == 1'b1)
      begin
        NextState_slvCntrl <= `FIN_SC;
        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
        next_endPMuxErrorsWEn <= 1'b1;
      end
      else
        NextState_slvCntrl <= `FIN_SC;
    `SETUP_OUT_CHK:
      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `SETUP_OUT_SEND;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `ACK;
      end
    `SETUP_OUT_SEND:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
        NextState_slvCntrl <= `CHK_RDY;
    end
    `SETUP_OUT_GET_PKT:
    begin
      next_getPacketREn <= 1'b0;
      if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
        NextState_slvCntrl <= `CHK_RDY;
      else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
        bitStuffError == 1'b0 &&
        RxOverflow == 1'b0 &&
        RxTimeOut == 1'b0))
        NextState_slvCntrl <= `SETUP_OUT_CHK;
      else if (getPacketRdy == 1'b1)
        NextState_slvCntrl <= `CHK_RDY;
    end
    `IN_NAK_STALL:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
        NextState_slvCntrl <= `CHK_RDY;
    end
    `IN_CHK_RDY:
      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `NAK;
        next_NAKSent <= 1'b1;
      end
      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `IN_NAK_STALL;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `STALL;
        next_stallSent <= 1'b1;
      end
      else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA0;
      end
      else
      begin
        NextState_slvCntrl <= `IN_RESP_DATA;
        next_sendPacketWEn <= 1'b1;
        next_sendPacketPID <= `DATA1;
      end
    `IN_RESP_GET_RESP:
    begin
      next_getPacketREn <= 1'b0;
      if (getPacketRdy == 1'b1)
        NextState_slvCntrl <= `CHK_RDY;
    end
    `IN_RESP_DATA:
    begin
      next_sendPacketWEn <= 1'b0;
      if (sendPacketRdy == 1'b1)
        NextState_slvCntrl <= `IN_RESP_CHK_ISO;
    end
    `IN_RESP_CHK_ISO:
      if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
        NextState_slvCntrl <= `CHK_RDY;
      else
      begin
        NextState_slvCntrl <= `IN_RESP_GET_RESP;
        next_getPacketREn <= 1'b1;
      end
    `START_S1:
      NextState_slvCntrl <= `WAIT_RX1;
    `GET_TOKEN_WAIT_CRC:
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
        next_endpCRCTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
        NextState_slvCntrl <= `WAIT_RX1;
    `GET_TOKEN_WAIT_ADDR:
      if (RxDataWEn == 1'b1 &&
        RxStatus == `RX_PACKET_STREAM)
      begin
        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
        next_addrEndPTemp <= RxByte;
      end
      else if (RxDataWEn == 1'b1 &&
        RxStatus != `RX_PACKET_STREAM)
        NextState_slvCntrl <= `WAIT_RX1;
    `GET_TOKEN_WAIT_STOP:
      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
      else if (RxDataWEn == 1'b1)
        NextState_slvCntrl <= `WAIT_RX1;
    `GET_TOKEN_CHK_SOF:
      if (PIDByte[3:0] == `SOF)
      begin
        NextState_slvCntrl <= `WAIT_RX1;
        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
        next_SOFRxed <= 1'b1;
      end
      else
      begin
        NextState_slvCntrl <= `GET_TOKEN_DELAY;
        next_USBAddress <= addrEndPTemp[6:0];
        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
      end
    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndP etc to update
      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
    `GET_TOKEN_CHK_ADDR:
      if (USBEndP < `NUM_OF_ENDPOINTS  &&
        USBAddress == USBTgtAddress &&
        SCGlobalEn == 1'b1 &&
        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
      begin
        NextState_slvCntrl <= `CHK_PID;
        next_USBEndPControlRegCopy <= USBEndPControlReg;
        next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
      end
      else
        NextState_slvCntrl <= `WAIT_RX1;
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : slvCntrl_CurrentState
  if (rst)
    CurrState_slvCntrl <= `START_S1;
  else
    CurrState_slvCntrl <= NextState_slvCntrl;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : slvCntrl_RegOutput
  if (rst)
  begin
    tempUSBEndPTransTypeReg <= 2'b00;
    addrEndPTemp <= 8'h00;
    endpCRCTemp <= 8'h00;
    USBAddress <= 7'b0000000;
    PIDByte <= 8'h00;
    USBEndPControlRegCopy <= 5'b00000;
    transDone <= 1'b0;
    getPacketREn <= 1'b0;
    sendPacketPID <= 4'b0;
    sendPacketWEn <= 1'b0;
    clrEPRdy <= 1'b0;
    USBEndPTransTypeReg <= 2'b00;
    USBEndPNakTransTypeReg <= 2'b00;
    NAKSent <= 1'b0;
    stallSent <= 1'b0;
    SOFRxed <= 1'b0;
    endPMuxErrorsWEn <= 1'b0;
    frameNum <= 11'b00000000000;
    USBEndP <= 4'h0;
    endPointReadyToGetPkt <= 1'b0;
  end
  else
  begin
    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
    addrEndPTemp <= next_addrEndPTemp;
    endpCRCTemp <= next_endpCRCTemp;
    USBAddress <= next_USBAddress;
    PIDByte <= next_PIDByte;
    USBEndPControlRegCopy <= next_USBEndPControlRegCopy;
    transDone <= next_transDone;
    getPacketREn <= next_getPacketREn;
    sendPacketPID <= next_sendPacketPID;
    sendPacketWEn <= next_sendPacketWEn;
    clrEPRdy <= next_clrEPRdy;
    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
    NAKSent <= next_NAKSent;
    stallSent <= next_stallSent;
    SOFRxed <= next_SOFRxed;
    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
    frameNum <= next_frameNum;
    USBEndP <= next_USBEndP;
    endPointReadyToGetPkt <= next_endPointReadyToGetPkt;
  end
end
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [slavecontroller_simlib.v] - Blame information for rev 449

Line No.	Rev	Author	Line
1	408	julius
2			`// File : ../RTL/slaveController/slavecontroller.v`
3			`// Generated : 11/10/06 05:37:25`
4			`// From : ../RTL/slaveController/slavecontroller.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// slaveController`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`include "timescale.v"
51			`include "usbSerialInterfaceEngine_h.v"
52			`include "usbSlaveControl_h.v"
53			`include "usbConstants_h.v"
54
55
56			`module slavecontroller_simlib (CRCError, NAKSent, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, SOFRxed, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBEndP, USBTgtAddress, bitStuffError, clk, clrEPRdy, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketREn, getPacketRdy, rst, sendPacketPID, sendPacketRdy, sendPacketWEn, stallSent, transDone);`
57			`input CRCError;`
58			`input [7:0] RxByte;`
59			`input RxDataWEn;`
60			`input RxOverflow;`
61			`input [7:0] RxStatus;`
62			`input RxTimeOut;`
63			`input SCGlobalEn;`
64			`input [4:0] USBEndPControlReg;`
65			`input [6:0] USBTgtAddress;`
66			`input bitStuffError;`
67			`input clk;`
68			`input getPacketRdy;`
69			`input rst;`
70			`input sendPacketRdy;`
71			`output NAKSent;`
72			`output SOFRxed;`
73			`output [1:0] USBEndPNakTransTypeReg;`
74			`output [1:0] USBEndPTransTypeReg;`
75			`output [3:0] USBEndP;`
76			`output clrEPRdy;`
77			`output endPMuxErrorsWEn;`
78			`output endPointReadyToGetPkt;`
79			`output [10:0] frameNum;`
80			`output getPacketREn;`
81			`output [3:0] sendPacketPID;`
82			`output sendPacketWEn;`
83			`output stallSent;`
84			`output transDone;`
85
86			`wire CRCError;`
87			`reg NAKSent, next_NAKSent;`
88			`wire [7:0] RxByte;`
89			`wire RxDataWEn;`
90			`wire RxOverflow;`
91			`wire [7:0] RxStatus;`
92			`wire RxTimeOut;`
93			`wire SCGlobalEn;`
94			`reg SOFRxed, next_SOFRxed;`
95			`wire [4:0] USBEndPControlReg;`
96			`reg [1:0] USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;`
97			`reg [1:0] USBEndPTransTypeReg, next_USBEndPTransTypeReg;`
98			`reg [3:0] USBEndP, next_USBEndP;`
99			`wire [6:0] USBTgtAddress;`
100			`wire bitStuffError;`
101			`wire clk;`
102			`reg clrEPRdy, next_clrEPRdy;`
103			`reg endPMuxErrorsWEn, next_endPMuxErrorsWEn;`
104			`reg endPointReadyToGetPkt, next_endPointReadyToGetPkt;`
105			`reg [10:0] frameNum, next_frameNum;`
106			`reg getPacketREn, next_getPacketREn;`
107			`wire getPacketRdy;`
108			`wire rst;`
109			`reg [3:0] sendPacketPID, next_sendPacketPID;`
110			`wire sendPacketRdy;`
111			`reg sendPacketWEn, next_sendPacketWEn;`
112			`reg stallSent, next_stallSent;`
113			`reg transDone, next_transDone;`
114
115			`// diagram signals declarations`
116			`reg [7:0]PIDByte, next_PIDByte;`
117			`reg [6:0]USBAddress, next_USBAddress;`
118			`reg [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;`
119			`reg [7:0]addrEndPTemp, next_addrEndPTemp;`
120			`reg [7:0]endpCRCTemp, next_endpCRCTemp;`
121			`reg [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;`
122
123			`// BINARY ENCODED state machine: slvCntrl`
124			`// State codes definitions:`
125			`define WAIT_RX1 5'b00000
126			`define FIN_SC 5'b00001
127			`define GET_TOKEN_WAIT_CRC 5'b00010
128			`define GET_TOKEN_WAIT_ADDR 5'b00011
129			`define GET_TOKEN_WAIT_STOP 5'b00100
130			`define CHK_PID 5'b00101
131			`define GET_TOKEN_CHK_SOF 5'b00110
132			`define PID_ERROR 5'b00111
133			`define CHK_RDY 5'b01000
134			`define IN_NAK_STALL 5'b01001
135			`define IN_CHK_RDY 5'b01010
136			`define SETUP_OUT_CHK 5'b01011
137			`define SETUP_OUT_SEND 5'b01100
138			`define SETUP_OUT_GET_PKT 5'b01101
139			`define START_S1 5'b01110
140			`define GET_TOKEN_DELAY 5'b01111
141			`define GET_TOKEN_CHK_ADDR 5'b10000
142			`define IN_RESP_GET_RESP 5'b10001
143			`define IN_RESP_DATA 5'b10010
144			`define IN_RESP_CHK_ISO 5'b10011
145
146			`reg [4:0] CurrState_slvCntrl;`
147			`reg [4:0] NextState_slvCntrl;`
148
149
150			`//--------------------------------------------------------------------`
151			`// Machine: slvCntrl`
152			`//--------------------------------------------------------------------`
153			`//----------------------------------`
154			`// Next State Logic (combinatorial)`
155			`//----------------------------------`
156			always @ (RxByte or tempUSBEndPTransTypeReg or endpCRCTemp or addrEndPTemp or USBEndPControlReg or RxDataWEn or RxStatus or PIDByte or USBEndPControlRegCopy or NAKSent or sendPacketRdy or getPacketRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or getPacketREn or sendPacketWEn or sendPacketPID or USBEndPTransTypeReg or USBEndPNakTransTypeReg or frameNum or endPointReadyToGetPkt or CurrState_slvCntrl)
157			`begin : slvCntrl_NextState`
158			`NextState_slvCntrl <= CurrState_slvCntrl;`
159			`// Set default values for outputs and signals`
160			`next_stallSent <= stallSent;`
161			`next_NAKSent <= NAKSent;`
162			`next_SOFRxed <= SOFRxed;`
163			`next_PIDByte <= PIDByte;`
164			`next_transDone <= transDone;`
165			`next_clrEPRdy <= clrEPRdy;`
166			`next_endPMuxErrorsWEn <= endPMuxErrorsWEn;`
167			`next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
168			`next_getPacketREn <= getPacketREn;`
169			`next_sendPacketWEn <= sendPacketWEn;`
170			`next_sendPacketPID <= sendPacketPID;`
171			`next_USBEndPTransTypeReg <= USBEndPTransTypeReg;`
172			`next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;`
173			`next_endpCRCTemp <= endpCRCTemp;`
174			`next_addrEndPTemp <= addrEndPTemp;`
175			`next_frameNum <= frameNum;`
176			`next_USBAddress <= USBAddress;`
177			`next_USBEndP <= USBEndP;`
178			`next_USBEndPControlRegCopy <= USBEndPControlRegCopy;`
179			`next_endPointReadyToGetPkt <= endPointReadyToGetPkt;`
180			`case (CurrState_slvCntrl)`
181			`WAIT_RX1:
182			`begin`
183			`next_stallSent <= 1'b0;`
184			`next_NAKSent <= 1'b0;`
185			`next_SOFRxed <= 1'b0;`
186			`if (RxDataWEn == 1'b1 &&`
187			RxStatus == `RX_PACKET_START &&
188			RxByte[1:0] == `TOKEN)
189			`begin`
190			NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
191			`next_PIDByte <= RxByte;`
192			`end`
193			`end`
194			`FIN_SC:
195			`begin`
196			`next_transDone <= 1'b0;`
197			`next_clrEPRdy <= 1'b0;`
198			`next_endPMuxErrorsWEn <= 1'b0;`
199			NextState_slvCntrl <= `WAIT_RX1;
200			`end`
201			`CHK_PID:
202			if (PIDByte[3:0] == `SETUP)
203			`begin`
204			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
205			next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
206			`next_getPacketREn <= 1'b1;`
207			`end`
208			else if (PIDByte[3:0] == `OUT)
209			`begin`
210			NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
211			next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
212			`next_getPacketREn <= 1'b1;`
213			`end`
214			else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
215			`begin`
216			NextState_slvCntrl <= `IN_CHK_RDY;
217			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
218			`end`
219			else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
220			`begin`
221			NextState_slvCntrl <= `IN_RESP_DATA;
222			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
223			`next_sendPacketWEn <= 1'b1;`
224			next_sendPacketPID <= `DATA0;
225			`end`
226			else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))
227			`begin`
228			NextState_slvCntrl <= `IN_RESP_DATA;
229			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
230			`next_sendPacketWEn <= 1'b1;`
231			next_sendPacketPID <= `DATA1;
232			`end`
233			else if (PIDByte[3:0] == `IN)
234			`begin`
235			NextState_slvCntrl <= `CHK_RDY;
236			next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
237			`end`
238			`else`
239			NextState_slvCntrl <= `PID_ERROR;
240			`PID_ERROR:
241			NextState_slvCntrl <= `WAIT_RX1;
242			`CHK_RDY:
243			if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)
244			`begin`
245			NextState_slvCntrl <= `FIN_SC;
246			`next_transDone <= 1'b1;`
247			`next_clrEPRdy <= 1'b1;`
248			`next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;`
249			`next_endPMuxErrorsWEn <= 1'b1;`
250			`end`
251			`else if (NAKSent == 1'b1)`
252			`begin`
253			NextState_slvCntrl <= `FIN_SC;
254			`next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;`
255			`next_endPMuxErrorsWEn <= 1'b1;`
256			`end`
257			`else`
258			NextState_slvCntrl <= `FIN_SC;
259			`SETUP_OUT_CHK:
260			if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
261			`begin`
262			NextState_slvCntrl <= `SETUP_OUT_SEND;
263			`next_sendPacketWEn <= 1'b1;`
264			next_sendPacketPID <= `NAK;
265			`next_NAKSent <= 1'b1;`
266			`end`
267			else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
268			`begin`
269			NextState_slvCntrl <= `SETUP_OUT_SEND;
270			`next_sendPacketWEn <= 1'b1;`
271			next_sendPacketPID <= `STALL;
272			`next_stallSent <= 1'b1;`
273			`end`
274			`else`
275			`begin`
276			NextState_slvCntrl <= `SETUP_OUT_SEND;
277			`next_sendPacketWEn <= 1'b1;`
278			next_sendPacketPID <= `ACK;
279			`end`
280			`SETUP_OUT_SEND:
281			`begin`
282			`next_sendPacketWEn <= 1'b0;`
283			`if (sendPacketRdy == 1'b1)`
284			NextState_slvCntrl <= `CHK_RDY;
285			`end`
286			`SETUP_OUT_GET_PKT:
287			`begin`
288			`next_getPacketREn <= 1'b0;`
289			if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
290			NextState_slvCntrl <= `CHK_RDY;
291			`else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&`
292			`bitStuffError == 1'b0 &&`
293			`RxOverflow == 1'b0 &&`
294			`RxTimeOut == 1'b0))`
295			NextState_slvCntrl <= `SETUP_OUT_CHK;
296			`else if (getPacketRdy == 1'b1)`
297			NextState_slvCntrl <= `CHK_RDY;
298			`end`
299			`IN_NAK_STALL:
300			`begin`
301			`next_sendPacketWEn <= 1'b0;`
302			`if (sendPacketRdy == 1'b1)`
303			NextState_slvCntrl <= `CHK_RDY;
304			`end`
305			`IN_CHK_RDY:
306			if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
307			`begin`
308			NextState_slvCntrl <= `IN_NAK_STALL;
309			`next_sendPacketWEn <= 1'b1;`
310			next_sendPacketPID <= `NAK;
311			`next_NAKSent <= 1'b1;`
312			`end`
313			else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
314			`begin`
315			NextState_slvCntrl <= `IN_NAK_STALL;
316			`next_sendPacketWEn <= 1'b1;`
317			next_sendPacketPID <= `STALL;
318			`next_stallSent <= 1'b1;`
319			`end`
320			else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
321			`begin`
322			NextState_slvCntrl <= `IN_RESP_DATA;
323			`next_sendPacketWEn <= 1'b1;`
324			next_sendPacketPID <= `DATA0;
325			`end`
326			`else`
327			`begin`
328			NextState_slvCntrl <= `IN_RESP_DATA;
329			`next_sendPacketWEn <= 1'b1;`
330			next_sendPacketPID <= `DATA1;
331			`end`
332			`IN_RESP_GET_RESP:
333			`begin`
334			`next_getPacketREn <= 1'b0;`
335			`if (getPacketRdy == 1'b1)`
336			NextState_slvCntrl <= `CHK_RDY;
337			`end`
338			`IN_RESP_DATA:
339			`begin`
340			`next_sendPacketWEn <= 1'b0;`
341			`if (sendPacketRdy == 1'b1)`
342			NextState_slvCntrl <= `IN_RESP_CHK_ISO;
343			`end`
344			`IN_RESP_CHK_ISO:
345			if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
346			NextState_slvCntrl <= `CHK_RDY;
347			`else`
348			`begin`
349			NextState_slvCntrl <= `IN_RESP_GET_RESP;
350			`next_getPacketREn <= 1'b1;`
351			`end`
352			`START_S1:
353			NextState_slvCntrl <= `WAIT_RX1;
354			`GET_TOKEN_WAIT_CRC:
355			`if (RxDataWEn == 1'b1 &&`
356			RxStatus == `RX_PACKET_STREAM)
357			`begin`
358			NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
359			`next_endpCRCTemp <= RxByte;`
360			`end`
361			`else if (RxDataWEn == 1'b1 &&`
362			RxStatus != `RX_PACKET_STREAM)
363			NextState_slvCntrl <= `WAIT_RX1;
364			`GET_TOKEN_WAIT_ADDR:
365			`if (RxDataWEn == 1'b1 &&`
366			RxStatus == `RX_PACKET_STREAM)
367			`begin`
368			NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
369			`next_addrEndPTemp <= RxByte;`
370			`end`
371			`else if (RxDataWEn == 1'b1 &&`
372			RxStatus != `RX_PACKET_STREAM)
373			NextState_slvCntrl <= `WAIT_RX1;
374			`GET_TOKEN_WAIT_STOP:
375			if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
376			RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
377			RxByte [`RX_OVERFLOW_BIT] == 1'b0))
378			NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
379			`else if (RxDataWEn == 1'b1)`
380			NextState_slvCntrl <= `WAIT_RX1;
381			`GET_TOKEN_CHK_SOF:
382			if (PIDByte[3:0] == `SOF)
383			`begin`
384			NextState_slvCntrl <= `WAIT_RX1;
385			`next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};`
386			`next_SOFRxed <= 1'b1;`
387			`end`
388			`else`
389			`begin`
390			NextState_slvCntrl <= `GET_TOKEN_DELAY;
391			`next_USBAddress <= addrEndPTemp[6:0];`
392			`next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};`
393			`end`
394			`GET_TOKEN_DELAY: // Insert delay to allow USBEndP etc to update
395			NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
396			`GET_TOKEN_CHK_ADDR:
397			if (USBEndP < `NUM_OF_ENDPOINTS &&
398			`USBAddress == USBTgtAddress &&`
399			`SCGlobalEn == 1'b1 &&`
400			USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
401			`begin`
402			NextState_slvCntrl <= `CHK_PID;
403			`next_USBEndPControlRegCopy <= USBEndPControlReg;`
404			next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
405			`end`
406			`else`
407			NextState_slvCntrl <= `WAIT_RX1;
408			`endcase`
409			`end`
410
411			`//----------------------------------`
412			`// Current State Logic (sequential)`
413			`//----------------------------------`
414			`always @ (posedge clk)`
415			`begin : slvCntrl_CurrentState`
416			`if (rst)`
417			CurrState_slvCntrl <= `START_S1;
418			`else`
419			`CurrState_slvCntrl <= NextState_slvCntrl;`
420			`end`
421
422			`//----------------------------------`
423			`// Registered outputs logic`
424			`//----------------------------------`
425			`always @ (posedge clk)`
426			`begin : slvCntrl_RegOutput`
427			`if (rst)`
428			`begin`
429			`tempUSBEndPTransTypeReg <= 2'b00;`
430			`addrEndPTemp <= 8'h00;`
431			`endpCRCTemp <= 8'h00;`
432			`USBAddress <= 7'b0000000;`
433			`PIDByte <= 8'h00;`
434			`USBEndPControlRegCopy <= 5'b00000;`
435			`transDone <= 1'b0;`
436			`getPacketREn <= 1'b0;`
437			`sendPacketPID <= 4'b0;`
438			`sendPacketWEn <= 1'b0;`
439			`clrEPRdy <= 1'b0;`
440			`USBEndPTransTypeReg <= 2'b00;`
441			`USBEndPNakTransTypeReg <= 2'b00;`
442			`NAKSent <= 1'b0;`
443			`stallSent <= 1'b0;`
444			`SOFRxed <= 1'b0;`
445			`endPMuxErrorsWEn <= 1'b0;`
446			`frameNum <= 11'b00000000000;`
447			`USBEndP <= 4'h0;`
448			`endPointReadyToGetPkt <= 1'b0;`
449			`end`
450			`else`
451			`begin`
452			`tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;`
453			`addrEndPTemp <= next_addrEndPTemp;`
454			`endpCRCTemp <= next_endpCRCTemp;`
455			`USBAddress <= next_USBAddress;`
456			`PIDByte <= next_PIDByte;`
457			`USBEndPControlRegCopy <= next_USBEndPControlRegCopy;`
458			`transDone <= next_transDone;`
459			`getPacketREn <= next_getPacketREn;`
460			`sendPacketPID <= next_sendPacketPID;`
461			`sendPacketWEn <= next_sendPacketWEn;`
462			`clrEPRdy <= next_clrEPRdy;`
463			`USBEndPTransTypeReg <= next_USBEndPTransTypeReg;`
464			`USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;`
465			`NAKSent <= next_NAKSent;`
466			`stallSent <= next_stallSent;`
467			`SOFRxed <= next_SOFRxed;`
468			`endPMuxErrorsWEn <= next_endPMuxErrorsWEn;`
469			`frameNum <= next_frameNum;`
470			`USBEndP <= next_USBEndP;`
471			`endPointReadyToGetPkt <= next_endPointReadyToGetPkt;`
472			`end`
473			`end`
474
475			`endmodule`