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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [speedCtrlMux_simlib.v] - Blame information for rev 408

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1 408 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// speedCtrlMux.v                                               ////
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module speedCtrlMux_simlib (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
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input   directCtrlRate;
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input   directCtrlPol;
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input   sendPacketRate;
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input   sendPacketPol;
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input   sendPacketSel;
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output  fullSpeedRate;
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output  fullSpeedPol;
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wire   directCtrlRate;
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wire   directCtrlPol;
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wire   sendPacketRate;
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wire   sendPacketPol;
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wire   sendPacketSel;
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reg   fullSpeedRate;
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reg   fullSpeedPol;
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always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
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begin
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  if (sendPacketSel == 1'b1)
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  begin
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  fullSpeedRate <= sendPacketRate;
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  fullSpeedPol <= sendPacketPol;
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  end
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  else
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  begin
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  fullSpeedRate <= directCtrlRate;
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  fullSpeedPol <= directCtrlPol;
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  end
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end
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endmodule

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