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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [updateCRC16_simlib.v] - Blame information for rev 655

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// updateCRC16.v                                                ////
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module updateCRC16_simlib (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
input   rstCRC;
input   CRCEn;
input   [7:0] dataIn;
input   clk;
input   rst;
output  [15:0] CRCResult;
output ready;
 
wire   rstCRC;
wire   CRCEn;
wire   [7:0] dataIn;
wire   clk;
wire   rst;
reg    [15:0] CRCResult;
reg    ready;
 
reg doUpdateCRC;
reg [7:0] data;
reg [3:0] i;
 
always @(posedge clk)
begin
  if (rst == 1'b1 || rstCRC == 1'b1) begin
    doUpdateCRC <= 1'b0;
    i <= 4'h0;
    CRCResult <= 16'hffff;
    ready <= 1'b1;
  end
  else
  begin
    if (doUpdateCRC == 1'b0)
    begin
      if (CRCEn == 1'b1) begin
        doUpdateCRC <= 1'b1;
        data <= dataIn;
        ready <= 1'b0;
    end
    end
    else begin
      i <= i + 1'b1;
      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
        CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
      end
      else begin
        CRCResult <= {1'b0, CRCResult[15:1]};
      end
      data <= {1'b0, data[7:1]};
      if (i == 4'h7)
      begin
        doUpdateCRC <= 1'b0;
        i <= 4'h0;
        ready <= 1'b1;
      end
    end
  end
end
 
 
endmodule

Line No.	Rev	Author	Line
1	408	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// updateCRC16.v ////`
4			`//// ////`
5			`//// This file is part of the usbhostslave opencores effort.`
6			`//// <http://www.opencores.org/cores//> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`////`
10			`//// ////`
11			`//// To Do: ////`
12			`////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Steve Fielding, sfielding@base2designs.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from <http://www.opencores.org/lgpl.shtml> ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`include "timescale.v"
45
46			`module updateCRC16_simlib (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);`
47			`input rstCRC;`
48			`input CRCEn;`
49			`input [7:0] dataIn;`
50			`input clk;`
51			`input rst;`
52			`output [15:0] CRCResult;`
53			`output ready;`
54
55			`wire rstCRC;`
56			`wire CRCEn;`
57			`wire [7:0] dataIn;`
58			`wire clk;`
59			`wire rst;`
60			`reg [15:0] CRCResult;`
61			`reg ready;`
62
63			`reg doUpdateCRC;`
64			`reg [7:0] data;`
65			`reg [3:0] i;`
66
67			`always @(posedge clk)`
68			`begin`
69			`if (rst == 1'b1 \|\| rstCRC == 1'b1) begin`
70			`doUpdateCRC <= 1'b0;`
71			`i <= 4'h0;`
72			`CRCResult <= 16'hffff;`
73			`ready <= 1'b1;`
74			`end`
75			`else`
76			`begin`
77			`if (doUpdateCRC == 1'b0)`
78			`begin`
79			`if (CRCEn == 1'b1) begin`
80			`doUpdateCRC <= 1'b1;`
81			`data <= dataIn;`
82			`ready <= 1'b0;`
83			`end`
84			`end`
85			`else begin`
86			`i <= i + 1'b1;`
87			`if ( (CRCResult[0] ^ data[0]) == 1'b1) begin`
88			`CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;`
89			`end`
90			`else begin`
91			`CRCResult <= {1'b0, CRCResult[15:1]};`
92			`end`
93			`data <= {1'b0, data[7:1]};`
94			`if (i == 4'h7)`
95			`begin`
96			`doUpdateCRC <= 1'b0;`
97			`i <= 4'h0;`
98			`ready <= 1'b1;`
99			`end`
100			`end`
101			`end`
102			`end`
103
104
105			`endmodule`

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [updateCRC16_simlib.v] - Blame information for rev 655