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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [updateCRC5_simlib.v] - Blame information for rev 606

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// updateCRC5.v                                                 ////
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module updateCRC5_simlib (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
input   rstCRC;
input   CRCEn;
input   CRC5_8BitIn;
input   [7:0] dataIn;
input   clk;
input   rst;
output  [4:0] CRCResult;
output ready;
 
wire   rstCRC;
wire   CRCEn;
wire   CRC5_8BitIn;
wire   [7:0] dataIn;
wire   clk;
wire   rst;
reg    [4:0] CRCResult;
reg ready;
 
reg doUpdateCRC;
reg [7:0] data;
reg [3:0] loopEnd;
reg [3:0] i;
 
always @(posedge clk)
begin
  if (rst == 1'b1 || rstCRC == 1'b1) begin
    doUpdateCRC <= 1'b0;
    i <= 4'h0;
    CRCResult <= 5'h1f;
    ready <= 1'b1;
  end
  else
  begin
    if (doUpdateCRC == 1'b0) begin
      if (CRCEn == 1'b1) begin
        ready <= 1'b0;
        doUpdateCRC <= 1'b1;
        data <= dataIn;
        if (CRC5_8BitIn == 1'b1) begin
          loopEnd <= 4'h7;
        end
        else begin
          loopEnd <= 4'h2;
        end
      end
    end
    else begin
      i <= i + 1'b1;
      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
        CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
      end
      else begin
        CRCResult <= {1'b0, CRCResult[4:1]};
      end
      data <= {1'b0, data[7:1]};
      if (i == loopEnd) begin
        doUpdateCRC <= 1'b0;
        i <= 4'h0;
        ready <= 1'b1;
      end
    end
  end
end
 
 
endmodule

Line No.	Rev	Author	Line
1	408	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// updateCRC5.v ////`
4			`//// ////`
5			`//// This file is part of the usbhostslave opencores effort.`
6			`//// <http://www.opencores.org/cores//> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`////`
10			`//// ////`
11			`//// To Do: ////`
12			`////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Steve Fielding, sfielding@base2designs.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from <http://www.opencores.org/lgpl.shtml> ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`include "timescale.v"
45
46			`module updateCRC5_simlib (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);`
47			`input rstCRC;`
48			`input CRCEn;`
49			`input CRC5_8BitIn;`
50			`input [7:0] dataIn;`
51			`input clk;`
52			`input rst;`
53			`output [4:0] CRCResult;`
54			`output ready;`
55
56			`wire rstCRC;`
57			`wire CRCEn;`
58			`wire CRC5_8BitIn;`
59			`wire [7:0] dataIn;`
60			`wire clk;`
61			`wire rst;`
62			`reg [4:0] CRCResult;`
63			`reg ready;`
64
65			`reg doUpdateCRC;`
66			`reg [7:0] data;`
67			`reg [3:0] loopEnd;`
68			`reg [3:0] i;`
69
70			`always @(posedge clk)`
71			`begin`
72			`if (rst == 1'b1 \|\| rstCRC == 1'b1) begin`
73			`doUpdateCRC <= 1'b0;`
74			`i <= 4'h0;`
75			`CRCResult <= 5'h1f;`
76			`ready <= 1'b1;`
77			`end`
78			`else`
79			`begin`
80			`if (doUpdateCRC == 1'b0) begin`
81			`if (CRCEn == 1'b1) begin`
82			`ready <= 1'b0;`
83			`doUpdateCRC <= 1'b1;`
84			`data <= dataIn;`
85			`if (CRC5_8BitIn == 1'b1) begin`
86			`loopEnd <= 4'h7;`
87			`end`
88			`else begin`
89			`loopEnd <= 4'h2;`
90			`end`
91			`end`
92			`end`
93			`else begin`
94			`i <= i + 1'b1;`
95			`if ( (CRCResult[0] ^ data[0]) == 1'b1) begin`
96			`CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;`
97			`end`
98			`else begin`
99			`CRCResult <= {1'b0, CRCResult[4:1]};`
100			`end`
101			`data <= {1'b0, data[7:1]};`
102			`if (i == loopEnd) begin`
103			`doUpdateCRC <= 1'b0;`
104			`i <= 4'h0;`
105			`ready <= 1'b1;`
106			`end`
107			`end`
108			`end`
109			`end`
110
111
112			`endmodule`

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [updateCRC5_simlib.v] - Blame information for rev 606