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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [usbHostControl_h.v] - Blame information for rev 577

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//////////////////////////////////////////////////////////////////////
// usbHostControl_h.v                                          
//////////////////////////////////////////////////////////////////////
 
`ifdef usbHostControl_h_vdefined
`else
`define usbHostControl_h_vdefined
 
//HCRegIndices
`define TX_CONTROL_REG 4'h0
`define TX_TRANS_TYPE_REG 4'h1
`define TX_LINE_CONTROL_REG 4'h2
`define TX_SOF_ENABLE_REG 4'h3
`define TX_ADDR_REG 4'h4
`define TX_ENDP_REG 4'h5
`define FRAME_NUM_MSB_REG 4'h6
`define FRAME_NUM_LSB_REG 4'h7
`define INTERRUPT_STATUS_REG 4'h8
`define INTERRUPT_MASK_REG 4'h9
`define RX_STATUS_REG 4'ha
`define RX_PID_REG 4'hb
`define RX_ADDR_REG 4'hc
`define RX_ENDP_REG 4'hd
`define RX_CONNECT_STATE_REG 4'he
`define HOST_SOF_TIMER_MSB_REG 4'hf
 
`define HCREG_BUFFER_LEN 4'hf
`define HCREG_MASK 4'hf
 
//TXControlRegIndices
`define TRANS_REQ_BIT 0
`define SOF_SYNC_BIT 1
`define PREAMBLE_ENABLE_BIT 2
`define ISO_ENABLE_BIT 3
 
//interruptRegIndices
`define TRANS_DONE_BIT 0
`define RESUME_INT_BIT 1
`define CONNECTION_EVENT_BIT 2
`define SOF_SENT_BIT 3
 
//TXTransactionTypes
`define SETUP_TRANS 0
`define IN_TRANS 1
`define OUTDATA0_TRANS 2
`define OUTDATA1_TRANS 3
 
 //TXLineControlIndices
`define TX_LINE_STATE_LSBIT 0
`define TX_LINE_STATE_MSBIT 1
`define DIRECT_CONTROL_BIT 2
`define FULL_SPEED_LINE_POLARITY_BIT 3
`define FULL_SPEED_LINE_RATE_BIT 4
 
//TXSOFEnableIndices
`define SOF_EN_BIT 0
 
//SOFTimeConstants 
//`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval   
//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer 
`define SOF_TX_TIME 16'hbb7d     //Correct SOF interval for 48MHz clock.
//`define SOF_TX_MARGIN 2 
`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
 
//Host RXStatusRegIndices 
`define HC_CRC_ERROR_BIT 0
`define HC_BIT_STUFF_ERROR_BIT 1
`define HC_RX_OVERFLOW_BIT 2
`define HC_RX_TIME_OUT_BIT 3
`define HC_NAK_RXED_BIT 4
`define HC_STALL_RXED_BIT 5
`define HC_ACK_RXED_BIT 6
`define HC_DATA_SEQUENCE_BIT 7
 
`endif //usbHostControl_h_vdefined 

Line No.	Rev	Author	Line
1	408	julius	`//////////////////////////////////////////////////////////////////////`
2			`// usbHostControl_h.v`
3			`//////////////////////////////////////////////////////////////////////`
4
5			`ifdef usbHostControl_h_vdefined
6			`else
7			`define usbHostControl_h_vdefined
8
9			`//HCRegIndices`
10			`define TX_CONTROL_REG 4'h0
11			`define TX_TRANS_TYPE_REG 4'h1
12			`define TX_LINE_CONTROL_REG 4'h2
13			`define TX_SOF_ENABLE_REG 4'h3
14			`define TX_ADDR_REG 4'h4
15			`define TX_ENDP_REG 4'h5
16			`define FRAME_NUM_MSB_REG 4'h6
17			`define FRAME_NUM_LSB_REG 4'h7
18			`define INTERRUPT_STATUS_REG 4'h8
19			`define INTERRUPT_MASK_REG 4'h9
20			`define RX_STATUS_REG 4'ha
21			`define RX_PID_REG 4'hb
22			`define RX_ADDR_REG 4'hc
23			`define RX_ENDP_REG 4'hd
24			`define RX_CONNECT_STATE_REG 4'he
25			`define HOST_SOF_TIMER_MSB_REG 4'hf
26
27			`define HCREG_BUFFER_LEN 4'hf
28			`define HCREG_MASK 4'hf
29
30			`//TXControlRegIndices`
31			`define TRANS_REQ_BIT 0
32			`define SOF_SYNC_BIT 1
33			`define PREAMBLE_ENABLE_BIT 2
34			`define ISO_ENABLE_BIT 3
35
36			`//interruptRegIndices`
37			`define TRANS_DONE_BIT 0
38			`define RESUME_INT_BIT 1
39			`define CONNECTION_EVENT_BIT 2
40			`define SOF_SENT_BIT 3
41
42			`//TXTransactionTypes`
43			`define SETUP_TRANS 0
44			`define IN_TRANS 1
45			`define OUTDATA0_TRANS 2
46			`define OUTDATA1_TRANS 3
47
48			`//TXLineControlIndices`
49			`define TX_LINE_STATE_LSBIT 0
50			`define TX_LINE_STATE_MSBIT 1
51			`define DIRECT_CONTROL_BIT 2
52			`define FULL_SPEED_LINE_POLARITY_BIT 3
53			`define FULL_SPEED_LINE_RATE_BIT 4
54
55			`//TXSOFEnableIndices`
56			`define SOF_EN_BIT 0
57
58			`//SOFTimeConstants`
59			//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
60			`//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer`
61			`define SOF_TX_TIME 16'hbb7d //Correct SOF interval for 48MHz clock.
62			//`define SOF_TX_MARGIN 2
63			`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
64
65			`//Host RXStatusRegIndices`
66			`define HC_CRC_ERROR_BIT 0
67			`define HC_BIT_STUFF_ERROR_BIT 1
68			`define HC_RX_OVERFLOW_BIT 2
69			`define HC_RX_TIME_OUT_BIT 3
70			`define HC_NAK_RXED_BIT 4
71			`define HC_STALL_RXED_BIT 5
72			`define HC_ACK_RXED_BIT 6
73			`define HC_DATA_SEQUENCE_BIT 7
74
75			`endif //usbHostControl_h_vdefined

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [usbHostControl_h.v] - Blame information for rev 577