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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [usbSerialInterfaceEngine_h.v] - Blame information for rev 651

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1 408 julius
//////////////////////////////////////////////////////////////////////
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// usbSerialInterfaceEngine_h.v                                
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//////////////////////////////////////////////////////////////////////
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`ifdef usbSerialInterfaceEngine_h_vdefined
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`else
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`define usbSerialInterfaceEngine_h_vdefined
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 // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
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`define FS_OVER_SAMPLE_RATE 4
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`define LS_OVER_SAMPLE_RATE 32
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//timeOuts
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`define RX_PACKET_TOUT 18
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`define RX_EDGE_DET_TOUT 7
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//TXStreamControlTypes
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`define TX_DIRECT_CONTROL 8'h00
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`define TX_RESUME_START 8'h01
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`define TX_PACKET_START 8'h02
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`define TX_PACKET_STREAM 8'h03
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`define TX_PACKET_STOP 8'h04
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`define TX_IDLE 8'h05
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`define TX_LS_KEEP_ALIVE 8'h06
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//RXStreamControlTypes
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`define RX_PACKET_START 0
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`define RX_PACKET_STREAM 1
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`define RX_PACKET_STOP 2
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//USBLineStates
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// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
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`define ONE_ZERO 2'b10
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`define ZERO_ONE 2'b01
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`define SE0 2'b00
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`define SE1 2'b11
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//RXStatusIndices
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`define CRC_ERROR_BIT 0
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`define BIT_STUFF_ERROR_BIT 1
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`define RX_OVERFLOW_BIT 2
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`define NAK_RXED_BIT 3
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`define STALL_RXED_BIT 4
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`define ACK_RXED_BIT 5
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`define DATA_SEQUENCE_BIT 6
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//usbWireControlStates
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`define TRI_STATE 1'b0
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`define DRIVE 1'b1
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//limits
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`define MAX_CONSEC_SAME_BITS 4'h6
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`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
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// RESUME_RX_WAIT_TIME defines the time period for resume detection
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// The resume counter is incremented at the bit rate, so
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// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
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// and 30 * 1/1.5MHz =  20uS at low speed, both of which are within the USB spec of 
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// 2.5uS <= resumeDetectTime <= 100uS
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`define RESUME_RX_WAIT_TIME 5'd29
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//`define RESUME_WAIT_TIME_MINUS1 9
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// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate 
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`ifdef SIM_COMPILE
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`define HOST_TX_RESUME_TIME 16'd10
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`else
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`define HOST_TX_RESUME_TIME 16'd30000  //Host sends resume for 30000 * 1/1.5MHz = 20mS
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`endif
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//`define CONNECT_WAIT_TIME 8'd20
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`define CONNECT_WAIT_TIME 8'd120      //Device connect detected after 120 * 1/48MHz = 2.5uS
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//`define DISCONNECT_WAIT_TIME 8'd20   
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`define DISCONNECT_WAIT_TIME 8'd120   //Device disconnect detected after 120 * 1/48MHz = 2.5uS
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//RXConnectStates
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`define DISCONNECT 2'b00
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`define LOW_SPEED_CONNECT 2'b01
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`define FULL_SPEED_CONNECT 2'b10
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//TX_RX_InternalStreamTypes
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`define DATA_START 8'h00
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`define DATA_STOP 8'h01
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`define DATA_STREAM 8'h02
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`define DATA_BIT_STUFF_ERROR 8'h03
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//RXStMach states
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`define DISCONNECT_ST 4'h0
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`define WAIT_FULL_SPEED_CONN_ST 4'h1
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`define WAIT_LOW_SPEED_CONN_ST 4'h2
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`define CONNECT_LOW_SPEED_ST 4'h3
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`define CONNECT_FULL_SPEED_ST 4'h4
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`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
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`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
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//RXBitStateMachStates
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`define IDLE_BIT_ST 2'b00
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`define DATA_RECEIVE_BIT_ST 2'b01
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`define WAIT_RESUME_ST 2'b10
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`define RESUME_END_WAIT_ST 2'b11
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//RXByteStateMachStates 
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`define IDLE_BYTE_ST 3'b000
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`define CHECK_SYNC_ST 3'b001
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`define CHECK_PID_ST 3'b010
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`define HS_BYTE_ST 3'b011
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`define TOKEN_BYTE_ST 3'b100
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`define DATA_BYTE_ST 3'b101
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`endif //usbSerialInterfaceEngine_h_vdefined
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