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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [usbSlaveControl_simlib.v] - Blame information for rev 655

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1 408 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// usbSlaveControl.v                                            ////
4
////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
6
//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44
`include "timescale.v"
45
 
46
module usbSlaveControl_simlib(
47
  busClk,
48
  rstSyncToBusClk,
49
  usbClk,
50
  rstSyncToUsbClk,
51
  //getPacket
52
  RxByteStatus, RxData, RxDataValid,
53
  SIERxTimeOut, RxFifoData, SIERxTimeOutEn,
54
  //speedCtrlMux
55
  fullSpeedRate, fullSpeedPol,
56
  connectSlaveToHost,
57
  //SCTxPortArbiter
58
  SCTxPortEn, SCTxPortRdy,
59
  SCTxPortData, SCTxPortCtrl,
60
  //rxStatusMonitor
61
  vBusDetect,
62
  connectStateIn,
63
  resumeDetectedIn,
64
  //USBHostControlBI 
65
  busAddress,
66
  busDataIn,
67
  busDataOut,
68
  busWriteEn,
69
  busStrobe_i,
70
  SOFRxedIntOut,
71
  resetEventIntOut,
72
  resumeIntOut,
73
  transDoneIntOut,
74
  vBusDetIntOut,
75
  NAKSentIntOut,
76
  slaveControlSelect,
77
  //fifoMux
78
  TxFifoEP0REn,
79
  TxFifoEP1REn,
80
  TxFifoEP2REn,
81
  TxFifoEP3REn,
82
  TxFifoEP0Data,
83
  TxFifoEP1Data,
84
  TxFifoEP2Data,
85
  TxFifoEP3Data,
86
  TxFifoEP0Empty,
87
  TxFifoEP1Empty,
88
  TxFifoEP2Empty,
89
  TxFifoEP3Empty,
90
  RxFifoEP0WEn,
91
  RxFifoEP1WEn,
92
  RxFifoEP2WEn,
93
  RxFifoEP3WEn,
94
  RxFifoEP0Full,
95
  RxFifoEP1Full,
96
  RxFifoEP2Full,
97
  RxFifoEP3Full
98
    );
99
 
100
input busClk;
101
input rstSyncToBusClk;
102
input usbClk;
103
input rstSyncToUsbClk;
104
//getPacket
105
input [7:0] RxByteStatus;
106
input [7:0] RxData;
107
input RxDataValid;
108
input SIERxTimeOut;
109
output SIERxTimeOutEn;
110
output [7:0] RxFifoData;
111
//speedCtrlMux
112
output fullSpeedRate;
113
output fullSpeedPol;
114
output connectSlaveToHost;
115
//HCTxPortArbiter
116
output SCTxPortEn;
117
input SCTxPortRdy;
118
output [7:0] SCTxPortData;
119
output [7:0] SCTxPortCtrl;
120
//rxStatusMonitor
121
input vBusDetect;
122
input [1:0] connectStateIn;
123
input resumeDetectedIn;
124
//USBHostControlBI 
125
input [4:0] busAddress;
126
input [7:0] busDataIn;
127
output [7:0] busDataOut;
128
input busWriteEn;
129
input busStrobe_i;
130
output SOFRxedIntOut;
131
output resetEventIntOut;
132
output resumeIntOut;
133
output transDoneIntOut;
134
output vBusDetIntOut;
135
output NAKSentIntOut;
136
input slaveControlSelect;
137
//fifoMux
138
output TxFifoEP0REn;
139
output TxFifoEP1REn;
140
output TxFifoEP2REn;
141
output TxFifoEP3REn;
142
input [7:0] TxFifoEP0Data;
143
input [7:0] TxFifoEP1Data;
144
input [7:0] TxFifoEP2Data;
145
input [7:0] TxFifoEP3Data;
146
input TxFifoEP0Empty;
147
input TxFifoEP1Empty;
148
input TxFifoEP2Empty;
149
input TxFifoEP3Empty;
150
output RxFifoEP0WEn;
151
output RxFifoEP1WEn;
152
output RxFifoEP2WEn;
153
output RxFifoEP3WEn;
154
input RxFifoEP0Full;
155
input RxFifoEP1Full;
156
input RxFifoEP2Full;
157
input RxFifoEP3Full;
158
 
159
wire busClk;
160
wire rstSyncToBusClk;
161
wire usbClk;
162
wire rstSyncToUsbClk;
163
wire [7:0] RxByteStatus;
164
wire [7:0] RxData;
165
wire RxDataValid;
166
wire SIERxTimeOut;
167
wire SIERxTimeOutEn;
168
wire [7:0] RxFifoData;
169
wire fullSpeedRate;
170
wire fullSpeedPol;
171
wire connectSlaveToHost;
172
wire [7:0] SCTxPortData;
173
wire [7:0] SCTxPortCtrl;
174
wire [1:0] connectStateIn;
175
wire resumeDetectedIn;
176
wire [4:0] busAddress;
177
wire [7:0] busDataIn;
178
wire [7:0] busDataOut;
179
wire busWriteEn;
180
wire busStrobe_i;
181
wire SOFRxedIntOut;
182
wire resetEventIntOut;
183
wire resumeIntOut;
184
wire transDoneIntOut;
185
wire vBusDetIntOut;
186
wire NAKSentIntOut;
187
wire slaveControlSelect;
188
wire TxFifoEP0REn;
189
wire TxFifoEP1REn;
190
wire TxFifoEP2REn;
191
wire TxFifoEP3REn;
192
wire [7:0] TxFifoEP0Data;
193
wire [7:0] TxFifoEP1Data;
194
wire [7:0] TxFifoEP2Data;
195
wire [7:0] TxFifoEP3Data;
196
wire TxFifoEP0Empty;
197
wire TxFifoEP1Empty;
198
wire TxFifoEP2Empty;
199
wire TxFifoEP3Empty;
200
wire RxFifoEP0WEn;
201
wire RxFifoEP1WEn;
202
wire RxFifoEP2WEn;
203
wire RxFifoEP3WEn;
204
wire RxFifoEP0Full;
205
wire RxFifoEP1Full;
206
wire RxFifoEP2Full;
207
wire RxFifoEP3Full;
208
 
209
//internal wiring
210
wire [7:0] directCntlCntl;
211
wire [7:0] directCntlData;
212
wire directCntlGnt;
213
wire directCntlReq;
214
wire directCntlWEn;
215
wire [7:0] sendPacketCntl;
216
wire [7:0] sendPacketData;
217
wire sendPacketGnt;
218
wire sendPacketReq;
219
wire sendPacketWEn;
220
wire SCTxPortArbRdyOut;
221
wire transDone;
222
wire [1:0] directLineState;
223
wire directLineCtrlEn;
224
wire [3:0] RxPID;
225
wire [1:0] connectStateOut;
226
wire resumeIntFromRxStatusMon;
227
wire [1:0] endP0TransTypeReg;
228
wire [1:0] endP1TransTypeReg;
229
wire [1:0] endP2TransTypeReg;
230
wire [1:0] endP3TransTypeReg;
231
wire [1:0] endP0NAKTransTypeReg;
232
wire [1:0] endP1NAKTransTypeReg;
233
wire [1:0] endP2NAKTransTypeReg;
234
wire [1:0] endP3NAKTransTypeReg;
235
wire [4:0] endP0ControlReg;
236
wire [4:0] endP1ControlReg;
237
wire [4:0] endP2ControlReg;
238
wire [4:0] endP3ControlReg;
239
wire [7:0] endP0StatusReg;
240
wire [7:0] endP1StatusReg;
241
wire [7:0] endP2StatusReg;
242
wire [7:0] endP3StatusReg;
243
wire [6:0] USBTgtAddress;
244
wire [10:0] frameNum;
245
wire clrEP0Rdy;
246
wire clrEP1Rdy;
247
wire clrEP2Rdy;
248
wire clrEP3Rdy;
249
wire SCGlobalEn;
250
wire ACKRxed;
251
wire CRCError;
252
wire RXOverflow;
253
wire RXTimeOut;
254
wire bitStuffError;
255
wire dataSequence;
256
wire stallSent;
257
wire NAKSent;
258
wire SOFRxed;
259
wire [4:0] endPControlReg;
260
wire [1:0] transTypeNAK;
261
wire [1:0] transType;
262
wire [3:0] currEndP;
263
wire getPacketREn;
264
wire getPacketRdy;
265
wire [3:0] slaveControllerPIDOut;
266
wire slaveControllerReadyIn;
267
wire slaveControllerWEnOut;
268
wire TxFifoRE;
269
wire [7:0] TxFifoData;
270
wire TxFifoEmpty;
271
wire RxFifoWE;
272
wire RxFifoFull;
273
wire resetEventFromRxStatusMon;
274
wire clrEPRdy;
275
wire endPMuxErrorsWEn;
276
wire endPointReadyFromSlaveCtrlrToGetPkt;
277
 
278
USBSlaveControlBI_simlib u_USBSlaveControlBI
279
  (.address(busAddress),
280
  .dataIn(busDataIn),
281
  .dataOut(busDataOut),
282
  .writeEn(busWriteEn),
283
  .strobe_i(busStrobe_i),
284
  .busClk(busClk),
285
  .rstSyncToBusClk(rstSyncToBusClk),
286
  .usbClk(usbClk),
287
  .rstSyncToUsbClk(rstSyncToUsbClk),
288
  .SOFRxedIntOut(SOFRxedIntOut),
289
  .resetEventIntOut(resetEventIntOut),
290
  .resumeIntOut(resumeIntOut),
291
  .transDoneIntOut(transDoneIntOut),
292
  .vBusDetIntOut(vBusDetIntOut),
293
  .NAKSentIntOut(NAKSentIntOut),
294
  .endP0TransTypeReg(endP0TransTypeReg),
295
  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
296
  .endP1TransTypeReg(endP1TransTypeReg),
297
  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
298
  .endP2TransTypeReg(endP2TransTypeReg),
299
  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
300
  .endP3TransTypeReg(endP3TransTypeReg),
301
  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
302
  .endP0ControlReg(endP0ControlReg),
303
  .endP1ControlReg(endP1ControlReg),
304
  .endP2ControlReg(endP2ControlReg),
305
  .endP3ControlReg(endP3ControlReg),
306
  .EP0StatusReg(endP0StatusReg),
307
  .EP1StatusReg(endP1StatusReg),
308
  .EP2StatusReg(endP2StatusReg),
309
  .EP3StatusReg(endP3StatusReg),
310
  .SCAddrReg(USBTgtAddress),
311
  .frameNum(frameNum),
312
  .connectStateIn(connectStateOut),
313
  .vBusDetectIn(vBusDetect),
314
  .SOFRxedIn(SOFRxed),
315
  .resetEventIn(resetEventFromRxStatusMon),
316
  .resumeIntIn(resumeIntFromRxStatusMon),
317
  .transDoneIn(transDone),
318
  .NAKSentIn(NAKSent),
319
  .slaveControlSelect(slaveControlSelect),
320
  .clrEP0Ready(clrEP0Rdy),
321
  .clrEP1Ready(clrEP1Rdy),
322
  .clrEP2Ready(clrEP2Rdy),
323
  .clrEP3Ready(clrEP3Rdy),
324
  .TxLineState(directLineState),
325
  .LineDirectControlEn(directLineCtrlEn),
326
  .fullSpeedPol(fullSpeedPol),
327
  .fullSpeedRate(fullSpeedRate),
328
  .connectSlaveToHost(connectSlaveToHost),
329
  .SCGlobalEn(SCGlobalEn)
330
  );
331
 
332
slavecontroller_simlib u_slavecontroller
333
  (.CRCError(CRCError),
334
  .NAKSent(NAKSent),
335
  .RxByte(RxData),
336
  .RxDataWEn(RxDataValid),
337
  .RxOverflow(RXOverflow),
338
  .RxStatus(RxByteStatus),
339
  .RxTimeOut(RXTimeOut),
340
  .SCGlobalEn(SCGlobalEn),
341
  .SOFRxed(SOFRxed),
342
  .USBEndPControlReg(endPControlReg),
343
  .USBEndPNakTransTypeReg(transTypeNAK),
344
  .USBEndPTransTypeReg(transType),
345
  .USBEndP(currEndP),
346
  .USBTgtAddress(USBTgtAddress),
347
  .bitStuffError(bitStuffError),
348
  .clk(usbClk),
349
  .clrEPRdy(clrEPRdy),
350
  .endPMuxErrorsWEn(endPMuxErrorsWEn),
351
  .frameNum(frameNum),
352
  .getPacketREn(getPacketREn),
353
  .getPacketRdy(getPacketRdy),
354
  .rst(rstSyncToUsbClk),
355
  .sendPacketPID(slaveControllerPIDOut),
356
  .sendPacketRdy(slaveControllerReadyIn),
357
  .sendPacketWEn(slaveControllerWEnOut),
358
  .stallSent(stallSent),
359
  .transDone(transDone),
360
  .endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
361
    );
362
 
363
 
364
endpMux_simlib u_endpMux (
365
  .clk(usbClk),
366
  .rst(rstSyncToUsbClk),
367
  .currEndP(currEndP),
368
  .NAKSent(NAKSent),
369
  .stallSent(stallSent),
370
  .CRCError(CRCError),
371
  .bitStuffError(bitStuffError),
372
  .RxOverflow(RXOverflow),
373
  .RxTimeOut(RXTimeOut),
374
  .dataSequence(dataSequence),
375
  .ACKRxed(ACKRxed),
376
  .transType(transType),
377
  .transTypeNAK(transTypeNAK),
378
  .endPControlReg(endPControlReg),
379
  .clrEPRdy(clrEPRdy),
380
  .endPMuxErrorsWEn(endPMuxErrorsWEn),
381
  .endP0ControlReg(endP0ControlReg),
382
  .endP1ControlReg(endP1ControlReg),
383
  .endP2ControlReg(endP2ControlReg),
384
  .endP3ControlReg(endP3ControlReg),
385
  .endP0StatusReg(endP0StatusReg),
386
  .endP1StatusReg(endP1StatusReg),
387
  .endP2StatusReg(endP2StatusReg),
388
  .endP3StatusReg(endP3StatusReg),
389
  .endP0TransTypeReg(endP0TransTypeReg),
390
  .endP1TransTypeReg(endP1TransTypeReg),
391
  .endP2TransTypeReg(endP2TransTypeReg),
392
  .endP3TransTypeReg(endP3TransTypeReg),
393
  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
394
  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
395
  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
396
  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
397
  .clrEP0Rdy(clrEP0Rdy),
398
  .clrEP1Rdy(clrEP1Rdy),
399
  .clrEP2Rdy(clrEP2Rdy),
400
  .clrEP3Rdy(clrEP3Rdy)
401
    );
402
 
403
slaveSendPacket_simlib u_slaveSendPacket
404
  (.PID(slaveControllerPIDOut),
405
  .SCTxPortCntl(sendPacketCntl),
406
  .SCTxPortData(sendPacketData),
407
  .SCTxPortGnt(sendPacketGnt),
408
  .SCTxPortRdy(SCTxPortArbRdyOut),
409
  .SCTxPortReq(sendPacketReq),
410
  .SCTxPortWEn(sendPacketWEn),
411
  .clk(usbClk),
412
  .fifoData(TxFifoData),
413
  .fifoEmpty(TxFifoEmpty),
414
  .fifoReadEn(TxFifoRE),
415
  .rst(rstSyncToUsbClk),
416
  .sendPacketRdy(slaveControllerReadyIn),
417
  .sendPacketWEn(slaveControllerWEnOut) );
418
 
419
slaveDirectControl_simlib u_slaveDirectControl
420
  (.SCTxPortCntl(directCntlCntl),
421
  .SCTxPortData(directCntlData),
422
  .SCTxPortGnt(directCntlGnt),
423
  .SCTxPortRdy(SCTxPortArbRdyOut),
424
  .SCTxPortReq(directCntlReq),
425
  .SCTxPortWEn(directCntlWEn),
426
  .clk(usbClk),
427
  .directControlEn(directLineCtrlEn),
428
  .directControlLineState(directLineState),
429
  .rst(rstSyncToUsbClk) );
430
 
431
SCTxPortArbiter_simlib u_SCTxPortArbiter
432
  (.SCTxPortCntl(SCTxPortCtrl),
433
  .SCTxPortData(SCTxPortData),
434
  .SCTxPortRdyIn(SCTxPortRdy),
435
  .SCTxPortRdyOut(SCTxPortArbRdyOut),
436
  .SCTxPortWEnable(SCTxPortEn),
437
  .clk(usbClk),
438
  .directCntlCntl(directCntlCntl),
439
  .directCntlData(directCntlData),
440
  .directCntlGnt(directCntlGnt),
441
  .directCntlReq(directCntlReq),
442
  .directCntlWEn(directCntlWEn),
443
  .rst(rstSyncToUsbClk),
444
  .sendPacketCntl(sendPacketCntl),
445
  .sendPacketData(sendPacketData),
446
  .sendPacketGnt(sendPacketGnt),
447
  .sendPacketReq(sendPacketReq),
448
  .sendPacketWEn(sendPacketWEn) );
449
 
450
 
451
slaveGetPacket_simlib u_slaveGetPacket
452
  (.ACKRxed(ACKRxed),
453
  .CRCError(CRCError),
454
  .RXDataIn(RxData),
455
  .RXDataValid(RxDataValid),
456
  .RXFifoData(RxFifoData),
457
  .RXFifoFull(RxFifoFull),
458
  .RXFifoWEn(RxFifoWE),
459
  .RXPacketRdy(getPacketRdy),
460
  .RXStreamStatusIn(RxByteStatus),
461
  .RxPID(RxPID),
462
  .SIERxTimeOut(SIERxTimeOut),
463
  .SIERxTimeOutEn(SIERxTimeOutEn),
464
  .clk(usbClk),
465
  .RXOverflow(RXOverflow),
466
  .RXTimeOut(RXTimeOut),
467
  .bitStuffError(bitStuffError),
468
  .dataSequence(dataSequence),
469
  .getPacketEn(getPacketREn),
470
  .rst(rstSyncToUsbClk),
471
  .endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
472
  );
473
 
474
slaveRxStatusMonitor_simlib  u_slaveRxStatusMonitor
475
  (.connectStateIn(connectStateIn),
476
  .connectStateOut(connectStateOut),
477
  .resumeDetectedIn(resumeDetectedIn),
478
  .resetEventOut(resetEventFromRxStatusMon),
479
  .resumeIntOut(resumeIntFromRxStatusMon),
480
  .clk(usbClk),
481
  .rst(rstSyncToUsbClk)  );
482
 
483
fifoMux_simlib u_fifoMux (
484
  .currEndP(currEndP),
485
  //TxFifo
486
  .TxFifoREn(TxFifoRE),
487
  .TxFifoEP0REn(TxFifoEP0REn),
488
  .TxFifoEP1REn(TxFifoEP1REn),
489
  .TxFifoEP2REn(TxFifoEP2REn),
490
  .TxFifoEP3REn(TxFifoEP3REn),
491
  .TxFifoData(TxFifoData),
492
  .TxFifoEP0Data(TxFifoEP0Data),
493
  .TxFifoEP1Data(TxFifoEP1Data),
494
  .TxFifoEP2Data(TxFifoEP2Data),
495
  .TxFifoEP3Data(TxFifoEP3Data),
496
  .TxFifoEmpty(TxFifoEmpty),
497
  .TxFifoEP0Empty(TxFifoEP0Empty),
498
  .TxFifoEP1Empty(TxFifoEP1Empty),
499
  .TxFifoEP2Empty(TxFifoEP2Empty),
500
  .TxFifoEP3Empty(TxFifoEP3Empty),
501
  //RxFifo
502
  .RxFifoWEn(RxFifoWE),
503
  .RxFifoEP0WEn(RxFifoEP0WEn),
504
  .RxFifoEP1WEn(RxFifoEP1WEn),
505
  .RxFifoEP2WEn(RxFifoEP2WEn),
506
  .RxFifoEP3WEn(RxFifoEP3WEn),
507
  .RxFifoFull(RxFifoFull),
508
  .RxFifoEP0Full(RxFifoEP0Full),
509
  .RxFifoEP1Full(RxFifoEP1Full),
510
  .RxFifoEP2Full(RxFifoEP2Full),
511
  .RxFifoEP3Full(RxFifoEP3Full)
512
    );
513
 
514
endmodule
515
 
516
 
517
 
518
 
519
 
520
 
521
 

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