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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [usb_slave_tb.v] - Blame information for rev 449

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Line No. Rev Author Line
1 408 julius
// To be included in testbench
2
// Relies on USB slave signals to be declared
3
//       .usb0wiredataout                       (usb0wiredataout),
4
//      .usb0wirectrlout                        (usb0wirectrlout),
5
//      .usb0fullspeed                  (usb0fullspeed),
6
//      .usb0dpluspullup                        (usb0dpluspullup),
7
//      .usb0dminuspullup                       (usb0dminuspullup),
8
//      .usb0wiredatain                 (usb0wiredatain),
9
//      .usb0vbusdetect                 (usb0vbusdetect),
10
 
11
 
12
`define SIM_HOST_BASE_ADDR 9'h000
13
`define SIM_SLAVE_BASE_ADDR 9'h100
14
`define CLK_50MHZ_HALF_PERIOD 10.4
15
 wire usbClk;
16
 
17
 
18
wire [8:0] adr;
19
wire [7:0] masterDout;
20
wire [7:0] masterDin;
21
wire [7:0] usbSlaveDout;
22
wire [7:0] usbHostDout;
23
wire stb;
24
wire we;
25
wire ack;
26
wire host_stb;
27
wire slave_stb;
28
 
29
wire hostSOFSentIntOut;
30
wire hostConnEventIntOut;
31
wire hostResumeIntOut;
32
wire hostTransDoneIntOut;
33
 
34
wire usb0dPlusPullDown;
35
wire usb0dMinusPullDown;
36
 
37
reg USBWireVP;
38
reg USBWireVM;
39
reg dpu;
40
 
41
wire [1:0] hostUSBWireDataIn;
42
wire [1:0] hostUSBWireDataOut;
43
wire [1:0] slaveUSBWireDataIn;
44
wire [1:0] slaveUSBWireDataOut;
45
 
46
wire hostUSBWireCtrlOut;
47
wire usb0dpluspullup;
48
wire usb0dminuspullup;
49
 
50
assign usb0dpluspullup = dpu;
51
assign usb0dminuspullup  = 1'b0;
52
 
53
pullup(usb0dpluspullup);
54
pulldown(usb0dPlusPullDown);
55
pullup(usb0dminuspullup);
56
pulldown(usb0dMinusPullDown);
57
 
58
assign hostUSBWireDataIn = {USBWireVP, USBWireVM};
59
assign usb0wiredatain = {USBWireVP, USBWireVM};
60
//always @(hostUSBWireCtrlOut or usb0wirectrlout or hostUSBWireDataOut or slaveUSBWireDataOut or
61
//  DPlusPullup or usb0dPlusPullDown or usb0dminuspullup or usb0dMinusPullDown) begin
62
always @(*) begin
63
  if (hostUSBWireCtrlOut == 1'b1 && !usb0wirectrlout == 1'b0)
64
    {USBWireVP, USBWireVM} <= hostUSBWireDataOut;
65
  else if (hostUSBWireCtrlOut == 1'b0 && !usb0wirectrlout == 1'b1)
66
    {USBWireVP, USBWireVM} <= usb0wiredataout;
67
  else if (hostUSBWireCtrlOut == 1'b1 && !usb0wirectrlout == 1'b1)
68
    {USBWireVP, USBWireVM} <= 2'bxx;
69
  else if (hostUSBWireCtrlOut == 1'b0 && !usb0wirectrlout == 1'b0) begin
70
    if (usb0dpluspullup == 1'b1)
71
      USBWireVP <= usb0dpluspullup;
72
    else
73
      USBWireVP <= usb0dPlusPullDown;
74
    if (usb0dminuspullup == 1'b1)
75
      USBWireVM <= usb0dminuspullup;
76
    else
77
      USBWireVM <= usb0dMinusPullDown;
78
  end
79
end
80
 
81
 
82
 
83
assign host_stb = ~adr[8] & stb;
84
assign slave_stb = adr[8] & stb;
85
assign masterDin = host_stb == 1'b1 ? usbHostDout : usbSlaveDout;
86
 
87
//Parameters declaration: 
88
defparam u_usbhost.HOST_FIFO_DEPTH = 64;
89
parameter HOST_FIFO_DEPTH = 64;
90
defparam u_usbhost.HOST_FIFO_ADDR_WIDTH = 6;
91
parameter HOST_FIFO_ADDR_WIDTH = 6;
92
 
93
  clkgen clkgen1
94
     (
95
      .sys_clk_pad_i                   (clk),
96
`ifdef ETH_CLK_PLL
97
      .eth_clk_pad_i (),
98
`endif
99
      .wb_clk                    (),
100
      .sdram_clk                 (),
101
      .usb_clk                   (usbClk),
102
      .spw_clk                   (),
103
      .rst_i                     (!rst),
104
      .rst_o                     ()
105
      );
106
 
107
usbhost_simlib u_usbhost (
108
  .clk_i(clk),
109
  .rst_i(!rst),
110
  .address_i(adr[7:0]),
111
  .data_i(masterDout),
112
  .data_o(usbHostDout),
113
  .we_i(we),
114
  .strobe_i(host_stb),
115
  .ack_o(ack),
116
  .usbClk(usbClk),
117
 
118
  .hostSOFSentIntOut(hostSOFSentIntOut),
119
  .hostConnEventIntOut(hostConnEventIntOut),
120
  .hostResumeIntOut(hostResumeIntOut),
121
  .hostTransDoneIntOut(hostTransDoneIntOut),
122
  .USBWireDataIn(hostUSBWireDataIn),
123
  .USBWireDataInTick(USBWireDataInTick),
124
  .USBWireDataOut(hostUSBWireDataOut),
125
  .USBWireDataOutTick(USBWireDataOutTick),
126
  .USBWireCtrlOut(hostUSBWireCtrlOut),
127
  .USBFullSpeed()
128
 
129
 
130
);
131
wb_master_model #(.dwidth(8), .awidth(9)) u_wb_master_model (
132
  .clk(clk),
133
  .rst(!rst),
134
  .adr(adr),
135
  .din(masterDin),
136
  .dout(masterDout),
137
  .cyc(),
138
  .stb(stb),
139
  .we(we),
140
  .sel(),
141
  .ack(ack),
142
  .err(1'b0),
143
  .rty(1'b0)
144
);
145
 
146
 
147
//--------------- reset ---------------
148
//always begin
149
 // #`CLK_50MHZ_HALF_PERIOD usbClk <= 1'b0;
150
 // #`CLK_50MHZ_HALF_PERIOD usbClk <= 1'b1;
151
//end
152
 
153
 
154
 
155
 
156
 
157
 
158
reg [7:0] data;
159
reg [15:0] dataWord;
160
reg [7:0] dataRead;
161
reg [7:0] dataWrite;
162
reg [7:0] USBAddress;
163
reg [7:0] USBEndPoint;
164
reg [7:0] transType;
165
integer dataSize;
166
integer i;
167
integer j;
168
assign    usb0vbusdetect = 1'b1;
169
 
170
initial
171
begin
172
  dpu<=1'b0;
173
 
174
 
175
  wait (usb0fullspeed);
176
   $write("USB Slave test starts at:%t\n",$time);
177
   dpu<=1'b1;
178
  #14000;
179
 
180
 
181
  u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
182
  $display("Host Version number = 0x%0x\n", dataRead);
183
 
184
  $write("Testing host register read/write  ");
185
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
186
  u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
187
  $write("--- PASSED\n");
188
 
189
 
190
  $write("Testing register reset  ");
191
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
192
  //u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
193
  #1000;
194
  u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h00);
195
  //u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h00);
196
  $write("--- PASSED\n");
197
  #1000;
198
 
199
  $write("Configure host   ");
200
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h1);
201
  $write("Connect full speed  ");
202
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
203
  #20000;
204
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
205
 
206
  $write("--- PASSED\n");
207
  #225000;
208
 
209
  //Transfer 1
210
  $write("Trans test 1: Device address = 0x63, 2 byte SETUP transaction to Endpoint 0. ");
211
  USBAddress = 8'h63;
212
  USBEndPoint = 8'h00;
213
  transType = `SETUP_TRANS;
214
  dataSize = 2;
215
 
216
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
217
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
218
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
219
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
220
  data = 8'h00;
221
  for (i=0; i<dataSize; i=i+1) begin
222
    u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
223
    data = data + 1'b1;
224
  end
225
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
226
  #35000
227
 
228
 
229
   u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
230
   $write(" Transaction done correct interrupt recived " );
231
 
232
 
233
  $write("Checking receive data  ");
234
  data = 8'h00;
235
  for (i=0; i<dataSize; i=i+1) begin
236
 
237
    data = data + 1'b1;
238
  end
239
  $write("--- PASSED\n");
240
 
241
  //Transfer 2
242
  $write("Trans test 2: Device address = 0x63, 20 byte OUT DATA0 transaction to Endpoint 1. ");
243
  USBAddress = 8'h63;
244
  USBEndPoint = 8'h00;
245
  transType = `OUTDATA0_TRANS;
246
  dataSize = 20;
247
 u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
248
 
249
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
250
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
251
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
252
  data = 8'h00;
253
  for (i=0; i<dataSize; i=i+1) begin
254
    u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
255
    data = data + 1'b1;
256
  end
257
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
258
  #20000
259
 
260
  $write("Checking received Transaction done interupt  ");
261
  u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
262
 
263
  $write("Checking receive data  ");
264
  data = 8'h00;
265
  for (i=0; i<dataSize; i=i+1) begin
266
    //u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP1_RX_FIFO_BASE + `FIFO_DATA_REG , data);
267
    data = data + 1'b1;
268
  end
269
  $write("--- PASSED\n");
270
   #200000
271
 
272
   //Transfer 3
273
   $write("Trans test 3: Device address = 0x63, 20 byte OUT DATA0 transaction to Endpoint 1. ");
274
  USBAddress = 8'h63;
275
  USBEndPoint = 8'h00;
276
  transType = `OUTDATA0_TRANS;
277
  dataSize = 2;
278
 u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
279
  //enable endpoint, and make ready
280
 
281
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
282
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
283
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
284
  data = 8'h00;
285
  for (i=0; i<dataSize; i=i+1) begin
286
    u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
287
    data = data + 1'b1;
288
  end
289
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
290
  #20000
291
 
292
  $write("Checking received Transaction done interupt\n  ");
293
  u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
294
 
295
 
296
  data = 8'h00;
297
  for (i=0; i<dataSize; i=i+1) begin
298
    //u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP1_RX_FIFO_BASE + `FIFO_DATA_REG , data);
299
    data = data + 1'b1;
300
  end
301
  $write("--- PASSED\n");
302
   #200000
303
 
304
  //Transfer 4 
305
    $write("Trans test 4: Device address = 0x63, 2 byte IN transaction to Endpoint 2. ");
306
  USBAddress = 8'h63;
307
  USBEndPoint = 8'h02;
308
  transType = `IN_TRANS;
309
  dataSize = 20;
310
  //enable endpoint, and make ready
311
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h3f);
312
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
313
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
314
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
315
  data = 8'h00;
316
  for (i=0; i<dataSize; i=i+1) begin
317
    //u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `EP2_TX_FIFO_BASE + `FIFO_DATA_REG , data);
318
    data = data + 1'b1;
319
  end
320
   #20000
321
  u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
322
  #200000
323
  //expecting transaction done interrupt
324
     $write("USB Slave transaction done interrupt at:%t\n",$time);
325
  u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
326
 
327
 
328
    $write("Checking receive data  ");
329
  data = 8'h0;
330
  for (i=0; i<dataSize; i=i+1) begin
331
    u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ,data);
332
    data = data + 1'b1;
333
  end
334
  $write("--- PASSED\n");
335
 
336
  $write("Finished all tests\n");
337
 
338
 
339
 
340
  $stop;
341
 
342
end
343
 
344
 

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