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julius |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// usbSlave.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// Top level module
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module usbslave_simlib(
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clk_i,
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rst_i,
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address_i,
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| 50 |
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data_i,
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| 51 |
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data_o,
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we_i,
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strobe_i,
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| 54 |
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ack_o,
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| 55 |
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usbClk,
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| 56 |
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slaveVBusDetIntOut,
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| 57 |
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slaveNAKSentIntOut,
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| 58 |
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slaveSOFRxedIntOut,
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| 59 |
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slaveResetEventIntOut,
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| 60 |
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slaveResumeIntOut,
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| 61 |
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slaveTransDoneIntOut,
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| 62 |
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USBWireDataIn,
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| 63 |
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USBWireDataInTick,
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| 64 |
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USBWireDataOut,
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| 65 |
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USBWireDataOutTick,
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USBWireCtrlOut,
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| 67 |
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USBFullSpeed,
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| 68 |
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USBDPlusPullup,
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USBDMinusPullup,
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vBusDetect
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| 71 |
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);
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parameter EP0_FIFO_DEPTH = 64;
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parameter EP0_FIFO_ADDR_WIDTH = 6;
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parameter EP1_FIFO_DEPTH = 64;
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parameter EP1_FIFO_ADDR_WIDTH = 6;
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parameter EP2_FIFO_DEPTH = 64;
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parameter EP2_FIFO_ADDR_WIDTH = 6;
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parameter EP3_FIFO_DEPTH = 64;
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parameter EP3_FIFO_ADDR_WIDTH = 6;
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input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
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input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
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input [7:0] address_i; //Wishbone bus address in
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input [7:0] data_i; //Wishbone bus data in
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| 85 |
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output [7:0] data_o; //Wishbone bus data out
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input we_i; //Wishbone bus write enable in
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input strobe_i; //Wishbone bus strobe in
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output ack_o; //Wishbone bus acknowledge out
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input usbClk; //usb clock. 48Mhz +/-0.25%
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output slaveSOFRxedIntOut;
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output slaveResetEventIntOut;
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output slaveResumeIntOut;
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output slaveTransDoneIntOut;
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output slaveNAKSentIntOut;
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output slaveVBusDetIntOut;
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input [1:0] USBWireDataIn;
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output [1:0] USBWireDataOut;
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output USBWireDataOutTick;
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output USBWireDataInTick;
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output USBWireCtrlOut;
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output USBFullSpeed;
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output USBDPlusPullup;
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output USBDMinusPullup;
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input vBusDetect;
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wire clk_i;
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wire rst_i;
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wire [7:0] address_i;
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wire [7:0] data_i;
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wire [7:0] data_o;
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wire we_i;
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| 112 |
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wire strobe_i;
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| 113 |
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wire ack_o;
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| 114 |
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wire usbClk;
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wire slaveSOFRxedIntOut;
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wire slaveResetEventIntOut;
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| 117 |
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wire slaveResumeIntOut;
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| 118 |
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wire slaveTransDoneIntOut;
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wire slaveNAKSentIntOut;
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| 120 |
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wire slaveVBusDetIntOut;
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wire [1:0] USBWireDataIn;
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wire [1:0] USBWireDataOut;
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wire USBWireDataOutTick;
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wire USBWireDataInTick;
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wire USBWireCtrlOut;
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wire USBFullSpeed;
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wire USBDPlusPullup;
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wire USBDMinusPullup;
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wire vBusDetect;
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//internal wiring
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wire slaveControlSel;
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wire hostSlaveMuxSel;
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wire [7:0] dataFromSlaveControl;
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wire [7:0] dataFromHostSlaveMux;
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wire [7:0] RxCtrlOut;
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wire [7:0] RxDataFromSIE;
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wire RxDataOutWEn;
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wire fullSpeedBitRateFromSlave;
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wire fullSpeedPolarityFromSlave;
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wire SIEPortWEnFromSlave;
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wire SIEPortTxRdy;
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wire [7:0] SIEPortDataInFromSlave;
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wire [7:0] SIEPortCtrlInFromSlave;
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wire [1:0] connectState;
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wire resumeDetected;
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wire [7:0] SIEPortDataInToSIE;
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wire SIEPortWEnToSIE;
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wire [7:0] SIEPortCtrlInToSIE;
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wire fullSpeedPolarityToSIE;
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wire fullSpeedBitRateToSIE;
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wire connectSlaveToHost;
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wire noActivityTimeOut;
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wire TxFifoEP0REn;
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wire TxFifoEP1REn;
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wire TxFifoEP2REn;
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wire TxFifoEP3REn;
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wire [7:0] TxFifoEP0Data;
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wire [7:0] TxFifoEP1Data;
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wire [7:0] TxFifoEP2Data;
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wire [7:0] TxFifoEP3Data;
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wire TxFifoEP0Empty;
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wire TxFifoEP1Empty;
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wire TxFifoEP2Empty;
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wire TxFifoEP3Empty;
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wire RxFifoEP0WEn;
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wire RxFifoEP1WEn;
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wire RxFifoEP2WEn;
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wire RxFifoEP3WEn;
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wire RxFifoEP0Full;
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wire RxFifoEP1Full;
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wire RxFifoEP2Full;
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wire RxFifoEP3Full;
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wire [7:0] slaveRxFifoData;
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wire [7:0] dataFromEP0RxFifo;
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wire [7:0] dataFromEP1RxFifo;
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wire [7:0] dataFromEP2RxFifo;
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wire [7:0] dataFromEP3RxFifo;
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wire [7:0] dataFromEP0TxFifo;
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wire [7:0] dataFromEP1TxFifo;
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| 181 |
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wire [7:0] dataFromEP2TxFifo;
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| 182 |
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wire [7:0] dataFromEP3TxFifo;
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| 183 |
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wire slaveEP0RxFifoSel;
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wire slaveEP1RxFifoSel;
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wire slaveEP2RxFifoSel;
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| 186 |
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wire slaveEP3RxFifoSel;
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| 187 |
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wire slaveEP0TxFifoSel;
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wire slaveEP1TxFifoSel;
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| 189 |
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wire slaveEP2TxFifoSel;
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wire slaveEP3TxFifoSel;
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wire rstSyncToBusClk;
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wire rstSyncToUsbClk;
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wire noActivityTimeOutEnableToSIE;
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| 194 |
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wire noActivityTimeOutEnableFromHost;
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wire noActivityTimeOutEnableFromSlave;
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assign USBFullSpeed = fullSpeedBitRateToSIE;
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assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
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assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
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usbSlaveControl_simlib u_usbSlaveControl(
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.busClk(clk_i),
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.rstSyncToBusClk(rstSyncToBusClk),
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.usbClk(usbClk),
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.rstSyncToUsbClk(rstSyncToUsbClk),
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.RxByteStatus(RxCtrlOut),
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.RxData(RxDataFromSIE),
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.RxDataValid(RxDataOutWEn),
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.SIERxTimeOut(noActivityTimeOut),
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.SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
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.RxFifoData(slaveRxFifoData),
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.connectSlaveToHost(connectSlaveToHost),
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| 213 |
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.fullSpeedRate(fullSpeedBitRateFromSlave),
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.fullSpeedPol(fullSpeedPolarityFromSlave),
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| 215 |
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.SCTxPortEn(SIEPortWEnFromSlave),
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| 216 |
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.SCTxPortRdy(SIEPortTxRdy),
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| 217 |
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.SCTxPortData(SIEPortDataInFromSlave),
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.SCTxPortCtrl(SIEPortCtrlInFromSlave),
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.vBusDetect(vBusDetect),
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.connectStateIn(connectState),
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.resumeDetectedIn(resumeDetected),
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.busAddress(address_i[4:0]),
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| 223 |
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.busDataIn(data_i),
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| 224 |
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.busDataOut(dataFromSlaveControl),
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| 225 |
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.busWriteEn(we_i),
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| 226 |
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.busStrobe_i(strobe_i),
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| 227 |
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.SOFRxedIntOut(slaveSOFRxedIntOut),
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| 228 |
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.resetEventIntOut(slaveResetEventIntOut),
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| 229 |
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.resumeIntOut(slaveResumeIntOut),
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| 230 |
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.transDoneIntOut(slaveTransDoneIntOut),
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| 231 |
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.NAKSentIntOut(slaveNAKSentIntOut),
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| 232 |
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.vBusDetIntOut(slaveVBusDetIntOut),
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| 233 |
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.slaveControlSelect(slaveControlSel),
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| 234 |
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.TxFifoEP0REn(TxFifoEP0REn),
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.TxFifoEP1REn(TxFifoEP1REn),
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.TxFifoEP2REn(TxFifoEP2REn),
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| 237 |
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.TxFifoEP3REn(TxFifoEP3REn),
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| 238 |
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.TxFifoEP0Data(TxFifoEP0Data),
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| 239 |
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.TxFifoEP1Data(TxFifoEP1Data),
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| 240 |
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.TxFifoEP2Data(TxFifoEP2Data),
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| 241 |
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.TxFifoEP3Data(TxFifoEP3Data),
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| 242 |
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.TxFifoEP0Empty(TxFifoEP0Empty),
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| 243 |
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.TxFifoEP1Empty(TxFifoEP1Empty),
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| 244 |
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.TxFifoEP2Empty(TxFifoEP2Empty),
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| 245 |
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.TxFifoEP3Empty(TxFifoEP3Empty),
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| 246 |
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.RxFifoEP0WEn(RxFifoEP0WEn),
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| 247 |
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.RxFifoEP1WEn(RxFifoEP1WEn),
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| 248 |
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.RxFifoEP2WEn(RxFifoEP2WEn),
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| 249 |
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.RxFifoEP3WEn(RxFifoEP3WEn),
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| 250 |
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.RxFifoEP0Full(RxFifoEP0Full),
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| 251 |
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.RxFifoEP1Full(RxFifoEP1Full),
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| 252 |
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.RxFifoEP2Full(RxFifoEP2Full),
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| 253 |
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.RxFifoEP3Full(RxFifoEP3Full)
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| 254 |
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);
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| 255 |
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| 256 |
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wishBoneBI_simlib u_wishBoneBI (
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| 258 |
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.address(address_i),
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| 259 |
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.dataIn(data_i),
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| 260 |
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.dataOut(data_o),
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| 261 |
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.writeEn(we_i),
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| 262 |
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.strobe_i(strobe_i),
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| 263 |
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.ack_o(ack_o),
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| 264 |
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.clk(clk_i),
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| 265 |
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.rst(rstSyncToBusClk),
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| 266 |
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.hostControlSel(),
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| 267 |
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.hostRxFifoSel(),
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| 268 |
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.hostTxFifoSel(),
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| 269 |
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.slaveControlSel(slaveControlSel),
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| 270 |
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.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
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| 271 |
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.slaveEP1RxFifoSel(slaveEP1RxFifoSel),
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| 272 |
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.slaveEP2RxFifoSel(slaveEP2RxFifoSel),
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| 273 |
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.slaveEP3RxFifoSel(slaveEP3RxFifoSel),
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| 274 |
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.slaveEP0TxFifoSel(slaveEP0TxFifoSel),
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| 275 |
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.slaveEP1TxFifoSel(slaveEP1TxFifoSel),
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| 276 |
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.slaveEP2TxFifoSel(slaveEP2TxFifoSel),
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| 277 |
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.slaveEP3TxFifoSel(slaveEP3TxFifoSel),
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| 278 |
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.hostSlaveMuxSel(hostSlaveMuxSel),
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| 279 |
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.dataFromHostControl(8'h00),
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| 280 |
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.dataFromHostRxFifo(8'h00),
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| 281 |
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.dataFromHostTxFifo(8'h00),
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| 282 |
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.dataFromSlaveControl(dataFromSlaveControl),
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| 283 |
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.dataFromEP0RxFifo(dataFromEP0RxFifo),
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| 284 |
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.dataFromEP1RxFifo(dataFromEP1RxFifo),
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| 285 |
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.dataFromEP2RxFifo(dataFromEP2RxFifo),
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| 286 |
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.dataFromEP3RxFifo(dataFromEP3RxFifo),
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| 287 |
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.dataFromEP0TxFifo(dataFromEP0TxFifo),
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| 288 |
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.dataFromEP1TxFifo(dataFromEP1TxFifo),
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| 289 |
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.dataFromEP2TxFifo(dataFromEP2TxFifo),
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| 290 |
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.dataFromEP3TxFifo(dataFromEP3TxFifo),
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| 291 |
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.dataFromHostSlaveMux(dataFromHostSlaveMux)
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| 292 |
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);
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| 293 |
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| 294 |
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| 295 |
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| 296 |
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assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave;
|
| 297 |
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assign SIEPortDataInToSIE = SIEPortDataInFromSlave;
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| 298 |
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assign SIEPortWEnToSIE = SIEPortWEnFromSlave;
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| 299 |
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assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave;
|
| 300 |
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assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave;
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| 301 |
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assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave;
|
| 302 |
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| 303 |
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hostSlaveMuxBI_simlib u_hostSlaveMuxBI (
|
| 304 |
|
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.dataIn(data_i),
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| 305 |
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.dataOut(dataFromHostSlaveMux),
|
| 306 |
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.address(address_i[0]),
|
| 307 |
|
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.writeEn(we_i),
|
| 308 |
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.strobe_i(strobe_i),
|
| 309 |
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.usbClk(usbClk),
|
| 310 |
|
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.busClk(clk_i),
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| 311 |
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.hostSlaveMuxSel(hostSlaveMuxSel),
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| 312 |
|
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.hostMode(),
|
| 313 |
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.rstFromWire(rst_i),
|
| 314 |
|
|
.rstSyncToBusClkOut(rstSyncToBusClk),
|
| 315 |
|
|
.rstSyncToUsbClkOut(rstSyncToUsbClk)
|
| 316 |
|
|
);
|
| 317 |
|
|
|
| 318 |
|
|
usbSerialInterfaceEngine_simlib u_usbSerialInterfaceEngine(
|
| 319 |
|
|
.clk(usbClk),
|
| 320 |
|
|
.rst(rstSyncToUsbClk),
|
| 321 |
|
|
.USBWireDataIn(USBWireDataIn),
|
| 322 |
|
|
.USBWireDataOut(USBWireDataOut),
|
| 323 |
|
|
.USBWireDataInTick(USBWireDataInTick),
|
| 324 |
|
|
.USBWireDataOutTick(USBWireDataOutTick),
|
| 325 |
|
|
.USBWireCtrlOut(USBWireCtrlOut),
|
| 326 |
|
|
.connectState(connectState),
|
| 327 |
|
|
.resumeDetected(resumeDetected),
|
| 328 |
|
|
.RxCtrlOut(RxCtrlOut),
|
| 329 |
|
|
.RxDataOutWEn(RxDataOutWEn),
|
| 330 |
|
|
.RxDataOut(RxDataFromSIE),
|
| 331 |
|
|
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
|
| 332 |
|
|
.SIEPortDataIn(SIEPortDataInToSIE),
|
| 333 |
|
|
.SIEPortTxRdy(SIEPortTxRdy),
|
| 334 |
|
|
.SIEPortWEn(SIEPortWEnToSIE),
|
| 335 |
|
|
.fullSpeedPolarity(fullSpeedPolarityToSIE),
|
| 336 |
|
|
.fullSpeedBitRate(fullSpeedBitRateToSIE),
|
| 337 |
|
|
.noActivityTimeOut(noActivityTimeOut),
|
| 338 |
|
|
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
|
| 339 |
|
|
);
|
| 340 |
|
|
|
| 341 |
|
|
|
| 342 |
|
|
|
| 343 |
|
|
//---Slave fifos
|
| 344 |
|
|
|
| 345 |
|
|
TxFifo_simlib #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
|
| 346 |
|
|
.usbClk(usbClk),
|
| 347 |
|
|
.busClk(clk_i),
|
| 348 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 349 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 350 |
|
|
.fifoREn(TxFifoEP0REn),
|
| 351 |
|
|
.fifoEmpty(TxFifoEP0Empty),
|
| 352 |
|
|
.busAddress(address_i[2:0]),
|
| 353 |
|
|
.busWriteEn(we_i),
|
| 354 |
|
|
.busStrobe_i(strobe_i),
|
| 355 |
|
|
.busFifoSelect(slaveEP0TxFifoSel),
|
| 356 |
|
|
.busDataIn(data_i),
|
| 357 |
|
|
.busDataOut(dataFromEP0TxFifo),
|
| 358 |
|
|
.fifoDataOut(TxFifoEP0Data) );
|
| 359 |
|
|
|
| 360 |
|
|
TxFifo_simlib #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
|
| 361 |
|
|
.usbClk(usbClk),
|
| 362 |
|
|
.busClk(clk_i),
|
| 363 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 364 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 365 |
|
|
.fifoREn(TxFifoEP1REn),
|
| 366 |
|
|
.fifoEmpty(TxFifoEP1Empty),
|
| 367 |
|
|
.busAddress(address_i[2:0]),
|
| 368 |
|
|
.busWriteEn(we_i),
|
| 369 |
|
|
.busStrobe_i(strobe_i),
|
| 370 |
|
|
.busFifoSelect(slaveEP1TxFifoSel),
|
| 371 |
|
|
.busDataIn(data_i),
|
| 372 |
|
|
.busDataOut(dataFromEP1TxFifo),
|
| 373 |
|
|
.fifoDataOut(TxFifoEP1Data) );
|
| 374 |
|
|
|
| 375 |
|
|
TxFifo_simlib #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
|
| 376 |
|
|
.usbClk(usbClk),
|
| 377 |
|
|
.busClk(clk_i),
|
| 378 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 379 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 380 |
|
|
.fifoREn(TxFifoEP2REn),
|
| 381 |
|
|
.fifoEmpty(TxFifoEP2Empty),
|
| 382 |
|
|
.busAddress(address_i[2:0]),
|
| 383 |
|
|
.busWriteEn(we_i),
|
| 384 |
|
|
.busStrobe_i(strobe_i),
|
| 385 |
|
|
.busFifoSelect(slaveEP2TxFifoSel),
|
| 386 |
|
|
.busDataIn(data_i),
|
| 387 |
|
|
.busDataOut(dataFromEP2TxFifo),
|
| 388 |
|
|
.fifoDataOut(TxFifoEP2Data) );
|
| 389 |
|
|
|
| 390 |
|
|
TxFifo_simlib #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
|
| 391 |
|
|
.usbClk(usbClk),
|
| 392 |
|
|
.busClk(clk_i),
|
| 393 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 394 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 395 |
|
|
.fifoREn(TxFifoEP3REn),
|
| 396 |
|
|
.fifoEmpty(TxFifoEP3Empty),
|
| 397 |
|
|
.busAddress(address_i[2:0]),
|
| 398 |
|
|
.busWriteEn(we_i),
|
| 399 |
|
|
.busStrobe_i(strobe_i),
|
| 400 |
|
|
.busFifoSelect(slaveEP3TxFifoSel),
|
| 401 |
|
|
.busDataIn(data_i),
|
| 402 |
|
|
.busDataOut(dataFromEP3TxFifo),
|
| 403 |
|
|
.fifoDataOut(TxFifoEP3Data) );
|
| 404 |
|
|
|
| 405 |
|
|
RxFifo_simlib #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
|
| 406 |
|
|
.usbClk(usbClk),
|
| 407 |
|
|
.busClk(clk_i),
|
| 408 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 409 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 410 |
|
|
.fifoWEn(RxFifoEP0WEn),
|
| 411 |
|
|
.fifoFull(RxFifoEP0Full),
|
| 412 |
|
|
.busAddress(address_i[2:0]),
|
| 413 |
|
|
.busWriteEn(we_i),
|
| 414 |
|
|
.busStrobe_i(strobe_i),
|
| 415 |
|
|
.busFifoSelect(slaveEP0RxFifoSel),
|
| 416 |
|
|
.busDataIn(data_i),
|
| 417 |
|
|
.busDataOut(dataFromEP0RxFifo),
|
| 418 |
|
|
.fifoDataIn(slaveRxFifoData) );
|
| 419 |
|
|
|
| 420 |
|
|
RxFifo_simlib #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
|
| 421 |
|
|
.usbClk(usbClk),
|
| 422 |
|
|
.busClk(clk_i),
|
| 423 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 424 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 425 |
|
|
.fifoWEn(RxFifoEP1WEn),
|
| 426 |
|
|
.fifoFull(RxFifoEP1Full),
|
| 427 |
|
|
.busAddress(address_i[2:0]),
|
| 428 |
|
|
.busWriteEn(we_i),
|
| 429 |
|
|
.busStrobe_i(strobe_i),
|
| 430 |
|
|
.busFifoSelect(slaveEP1RxFifoSel),
|
| 431 |
|
|
.busDataIn(data_i),
|
| 432 |
|
|
.busDataOut(dataFromEP1RxFifo),
|
| 433 |
|
|
.fifoDataIn(slaveRxFifoData) );
|
| 434 |
|
|
|
| 435 |
|
|
RxFifo_simlib #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
|
| 436 |
|
|
.usbClk(usbClk),
|
| 437 |
|
|
.busClk(clk_i),
|
| 438 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 439 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 440 |
|
|
.fifoWEn(RxFifoEP2WEn),
|
| 441 |
|
|
.fifoFull(RxFifoEP2Full),
|
| 442 |
|
|
.busAddress(address_i[2:0]),
|
| 443 |
|
|
.busWriteEn(we_i),
|
| 444 |
|
|
.busStrobe_i(strobe_i),
|
| 445 |
|
|
.busFifoSelect(slaveEP2RxFifoSel),
|
| 446 |
|
|
.busDataIn(data_i),
|
| 447 |
|
|
.busDataOut(dataFromEP2RxFifo),
|
| 448 |
|
|
.fifoDataIn(slaveRxFifoData) );
|
| 449 |
|
|
|
| 450 |
|
|
RxFifo_simlib #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
|
| 451 |
|
|
.usbClk(usbClk),
|
| 452 |
|
|
.busClk(clk_i),
|
| 453 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 454 |
|
|
.rstSyncToUsbClk(rstSyncToUsbClk),
|
| 455 |
|
|
.fifoWEn(RxFifoEP3WEn),
|
| 456 |
|
|
.fifoFull(RxFifoEP3Full),
|
| 457 |
|
|
.busAddress(address_i[2:0]),
|
| 458 |
|
|
.busWriteEn(we_i),
|
| 459 |
|
|
.busStrobe_i(strobe_i),
|
| 460 |
|
|
.busFifoSelect(slaveEP3RxFifoSel),
|
| 461 |
|
|
.busDataIn(data_i),
|
| 462 |
|
|
.busDataOut(dataFromEP3RxFifo),
|
| 463 |
|
|
.fifoDataIn(slaveRxFifoData) );
|
| 464 |
|
|
|
| 465 |
|
|
|
| 466 |
|
|
|
| 467 |
|
|
endmodule
|
| 468 |
|
|
|
| 469 |
|
|
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
|
| 473 |
|
|
|
| 474 |
|
|
|
