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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.c] - Blame information for rev 40

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/*$$HEADER*/
/******************************************************************************/
/*                                                                            */
/*                    H E A D E R   I N F O R M A T I O N                     */
/*                                                                            */
/******************************************************************************/
 
// Project Name                   : ORPSoCv2
// File Name                      : rsp-rtl_sim.c
// Prepared By                    : jb, jb@orsoc.se
// Project Start                  : 2009-05-01
 
/*$$COPYRIGHT NOTICE*/
/******************************************************************************/
/*                                                                            */
/*                      C O P Y R I G H T   N O T I C E                       */
/*                                                                            */
/******************************************************************************/
/*
  This library is free software; you can redistribute it and/or
  modify it under the terms of the GNU Lesser General Public
  License as published by the Free Software Foundation;
  version 2.1 of the License, a copy of which is available from
  http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
 
  This library is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  Lesser General Public License for more details.
 
  You should have received a copy of the GNU Lesser General Public
  License along with this library; if not, write to the Free Software
  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
*/
 
 
/* Establishes GDB proxy server and communicates via pipes
   to some functions running under the VPI in an RTL sim */
 
#include <stdio.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <assert.h>
 
#include <ctype.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdarg.h>
#include <fcntl.h>
#include <errno.h>
#include <signal.h>
 
#include "gdb.h"
#include "rsp-rtl_sim.h"
#include "rsp-vpi.h"
 
static int err = 0;
 
/* Currently selected scan chain - just to prevent unnecessary
   transfers. */
static int current_chain = -1;
 
/* The chain that should be currently selected. */
static int dbg_chain = -1;
 
/* Crc of current read or written data.  */
static int crc_r, crc_w = 0;
 
/* Generates new crc, sending in new bit input_bit */
static uint32_t crc_calc(uint32_t crc, int input_bit) {
  uint32_t d = (input_bit&1) ? 0xfffffff : 0x0000000;
  uint32_t crc_32 = ((crc >> 31)&1) ? 0xfffffff : 0x0000000;
  crc <<= 1;
  return crc ^ (d ^ crc_32) & DBG_CRC_POLY;
}
 
/* VPI communication prototyopes */
static void get_response_from_vpi();
static void get_data_from_vpi();
static void get_block_data_from_vpi(int len, uint32_t *data);
static void send_data_to_vpi(uint32_t data);
static void send_block_data_to_vpi(int len, uint32_t *data);
static void send_address_to_vpi(uint32_t address);
static void send_command_to_vpi(char CMD);
 
void send_command_to_vpi(char CMD)
{
  // first thing we do  is send a command
  // and wait for an ack
  int n;
  char cmd_resp;
 
 
  //n = write(rsp_to_vpi_pipe[1],&CMD, 1); // send the command to the sim
  n = write(command_pipe[1],&CMD, 1); // send the command to the sim
 
  if (n < 0)   error("ERROR writing to VPI FIFO");
 
  n = read(vpi_to_rsp_pipe[0],&cmd_resp,1); // block and wait for the ack
 
  if (cmd_resp != CMD) error("Response from RTL sim incorrect"); //check it acked with cmd
 
  return;
}
 
void send_address_to_vpi(uint32_t address)
{
  // Now send address
  int n;
 
  char* send_buf;
 
  send_buf = (char *) &address;
 
  n = write(rsp_to_vpi_pipe[1],send_buf, 4); // send the address to the sim
 
  if (n < 0)   error("ERROR writing to VPI socket");
 
  return;
}
 
void send_data_to_vpi(uint32_t data)
{
  // Now send data
  int n;
 
  char* send_buf;
 
  send_buf = (char *) &data;
 
  n = write(rsp_to_vpi_pipe[1],send_buf, 4); // Write the data to the socket
 
  if (n < 0)   error("ERROR writing to VPI socket");
 
  return;
 
}
 
void send_block_data_to_vpi(int len, uint32_t *data)
{
  // Now send data
  int n, i;
 
  char* send_buf;
 
  send_buf = (char *) data;
 
  n = write(rsp_to_vpi_pipe[1],send_buf, len); // Write the data to the fifo
 
  if (n < 0)   error("ERROR writing to VPI socket");
 
  return;
 
}
 
void get_data_from_vpi(uint32_t* data)
{
 
  int n;
 
  uint32_t inc_data;
 
  char* recv_buf;
 
  recv_buf = (char*) &inc_data;
 
  n = read(vpi_to_rsp_pipe[0],recv_buf,4); // block and wait for the data
 
  if (DBG_VPI) printf("rsp-rtl_sim: get_data_from_vpi: 0x%.8x\n",inc_data);
 
  *data = inc_data;
 
  return;
 
}
 
void get_block_data_from_vpi(int len, uint32_t* data)
{
  int n, i, status;
 
  uint32_t inc_data;
 
  char* recv_buf;
 
  uint32_t* data_ptr;
 
  recv_buf = (char *) data;
 
  n=0;
 
  while (n < len)
    {
 
      status = read(vpi_to_rsp_pipe[0], recv_buf, len - n); // block and wait for the data
 
      if (status > 0) n += status; // we read "status" number of bytes
 
    }
 
 
  if (DBG_VPI){
    printf("rsp-rtl_sim: get_block_data_from_vpi: %d bytes",len);
    for (i = 0;i < (len/4); i++)
      {
        printf("0x%.8x ",data[i]);
      }
    printf("\n");
  }
 
  return;
 
}
 
void get_response_from_vpi()
{
  // Basically just wait for the response from VPI
  // by blocking wait on recv
 
  int n = 0;
  char tmp;
 
  n = read(vpi_to_rsp_pipe[0],&tmp,1); // block and wait
 
  return;
}
 
/* Resets JTAG
   Writes TRST=0
   and    TRST=1 */
static void jp2_reset_JTAG() {
  int i;
 
  debug2("\nreset(");
 
  send_command_to_vpi(CMD_RESET);
 
  get_response_from_vpi();
 
  debug2(")\n");
 
}
 
/* Resets JTAG, and sets DEBUG scan chain */
 int dbg_reset() {
 
   int err;
   uint32_t id;
 
   jp2_reset_JTAG();
 
  /* set idcode jtag chain */
  send_command_to_vpi(CMD_JTAG_SET_IR);
 
  send_data_to_vpi(JI_IDCODE);
 
  get_response_from_vpi();
 
  /* now read out the jtag id */
  send_command_to_vpi(CMD_READ_JTAG_ID);
 
  //id = get_data_from_vpi();  
  get_data_from_vpi((uint32_t *)&id);
 
  get_response_from_vpi();
 
  printf("JTAG ID = %08x\n", id);
 
  /* now set the chain to debug */
  send_command_to_vpi(CMD_JTAG_SET_IR);
 
  send_data_to_vpi(JI_DEBUG);
 
  get_response_from_vpi();
 
  current_chain = -1;
  return DBG_ERR_OK;
}
 
/* counts retries and returns zero if we should abort */
/* TODO: dinamically adjust timings for jp2 */
static int retry_no = 0;
int retry_do() {
  int i, err;
  printf("RETRY\n");
  //exit(2);
  if (retry_no >= NUM_SOFT_RETRIES) {
    if ((err = dbg_reset())) return err;
  }
  if (retry_no >= NUM_SOFT_RETRIES + NUM_HARD_RETRIES) {
    retry_no = 0;
    return 0;
  }
  retry_no++;
  return 1;
}
 
/* resets retry counter */
void retry_ok() {
  retry_no = 0;
}
 
/* Sets scan chain.  */
int dbg_set_chain(int chain) {
 
  debug("\n");
  debug2("dbg_set_chain %d\n", chain);
 
  if (current_chain == chain)
    return DBG_ERR_OK;
 
  dbg_chain = chain;
 
  send_command_to_vpi(CMD_SET_DEBUG_CHAIN);
 
  send_data_to_vpi(chain);
 
  get_response_from_vpi();
 
  current_chain = chain;
 
  return DBG_ERR_OK;
}
 
/* writes a ctrl reg */
int dbg_ctrl(int reset, int stall)
{
 
  debug("\n");
  debug2("ctrl\n");
 
  dbg_set_chain(dbg_chain);
 
  send_command_to_vpi(CMD_CPU_CTRL_WR);
 
  //send_data_to_vpi(((reset & 0x1) | ((stall&0x1)<<1)));
  send_data_to_vpi(((stall & 0x1) | ((reset&0x1)<<1)));
 
  get_response_from_vpi();
 
  return DBG_ERR_OK;
}
 
/* reads control register */
int dbg_ctrl_read(int *reset, int *stall)
{
 
  uint32_t resp;
 
  dbg_set_chain(dbg_chain);
 
  debug("\n");
  debug2("ctrl\n");
 
  dbg_set_chain(dbg_chain);
 
  send_command_to_vpi(CMD_CPU_CTRL_RD);
 
  get_data_from_vpi((uint32_t *)&resp);
 
  if (DBG_VPI) printf("rsp-rtl_sim: dbg_ctrl_read: 0x%.8x\n",resp);
 
  get_response_from_vpi();
 
  *reset = (int)(resp & 0x00000001);
 
  *stall = (int)((resp >> 1) & 0x00000001);
 
  return DBG_ERR_OK;
}
 
/* read a word from wishbone */
int dbg_wb_read32(uint32_t adr, uint32_t *data)
{
  //uint32_t resp;
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_RD32);
 
  send_address_to_vpi(adr);
 
  get_data_from_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
}
 
/* write a word to wishbone */
int dbg_wb_write32(uint32_t adr, uint32_t data)
{
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_WR32);
 
  send_address_to_vpi(adr);
 
  send_data_to_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
}
 
/* read a block from wishbone */
int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len)
{
 
  // len is in B Y T E S ! !
 
  if (DBG_VPI) printf("rsp-rtl_sim: block read len: %d from addr: 0x%.8x\n",len, adr);
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_BLOCK_RD32);
 
  send_data_to_vpi(adr);
 
  send_data_to_vpi(len);
 
  get_block_data_from_vpi(len, data);
 
  get_response_from_vpi();
 
  return DBG_ERR_OK;
}
 
/* write a block to wishbone */
int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len)
{
 
  dbg_set_chain(DC_WISHBONE);
 
  send_command_to_vpi(CMD_WB_BLOCK_WR32);
 
  send_data_to_vpi(adr);
 
  send_data_to_vpi(len);
 
  send_block_data_to_vpi(len, data);
 
  get_response_from_vpi();
 
  return DBG_ERR_OK;
}
 
/* read a register from cpu */
int dbg_cpu0_read(uint32_t adr, uint32_t *data)
{
 
  dbg_set_chain(DC_CPU0);
 
  send_command_to_vpi(CMD_CPU_RD_REG);
 
  send_address_to_vpi(adr);
 
  get_data_from_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
 
}
 
/* write a cpu register */
int dbg_cpu0_write(uint32_t adr, uint32_t data)
{
 
  uint32_t resp;
 
  dbg_set_chain(DC_CPU0);
 
  send_command_to_vpi(CMD_CPU_WR_REG);
 
  send_address_to_vpi(adr);
 
  send_data_to_vpi(data);
 
  get_response_from_vpi();
 
  return 0;
}
 
/* read a register from cpu */
int dbg_cpu1_read(uint32_t adr, uint32_t *data) {
  /*
  int err;
  if ((err = dbg_set_chain(DC_CPU1))) return err;
  if ((err = dbg_command(0x6, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
  *data = ntohl(*data);
  */
  return DBG_ERR_OK;
}
 
/* write a cpu register */
int dbg_cpu1_write(uint32_t adr, uint32_t data) {
  /*
  int err;
  data = ntohl(data);
  if ((err = dbg_set_chain(DC_CPU1))) return err;
  if ((err = dbg_command(0x2, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
  */
  return DBG_ERR_OK;
}
 
/* read a register from cpu module */
int dbg_cpu1_read_ctrl(uint32_t adr, unsigned char *data) {
  /*
    int err;
    int r, s;
    if ((err = dbg_set_chain(DC_CPU1))) return err;
    if ((err = dbg_ctrl_read(&r, &s))) return err;
    *data = (r << 1) | s;
    */
  return DBG_ERR_OK;
}
 
/* write a cpu module register */
int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data) {
  int err;
  if ((err = dbg_set_chain(DC_CPU0))) return err;
  if ((err = dbg_ctrl(data & 2, data &1))) return err;
  return DBG_ERR_OK;
}
 
/* read a register from cpu module */
int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data) {
  int err;
  int r, s;
  if ((err = dbg_set_chain(DC_CPU0))) return err;
  if ((err = dbg_ctrl_read(&r, &s))) return err;
  *data = (r << 1) | s;
  return DBG_ERR_OK;
}
 
void dbg_test() {
  int i;
  uint32_t npc, ppc, r1, insn, result;
  unsigned char stalled;
  //    uint32_t stalled;
  unsigned char read_byte;
 
  printf("  Stall or1k\n");
  dbg_cpu0_write_ctrl(0, 0x01);      // stall or1k
 
  dbg_cpu0_read_ctrl(0, &stalled);
  if (!(stalled & 0x1)) {
    printf("\tor1k stall failed. read: 0x%x\n", stalled);   // check stall or1k
    //exit(1);
  }
 
  debug2("  Reading npc\n");
  dbg_cpu0_read((0 << 11) + 16, &npc);
  debug2("  Reading ppc\n");
  dbg_cpu0_read((0 << 11) + 18, &ppc);
  debug2("  Reading r1\n");
  dbg_cpu0_read(0x401, &r1);
  printf("  Read      npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
 
}
 
// Catch the term/int signals, close gdb then close ourselves
void catch_sigint(int sig_num)
{
  gdb_close();
  exit(0);
}
 
void dbg_client_detached(void)
{
  // Send this message back to the sim
  send_command_to_vpi(CMD_GDB_DETACH);
}
 
 
// This function is called after the fork in the VPI function.
 
void run_rsp_server(int portNum)
{
  // Send commands to init and reset debug interface
  dbg_reset();
  // Stall and read NPC, PPC etc
  dbg_test();
 
  set_rsp_server_port(portNum);
 
  // Install SIGINT/SIGTERM handlers, to close down gracefully
  signal(SIGINT, catch_sigint);
  signal(SIGTERM, catch_sigint);
 
  if (DBG_ON) printf("rsp-rtl_sim: starting handle_rsp()\n");
  // Now, start the RSP server. This should not return
  handle_rsp ();
 
  // Exit gracefully if it returns (shouldn't though)
  exit(0);
 
}
 
 

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-rtl_sim.c] - Blame information for rev 40

Line No.	Rev	Author	Line
1	40	julius	`/$$HEADER/`
2			`/******************************************************************************/`
3			`/* */`
4			`/* H E A D E R I N F O R M A T I O N */`
5			`/* */`
6			`/******************************************************************************/`
7
8			`// Project Name : ORPSoCv2`
9			`// File Name : rsp-rtl_sim.c`
10			`// Prepared By : jb, jb@orsoc.se`
11			`// Project Start : 2009-05-01`
12
13			`/$$COPYRIGHT NOTICE/`
14			`/******************************************************************************/`
15			`/* */`
16			`/* C O P Y R I G H T N O T I C E */`
17			`/* */`
18			`/******************************************************************************/`
19			`/*`
20			`This library is free software; you can redistribute it and/or`
21			`modify it under the terms of the GNU Lesser General Public`
22			`License as published by the Free Software Foundation;`
23			`version 2.1 of the License, a copy of which is available from`
24			`http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.`
25
26			`This library is distributed in the hope that it will be useful,`
27			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
28			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
29			`Lesser General Public License for more details.`
30
31			`You should have received a copy of the GNU Lesser General Public`
32			`License along with this library; if not, write to the Free Software`
33			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
34			`*/`
35
36
37			`/* Establishes GDB proxy server and communicates via pipes`
38			`to some functions running under the VPI in an RTL sim */`
39
40			`#include <stdio.h>`
41			`#include <sys/stat.h>`
42			`#include <sys/types.h>`
43			`#include <assert.h>`
44
45			`#include <ctype.h>`
46			`#include <stdint.h>`
47			`#include <string.h>`
48			`#include <stdlib.h>`
49			`#include <unistd.h>`
50			`#include <stdarg.h>`
51			`#include <fcntl.h>`
52			`#include <errno.h>`
53			`#include <signal.h>`
54
55			`#include "gdb.h"`
56			`#include "rsp-rtl_sim.h"`
57			`#include "rsp-vpi.h"`
58
59			`static int err = 0;`
60
61			`/* Currently selected scan chain - just to prevent unnecessary`
62			`transfers. */`
63			`static int current_chain = -1;`
64
65			`/* The chain that should be currently selected. */`
66			`static int dbg_chain = -1;`
67
68			`/* Crc of current read or written data. */`
69			`static int crc_r, crc_w = 0;`
70
71			`/* Generates new crc, sending in new bit input_bit */`
72			`static uint32_t crc_calc(uint32_t crc, int input_bit) {`
73			`uint32_t d = (input_bit&1) ? 0xfffffff : 0x0000000;`
74			`uint32_t crc_32 = ((crc >> 31)&1) ? 0xfffffff : 0x0000000;`
75			`crc <<= 1;`
76			`return crc ^ (d ^ crc_32) & DBG_CRC_POLY;`
77			`}`
78
79			`/* VPI communication prototyopes */`
80			`static void get_response_from_vpi();`
81			`static void get_data_from_vpi();`
82			`static void get_block_data_from_vpi(int len, uint32_t *data);`
83			`static void send_data_to_vpi(uint32_t data);`
84			`static void send_block_data_to_vpi(int len, uint32_t *data);`
85			`static void send_address_to_vpi(uint32_t address);`
86			`static void send_command_to_vpi(char CMD);`
87
88			`void send_command_to_vpi(char CMD)`
89			`{`
90			`// first thing we do is send a command`
91			`// and wait for an ack`
92			`int n;`
93			`char cmd_resp;`
94
95
96			`//n = write(rsp_to_vpi_pipe[1],&CMD, 1); // send the command to the sim`
97			`n = write(command_pipe[1],&CMD, 1); // send the command to the sim`
98
99			`if (n < 0) error("ERROR writing to VPI FIFO");`
100
101			`n = read(vpi_to_rsp_pipe[0],&cmd_resp,1); // block and wait for the ack`
102
103			`if (cmd_resp != CMD) error("Response from RTL sim incorrect"); //check it acked with cmd`
104
105			`return;`
106			`}`
107
108			`void send_address_to_vpi(uint32_t address)`
109			`{`
110			`// Now send address`
111			`int n;`
112
113			`char* send_buf;`
114
115			`send_buf = (char *) &address;`
116
117			`n = write(rsp_to_vpi_pipe[1],send_buf, 4); // send the address to the sim`
118
119			`if (n < 0) error("ERROR writing to VPI socket");`
120
121			`return;`
122			`}`
123
124			`void send_data_to_vpi(uint32_t data)`
125			`{`
126			`// Now send data`
127			`int n;`
128
129			`char* send_buf;`
130
131			`send_buf = (char *) &data;`
132
133			`n = write(rsp_to_vpi_pipe[1],send_buf, 4); // Write the data to the socket`
134
135			`if (n < 0) error("ERROR writing to VPI socket");`
136
137			`return;`
138
139			`}`
140
141			`void send_block_data_to_vpi(int len, uint32_t *data)`
142			`{`
143			`// Now send data`
144			`int n, i;`
145
146			`char* send_buf;`
147
148			`send_buf = (char *) data;`
149
150			`n = write(rsp_to_vpi_pipe[1],send_buf, len); // Write the data to the fifo`
151
152			`if (n < 0) error("ERROR writing to VPI socket");`
153
154			`return;`
155
156			`}`
157
158			`void get_data_from_vpi(uint32_t* data)`
159			`{`
160
161			`int n;`
162
163			`uint32_t inc_data;`
164
165			`char* recv_buf;`
166
167			`recv_buf = (char*) &inc_data;`
168
169			`n = read(vpi_to_rsp_pipe[0],recv_buf,4); // block and wait for the data`
170
171			`if (DBG_VPI) printf("rsp-rtl_sim: get_data_from_vpi: 0x%.8x\n",inc_data);`
172
173			`*data = inc_data;`
174
175			`return;`
176
177			`}`
178
179			`void get_block_data_from_vpi(int len, uint32_t* data)`
180			`{`
181			`int n, i, status;`
182
183			`uint32_t inc_data;`
184
185			`char* recv_buf;`
186
187			`uint32_t* data_ptr;`
188
189			`recv_buf = (char *) data;`
190
191			`n=0;`
192
193			`while (n < len)`
194			`{`
195
196			`status = read(vpi_to_rsp_pipe[0], recv_buf, len - n); // block and wait for the data`
197
198			`if (status > 0) n += status; // we read "status" number of bytes`
199
200			`}`
201
202
203			`if (DBG_VPI){`
204			`printf("rsp-rtl_sim: get_block_data_from_vpi: %d bytes",len);`
205			`for (i = 0;i < (len/4); i++)`
206			`{`
207			`printf("0x%.8x ",data[i]);`
208			`}`
209			`printf("\n");`
210			`}`
211
212			`return;`
213
214			`}`
215
216			`void get_response_from_vpi()`
217			`{`
218			`// Basically just wait for the response from VPI`
219			`// by blocking wait on recv`
220
221			`int n = 0;`
222			`char tmp;`
223
224			`n = read(vpi_to_rsp_pipe[0],&tmp,1); // block and wait`
225
226			`return;`
227			`}`
228
229			`/* Resets JTAG`
230			`Writes TRST=0`
231			`and TRST=1 */`
232			`static void jp2_reset_JTAG() {`
233			`int i;`
234
235			`debug2("\nreset(");`
236
237			`send_command_to_vpi(CMD_RESET);`
238
239			`get_response_from_vpi();`
240
241			`debug2(")\n");`
242
243			`}`
244
245			`/* Resets JTAG, and sets DEBUG scan chain */`
246			`int dbg_reset() {`
247
248			`int err;`
249			`uint32_t id;`
250
251			`jp2_reset_JTAG();`
252
253			`/* set idcode jtag chain */`
254			`send_command_to_vpi(CMD_JTAG_SET_IR);`
255
256			`send_data_to_vpi(JI_IDCODE);`
257
258			`get_response_from_vpi();`
259
260			`/* now read out the jtag id */`
261			`send_command_to_vpi(CMD_READ_JTAG_ID);`
262
263			`//id = get_data_from_vpi();`
264			`get_data_from_vpi((uint32_t *)&id);`
265
266			`get_response_from_vpi();`
267
268			`printf("JTAG ID = %08x\n", id);`
269
270			`/* now set the chain to debug */`
271			`send_command_to_vpi(CMD_JTAG_SET_IR);`
272
273			`send_data_to_vpi(JI_DEBUG);`
274
275			`get_response_from_vpi();`
276
277			`current_chain = -1;`
278			`return DBG_ERR_OK;`
279			`}`
280
281			`/* counts retries and returns zero if we should abort */`
282			`/* TODO: dinamically adjust timings for jp2 */`
283			`static int retry_no = 0;`
284			`int retry_do() {`
285			`int i, err;`
286			`printf("RETRY\n");`
287			`//exit(2);`
288			`if (retry_no >= NUM_SOFT_RETRIES) {`
289			`if ((err = dbg_reset())) return err;`
290			`}`
291			`if (retry_no >= NUM_SOFT_RETRIES + NUM_HARD_RETRIES) {`
292			`retry_no = 0;`
293			`return 0;`
294			`}`
295			`retry_no++;`
296			`return 1;`
297			`}`
298
299			`/* resets retry counter */`
300			`void retry_ok() {`
301			`retry_no = 0;`
302			`}`
303
304			`/* Sets scan chain. */`
305			`int dbg_set_chain(int chain) {`
306
307			`debug("\n");`
308			`debug2("dbg_set_chain %d\n", chain);`
309
310			`if (current_chain == chain)`
311			`return DBG_ERR_OK;`
312
313			`dbg_chain = chain;`
314
315			`send_command_to_vpi(CMD_SET_DEBUG_CHAIN);`
316
317			`send_data_to_vpi(chain);`
318
319			`get_response_from_vpi();`
320
321			`current_chain = chain;`
322
323			`return DBG_ERR_OK;`
324			`}`
325
326			`/* writes a ctrl reg */`
327			`int dbg_ctrl(int reset, int stall)`
328			`{`
329
330			`debug("\n");`
331			`debug2("ctrl\n");`
332
333			`dbg_set_chain(dbg_chain);`
334
335			`send_command_to_vpi(CMD_CPU_CTRL_WR);`
336
337			`//send_data_to_vpi(((reset & 0x1) \| ((stall&0x1)<<1)));`
338			`send_data_to_vpi(((stall & 0x1) \| ((reset&0x1)<<1)));`
339
340			`get_response_from_vpi();`
341
342			`return DBG_ERR_OK;`
343			`}`
344
345			`/* reads control register */`
346			`int dbg_ctrl_read(int reset, int stall)`
347			`{`
348
349			`uint32_t resp;`
350
351			`dbg_set_chain(dbg_chain);`
352
353			`debug("\n");`
354			`debug2("ctrl\n");`
355
356			`dbg_set_chain(dbg_chain);`
357
358			`send_command_to_vpi(CMD_CPU_CTRL_RD);`
359
360			`get_data_from_vpi((uint32_t *)&resp);`
361
362			`if (DBG_VPI) printf("rsp-rtl_sim: dbg_ctrl_read: 0x%.8x\n",resp);`
363
364			`get_response_from_vpi();`
365
366			`*reset = (int)(resp & 0x00000001);`
367
368			`*stall = (int)((resp >> 1) & 0x00000001);`
369
370			`return DBG_ERR_OK;`
371			`}`
372
373			`/* read a word from wishbone */`
374			`int dbg_wb_read32(uint32_t adr, uint32_t *data)`
375			`{`
376			`//uint32_t resp;`
377
378			`dbg_set_chain(DC_WISHBONE);`
379
380			`send_command_to_vpi(CMD_WB_RD32);`
381
382			`send_address_to_vpi(adr);`
383
384			`get_data_from_vpi(data);`
385
386			`get_response_from_vpi();`
387
388			`return 0;`
389			`}`
390
391			`/* write a word to wishbone */`
392			`int dbg_wb_write32(uint32_t adr, uint32_t data)`
393			`{`
394
395			`dbg_set_chain(DC_WISHBONE);`
396
397			`send_command_to_vpi(CMD_WB_WR32);`
398
399			`send_address_to_vpi(adr);`
400
401			`send_data_to_vpi(data);`
402
403			`get_response_from_vpi();`
404
405			`return 0;`
406			`}`
407
408			`/* read a block from wishbone */`
409			`int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len)`
410			`{`
411
412			`// len is in B Y T E S ! !`
413
414			`if (DBG_VPI) printf("rsp-rtl_sim: block read len: %d from addr: 0x%.8x\n",len, adr);`
415
416			`dbg_set_chain(DC_WISHBONE);`
417
418			`send_command_to_vpi(CMD_WB_BLOCK_RD32);`
419
420			`send_data_to_vpi(adr);`
421
422			`send_data_to_vpi(len);`
423
424			`get_block_data_from_vpi(len, data);`
425
426			`get_response_from_vpi();`
427
428			`return DBG_ERR_OK;`
429			`}`
430
431			`/* write a block to wishbone */`
432			`int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len)`
433			`{`
434
435			`dbg_set_chain(DC_WISHBONE);`
436
437			`send_command_to_vpi(CMD_WB_BLOCK_WR32);`
438
439			`send_data_to_vpi(adr);`
440
441			`send_data_to_vpi(len);`
442
443			`send_block_data_to_vpi(len, data);`
444
445			`get_response_from_vpi();`
446
447			`return DBG_ERR_OK;`
448			`}`
449
450			`/* read a register from cpu */`
451			`int dbg_cpu0_read(uint32_t adr, uint32_t *data)`
452			`{`
453
454			`dbg_set_chain(DC_CPU0);`
455
456			`send_command_to_vpi(CMD_CPU_RD_REG);`
457
458			`send_address_to_vpi(adr);`
459
460			`get_data_from_vpi(data);`
461
462			`get_response_from_vpi();`
463
464			`return 0;`
465
466			`}`
467
468			`/* write a cpu register */`
469			`int dbg_cpu0_write(uint32_t adr, uint32_t data)`
470			`{`
471
472			`uint32_t resp;`
473
474			`dbg_set_chain(DC_CPU0);`
475
476			`send_command_to_vpi(CMD_CPU_WR_REG);`
477
478			`send_address_to_vpi(adr);`
479
480			`send_data_to_vpi(data);`
481
482			`get_response_from_vpi();`
483
484			`return 0;`
485			`}`
486
487			`/* read a register from cpu */`
488			`int dbg_cpu1_read(uint32_t adr, uint32_t *data) {`
489			`/*`
490			`int err;`
491			`if ((err = dbg_set_chain(DC_CPU1))) return err;`
492			`if ((err = dbg_command(0x6, adr, 4))) return err;`
493			`if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;`
494			`data = ntohl(data);`
495			`*/`
496			`return DBG_ERR_OK;`
497			`}`
498
499			`/* write a cpu register */`
500			`int dbg_cpu1_write(uint32_t adr, uint32_t data) {`
501			`/*`
502			`int err;`
503			`data = ntohl(data);`
504			`if ((err = dbg_set_chain(DC_CPU1))) return err;`
505			`if ((err = dbg_command(0x2, adr, 4))) return err;`
506			`if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;`
507			`*/`
508			`return DBG_ERR_OK;`
509			`}`
510
511			`/* read a register from cpu module */`
512			`int dbg_cpu1_read_ctrl(uint32_t adr, unsigned char *data) {`
513			`/*`
514			`int err;`
515			`int r, s;`
516			`if ((err = dbg_set_chain(DC_CPU1))) return err;`
517			`if ((err = dbg_ctrl_read(&r, &s))) return err;`
518			`*data = (r << 1) \| s;`
519			`*/`
520			`return DBG_ERR_OK;`
521			`}`
522
523			`/* write a cpu module register */`
524			`int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data) {`
525			`int err;`
526			`if ((err = dbg_set_chain(DC_CPU0))) return err;`
527			`if ((err = dbg_ctrl(data & 2, data &1))) return err;`
528			`return DBG_ERR_OK;`
529			`}`
530
531			`/* read a register from cpu module */`
532			`int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data) {`
533			`int err;`
534			`int r, s;`
535			`if ((err = dbg_set_chain(DC_CPU0))) return err;`
536			`if ((err = dbg_ctrl_read(&r, &s))) return err;`
537			`*data = (r << 1) \| s;`
538			`return DBG_ERR_OK;`
539			`}`
540
541			`void dbg_test() {`
542			`int i;`
543			`uint32_t npc, ppc, r1, insn, result;`
544			`unsigned char stalled;`
545			`// uint32_t stalled;`
546			`unsigned char read_byte;`
547
548			`printf(" Stall or1k\n");`
549			`dbg_cpu0_write_ctrl(0, 0x01); // stall or1k`
550
551			`dbg_cpu0_read_ctrl(0, &stalled);`
552			`if (!(stalled & 0x1)) {`
553			`printf("\tor1k stall failed. read: 0x%x\n", stalled); // check stall or1k`
554			`//exit(1);`
555			`}`
556
557			`debug2(" Reading npc\n");`
558			`dbg_cpu0_read((0 << 11) + 16, &npc);`
559			`debug2(" Reading ppc\n");`
560			`dbg_cpu0_read((0 << 11) + 18, &ppc);`
561			`debug2(" Reading r1\n");`
562			`dbg_cpu0_read(0x401, &r1);`
563			`printf(" Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);`
564
565			`}`
566
567			`// Catch the term/int signals, close gdb then close ourselves`
568			`void catch_sigint(int sig_num)`
569			`{`
570			`gdb_close();`
571			`exit(0);`
572			`}`
573
574			`void dbg_client_detached(void)`
575			`{`
576			`// Send this message back to the sim`
577			`send_command_to_vpi(CMD_GDB_DETACH);`
578			`}`
579
580
581			`// This function is called after the fork in the VPI function.`
582
583			`void run_rsp_server(int portNum)`
584			`{`
585			`// Send commands to init and reset debug interface`
586			`dbg_reset();`
587			`// Stall and read NPC, PPC etc`
588			`dbg_test();`
589
590			`set_rsp_server_port(portNum);`
591
592			`// Install SIGINT/SIGTERM handlers, to close down gracefully`
593			`signal(SIGINT, catch_sigint);`
594			`signal(SIGTERM, catch_sigint);`
595
596			`if (DBG_ON) printf("rsp-rtl_sim: starting handle_rsp()\n");`
597			`// Now, start the RSP server. This should not return`
598			`handle_rsp ();`
599
600			`// Exit gracefully if it returns (shouldn't though)`
601			`exit(0);`
602
603			`}`
604
605