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julius |
/*$$HEADER*/
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/******************************************************************************/
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/* */
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/* H E A D E R I N F O R M A T I O N */
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/* */
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/******************************************************************************/
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// Project Name : ORPSoCv2
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// File Name : rsp-rtl_sim.h
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// Prepared By : jb, jb@orsoc.se
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// Project Start : 2009-05-01
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/*$$COPYRIGHT NOTICE*/
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/******************************************************************************/
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/* */
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/* C O P Y R I G H T N O T I C E */
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/* */
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/******************************************************************************/
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/*
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation;
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version 2.1 of the License, a copy of which is available from
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http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _RSP_RTL_SIM_H_
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#define _RSP_RTL_SIM_H_
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#include <stdint.h> // For uint32_t types
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//#define DEBUG 1
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//#define DEBUG2 1
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#define Boolean int
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#define false 0
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#define true 1
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#ifdef DEBUG
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#define debug printf
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#else
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#define debug
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#endif
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#ifdef DEBUG2
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#define debug2 printf
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#else
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#define debug2
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#endif
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#define DBG_ON 0
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#define DBG_VPI 0
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extern int vpi_to_rsp_pipe[2]; // [0] - read, [1] - write
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extern int rsp_to_vpi_pipe[2]; // [0] - read, [1] - write
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extern int command_pipe[2]; // RSP end writes, VPI end reads ONLY
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#if (DEBUG) || (DEBUG2)
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#define flush_debug() fflush(stdout)
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#else
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#define flush_debug()
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#endif
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# define JTAG_WAIT() usleep(1000)
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# define JTAG_RETRY_WAIT() usleep (1000)
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/* Selects crc trailer size in bits. Currently supported: 8 */
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#define CRC_SIZE (8)
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/* Scan chain size in bits. */
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#define SC_SIZE (4)
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/* function to kick off this server */
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void run_rsp_server(int);
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/* read a word from wishbone */
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int dbg_wb_read32(uint32_t adr, uint32_t *data);
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/* write a word to wishbone */
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int dbg_wb_write32(uint32_t adr, uint32_t data);
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/* read a block from wishbone */
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int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len);
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/* write a block to wishbone */
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int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len);
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/* read a register from cpu */
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int dbg_cpu0_read(uint32_t adr, uint32_t *data);
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/* read a register from cpu module */
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int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data);
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/* write a cpu register */
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int dbg_cpu0_write(uint32_t adr, uint32_t data);
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/* write a cpu module register */
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int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data);
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/* send a message to the sim that the debugging client has disconnected */
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void dbg_client_detached(void);
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#define DC_SIZE 4
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#define DC_STATUS_SIZE 4
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#define DC_WISHBONE 0
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#define DC_CPU0 1
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#define DC_CPU1 2
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#define DI_GO 0
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#define DI_READ_CMD 1
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#define DI_WRITE_CMD 2
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#define DI_READ_CTRL 3
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#define DI_WRITE_CTRL 4
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#define DBG_CRC_SIZE 32
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#define DBG_CRC_POLY 0x04c11db7
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#define DBG_ERR_OK 0
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#define DBG_ERR_CRC 8
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#define NUM_SOFT_RETRIES 3
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#define NUM_HARD_RETRIES 3
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#define NUM_ACCESS_RETRIES 10
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/* Possible errors are listed here. */
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enum enum_errors /* modified <chris@asics.ws> CZ 24/05/01 */
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{
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/* Codes > 0 are for system errors */
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ERR_NONE = 0,
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ERR_CRC = -1,
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ERR_MEM = -2,
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JTAG_PROXY_INVALID_COMMAND = -3,
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JTAG_PROXY_SERVER_TERMINATED = -4,
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JTAG_PROXY_NO_CONNECTION = -5,
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JTAG_PROXY_PROTOCOL_ERROR = -6,
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JTAG_PROXY_COMMAND_NOT_IMPLEMENTED = -7,
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JTAG_PROXY_INVALID_CHAIN = -8,
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JTAG_PROXY_INVALID_ADDRESS = -9,
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JTAG_PROXY_ACCESS_EXCEPTION = -10, /* Write to ROM */
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JTAG_PROXY_INVALID_LENGTH = -11,
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JTAG_PROXY_OUT_OF_MEMORY = -12,
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};
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#endif
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