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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [verilog/] [vpi_debug_defines.v] - Blame information for rev 40

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ORPSoC Testbench                                            ////
////                                                              ////
////  Description                                                 ////
////  ORPSoC VPI Debugging Testbench defines file                 ////
////                                                              ////
////  To Do:                                                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////      - jb, jb@orsoc.se                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps
// Defines from the following files:
// tap_defines.v
 
// Define IDCODE Value
`define IDCODE_VALUE  32'h14951185
 
// Length of the Instruction register
`define IR_LENGTH       4
 
// Supported Instructions
`define EXTEST          4'b0000
`define SAMPLE_PRELOAD  4'b0001
`define IDCODE          4'b0010
`define DEBUG           4'b1000
`define MBIST           4'b1001
`define BYPASS          4'b1111
 
// Number of cells in boundary scan chain
`define BS_CELL_NB      32'd558
 
//dbg_defines.v
 
// Length of the MODULE ID register
`define DBG_TOP_MODULE_ID_LENGTH        4
 
// Length of data
`define DBG_TOP_MODULE_DATA_LEN  `DBG_TOP_MODULE_ID_LENGTH + 1
`define DBG_TOP_DATA_CNT          3
 
// Length of status
`define DBG_TOP_STATUS_LEN        3'd4
`define DBG_TOP_STATUS_CNT_WIDTH  3
 
// Length of the CRC
`define DBG_TOP_CRC_LEN           32
`define DBG_TOP_CRC_CNT           6
 
// Chains
`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0
`define DBG_TOP_CPU0_DEBUG_MODULE     4'h1
`define DBG_TOP_CPU1_DEBUG_MODULE     4'h2
 
// dbg_wb_defines.v
 
// If WISHBONE sub-module is supported uncomment the folowing line
`define DBG_WISHBONE_SUPPORTED
 
// If CPU_0 sub-module is supported uncomment the folowing line
`define DBG_CPU0_SUPPORTED
 
// If CPU_1 sub-module is supported uncomment the folowing line
//`define DBG_CPU1_SUPPORTED
 
// If more debug info is needed, uncomment the follofing line
//`define DBG_MORE_INFO
 
 
// Defining length of the command
`define DBG_WB_CMD_LEN          3'd4
`define DBG_WB_CMD_CNT_WIDTH    3
 
// Defining length of the access_type field
`define DBG_WB_ACC_TYPE_LEN     3'd4
 
// Defining length of the address
`define DBG_WB_ADR_LEN          6'd32
 
// Defining length of the length register
`define DBG_WB_LEN_LEN          5'd16
 
// Defining total length of the DR needed
`define DBG_WB_DR_LEN           (`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN)
 
// Defining length of the CRC
`define DBG_WB_CRC_LEN          6'd32
`define DBG_WB_CRC_CNT_WIDTH    6
 
// Defining length of status
`define DBG_WB_STATUS_LEN       3'd4
`define DBG_WB_STATUS_CNT_WIDTH 3
 
// Defining length of the data
`define DBG_WB_DATA_CNT_WIDTH     (`DBG_WB_LEN_LEN + 3)
`define DBG_WB_DATA_CNT_LIM_WIDTH `DBG_WB_LEN_LEN
 
//Defining commands
`define DBG_WB_GO               4'h0
`define DBG_WB_RD_COMM          4'h1
`define DBG_WB_WR_COMM          4'h2
 
// Defining access types for wishbone
`define DBG_WB_WRITE8           4'h0
`define DBG_WB_WRITE16          4'h1
`define DBG_WB_WRITE32          4'h2
`define DBG_WB_READ8            4'h4
`define DBG_WB_READ16           4'h5
`define DBG_WB_READ32           4'h6
 
// dbg_cpu_defines.v
 
 
// Defining length of the command
`define DBG_CPU_CMD_LEN          3'd4
`define DBG_CPU_CMD_CNT_WIDTH    3
 
// Defining length of the access_type field
`define DBG_CPU_ACC_TYPE_LEN     3'd4
 
// Defining length of the address
`define DBG_CPU_ADR_LEN          6'd32
 
// Defining length of the length register
`define DBG_CPU_LEN_LEN          5'd16
 
// Defining total length of the DR needed
//define DBG_CPU_DR_LEN           (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
`define DBG_CPU_DR_LEN           52
// Defining length of the CRC
`define DBG_CPU_CRC_LEN          6'd32
`define DBG_CPU_CRC_CNT_WIDTH    6
 
// Defining length of status
`define DBG_CPU_STATUS_LEN       3'd4
`define DBG_CPU_STATUS_CNT_WIDTH 3
 
// Defining length of the data
//define DBG_CPU_DATA_CNT_WIDTH      `DBG_CPU_LEN_LEN + 3
`define DBG_CPU_DATA_CNT_WIDTH    19
//define DBG_CPU_DATA_CNT_LIM_WIDTH   `DBG_CPU_LEN_LEN
`define DBG_CPU_DATA_CNT_LIM_WIDTH 16
// Defining length of the control register
`define DBG_CPU_CTRL_LEN         2
 
//Defining commands
`define DBG_CPU_GO               4'h0
`define DBG_CPU_RD_COMM          4'h1
`define DBG_CPU_WR_COMM          4'h2
`define DBG_CPU_RD_CTRL          4'h3
`define DBG_CPU_WR_CTRL          4'h4
 
// Defining access types for wishbone
`define DBG_CPU_WRITE            4'h2
`define DBG_CPU_READ             4'h6
 
 
// commands from jp_vpi
`define CMD_JTAG_SET_IR          4'h1
`define CMD_SET_DEBUG_CHAIN      4'h2
`define CMD_CPU_CTRL_WR          4'h3
`define CMD_CPU_CTRL_RD          4'h4
`define CMD_CPU_WR_REG           4'h5
`define CMD_CPU_RD_REG           4'h6
`define CMD_WB_WR32              4'h7
`define CMD_WB_RD32              4'h8
`define CMD_WB_BLOCK_WR32        4'h9
`define CMD_WB_BLOCK_RD32        4'ha
`define CMD_RESET                4'hb
`define CMD_READ_JTAG_ID         4'hc
`define CMD_GDB_DETACH           4'hd
 
// commands:
// 4'h1 jtag set instruction register (input: instruction value)
// 4'h2 set debug chain (dbg_set_command here) (input: chain value)
// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))
// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))
// 4'h5 cpu wr reg (inputs: address, data)
// 4'h6 cpu rd reg (input: address; output: data)
// 4'h7 wb wr 32 (inputs: address, data)
// 4'h8 wb rd 32 (input: address; output: data)
// 4'h9 wb wr block 32 (inputs: address, length, data)
// 4'ha wb rd block 32 (inputs: address, length; output: data)
// 4'hb reset
// 4'hc read jtag id (output: data)
 
`define SDRAM_BASE_ADDRESS 32'h00000000

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [verilog/] [vpi_debug_defines.v] - Blame information for rev 40

Line No.	Rev	Author	Line
1	40	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ORPSoC Testbench ////`
4			`//// ////`
5			`//// Description ////`
6			`//// ORPSoC VPI Debugging Testbench defines file ////`
7			`//// ////`
8			`//// To Do: ////`
9			`//// ////`
10			`//// ////`
11			`//// Author(s): ////`
12			`//// - jb, jb@orsoc.se ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`timescale 1ns/10ps
42			`// Defines from the following files:`
43			`// tap_defines.v`
44
45			`// Define IDCODE Value`
46			`define IDCODE_VALUE 32'h14951185
47
48			`// Length of the Instruction register`
49			`define IR_LENGTH 4
50
51			`// Supported Instructions`
52			`define EXTEST 4'b0000
53			`define SAMPLE_PRELOAD 4'b0001
54			`define IDCODE 4'b0010
55			`define DEBUG 4'b1000
56			`define MBIST 4'b1001
57			`define BYPASS 4'b1111
58
59			`// Number of cells in boundary scan chain`
60			`define BS_CELL_NB 32'd558
61
62			`//dbg_defines.v`
63
64			`// Length of the MODULE ID register`
65			`define DBG_TOP_MODULE_ID_LENGTH 4
66
67			`// Length of data`
68			`define DBG_TOP_MODULE_DATA_LEN `DBG_TOP_MODULE_ID_LENGTH + 1
69			`define DBG_TOP_DATA_CNT 3
70
71			`// Length of status`
72			`define DBG_TOP_STATUS_LEN 3'd4
73			`define DBG_TOP_STATUS_CNT_WIDTH 3
74
75			`// Length of the CRC`
76			`define DBG_TOP_CRC_LEN 32
77			`define DBG_TOP_CRC_CNT 6
78
79			`// Chains`
80			`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0
81			`define DBG_TOP_CPU0_DEBUG_MODULE 4'h1
82			`define DBG_TOP_CPU1_DEBUG_MODULE 4'h2
83
84			`// dbg_wb_defines.v`
85
86			`// If WISHBONE sub-module is supported uncomment the folowing line`
87			`define DBG_WISHBONE_SUPPORTED
88
89			`// If CPU_0 sub-module is supported uncomment the folowing line`
90			`define DBG_CPU0_SUPPORTED
91
92			`// If CPU_1 sub-module is supported uncomment the folowing line`
93			//`define DBG_CPU1_SUPPORTED
94
95			`// If more debug info is needed, uncomment the follofing line`
96			//`define DBG_MORE_INFO
97
98
99			`// Defining length of the command`
100			`define DBG_WB_CMD_LEN 3'd4
101			`define DBG_WB_CMD_CNT_WIDTH 3
102
103			`// Defining length of the access_type field`
104			`define DBG_WB_ACC_TYPE_LEN 3'd4
105
106			`// Defining length of the address`
107			`define DBG_WB_ADR_LEN 6'd32
108
109			`// Defining length of the length register`
110			`define DBG_WB_LEN_LEN 5'd16
111
112			`// Defining total length of the DR needed`
113			`define DBG_WB_DR_LEN (`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN)
114
115			`// Defining length of the CRC`
116			`define DBG_WB_CRC_LEN 6'd32
117			`define DBG_WB_CRC_CNT_WIDTH 6
118
119			`// Defining length of status`
120			`define DBG_WB_STATUS_LEN 3'd4
121			`define DBG_WB_STATUS_CNT_WIDTH 3
122
123			`// Defining length of the data`
124			`define DBG_WB_DATA_CNT_WIDTH (`DBG_WB_LEN_LEN + 3)
125			`define DBG_WB_DATA_CNT_LIM_WIDTH `DBG_WB_LEN_LEN
126
127			`//Defining commands`
128			`define DBG_WB_GO 4'h0
129			`define DBG_WB_RD_COMM 4'h1
130			`define DBG_WB_WR_COMM 4'h2
131
132			`// Defining access types for wishbone`
133			`define DBG_WB_WRITE8 4'h0
134			`define DBG_WB_WRITE16 4'h1
135			`define DBG_WB_WRITE32 4'h2
136			`define DBG_WB_READ8 4'h4
137			`define DBG_WB_READ16 4'h5
138			`define DBG_WB_READ32 4'h6
139
140			`// dbg_cpu_defines.v`
141
142
143			`// Defining length of the command`
144			`define DBG_CPU_CMD_LEN 3'd4
145			`define DBG_CPU_CMD_CNT_WIDTH 3
146
147			`// Defining length of the access_type field`
148			`define DBG_CPU_ACC_TYPE_LEN 3'd4
149
150			`// Defining length of the address`
151			`define DBG_CPU_ADR_LEN 6'd32
152
153			`// Defining length of the length register`
154			`define DBG_CPU_LEN_LEN 5'd16
155
156			`// Defining total length of the DR needed`
157			//define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
158			`define DBG_CPU_DR_LEN 52
159			`// Defining length of the CRC`
160			`define DBG_CPU_CRC_LEN 6'd32
161			`define DBG_CPU_CRC_CNT_WIDTH 6
162
163			`// Defining length of status`
164			`define DBG_CPU_STATUS_LEN 3'd4
165			`define DBG_CPU_STATUS_CNT_WIDTH 3
166
167			`// Defining length of the data`
168			//define DBG_CPU_DATA_CNT_WIDTH `DBG_CPU_LEN_LEN + 3
169			`define DBG_CPU_DATA_CNT_WIDTH 19
170			//define DBG_CPU_DATA_CNT_LIM_WIDTH `DBG_CPU_LEN_LEN
171			`define DBG_CPU_DATA_CNT_LIM_WIDTH 16
172			`// Defining length of the control register`
173			`define DBG_CPU_CTRL_LEN 2
174
175			`//Defining commands`
176			`define DBG_CPU_GO 4'h0
177			`define DBG_CPU_RD_COMM 4'h1
178			`define DBG_CPU_WR_COMM 4'h2
179			`define DBG_CPU_RD_CTRL 4'h3
180			`define DBG_CPU_WR_CTRL 4'h4
181
182			`// Defining access types for wishbone`
183			`define DBG_CPU_WRITE 4'h2
184			`define DBG_CPU_READ 4'h6
185
186
187			`// commands from jp_vpi`
188			`define CMD_JTAG_SET_IR 4'h1
189			`define CMD_SET_DEBUG_CHAIN 4'h2
190			`define CMD_CPU_CTRL_WR 4'h3
191			`define CMD_CPU_CTRL_RD 4'h4
192			`define CMD_CPU_WR_REG 4'h5
193			`define CMD_CPU_RD_REG 4'h6
194			`define CMD_WB_WR32 4'h7
195			`define CMD_WB_RD32 4'h8
196			`define CMD_WB_BLOCK_WR32 4'h9
197			`define CMD_WB_BLOCK_RD32 4'ha
198			`define CMD_RESET 4'hb
199			`define CMD_READ_JTAG_ID 4'hc
200			`define CMD_GDB_DETACH 4'hd
201
202			`// commands:`
203			`// 4'h1 jtag set instruction register (input: instruction value)`
204			`// 4'h2 set debug chain (dbg_set_command here) (input: chain value)`
205			`// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))`
206			`// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))`
207			`// 4'h5 cpu wr reg (inputs: address, data)`
208			`// 4'h6 cpu rd reg (input: address; output: data)`
209			`// 4'h7 wb wr 32 (inputs: address, data)`
210			`// 4'h8 wb rd 32 (input: address; output: data)`
211			`// 4'h9 wb wr block 32 (inputs: address, length, data)`
212			`// 4'ha wb rd block 32 (inputs: address, length; output: data)`
213			`// 4'hb reset`
214			`// 4'hc read jtag id (output: data)`
215
216			`define SDRAM_BASE_ADDRESS 32'h00000000