OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [wiredelay.v] - Blame information for rev 408

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius 
 
2 
`timescale 1ns / 1ps
3 
 
4 
module wiredelay # (
5 
  parameter Delay_g = 0,
6 
  parameter Delay_rd = 0
7 
)
8 
(
9 
  inout A,
10 
  inout B,
11 
  input reset
12 
);
13 
 
14 
  reg A_r;
15 
  reg B_r;
16 
  reg line_en;
17 
 
18 
  assign A = A_r;
19 
  assign B = B_r;
20 
 
21 
  always @(*) begin
22 
    if (!reset) begin
23 
      A_r <= 1'bz;
24 
      B_r <= 1'bz;
25 
      line_en <= 1'b0;
26 
    end else begin
27 
      if (line_en) begin
28 
        A_r <= #Delay_rd B;
29 
        B_r <= 1'bz;
30 
      end else begin
31 
        B_r <= #Delay_g A;
32 
        A_r <= 1'bz;
33 
      end
34 
    end
35 
  end
36 
 
37 
  always @(A or B) begin
38 
    if (!reset) begin
39 
      line_en <= 1'b0;
40 
    end else if (A !== A_r) begin
41 
      line_en <= 1'b0;
42 
    end else if (B_r !== B) begin
43 
      line_en <= 1'b1;
44 
    end else begin
45 
      line_en <= line_en;
46 
    end
47 
  end
48 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.