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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [wiredelay.v] - Blame information for rev 862

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Line No. Rev Author Line
1 408 julius 
 
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`timescale 1ns / 1ps
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module wiredelay # (
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  parameter Delay_g = 0,
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  parameter Delay_rd = 0
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)
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(
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  inout A,
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  inout B,
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  input reset
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);
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  reg A_r;
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  reg B_r;
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  reg line_en;
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  assign A = A_r;
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  assign B = B_r;
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  always @(*) begin
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    if (!reset) begin
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      A_r <= 1'bz;
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      B_r <= 1'bz;
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      line_en <= 1'b0;
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    end else begin
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      if (line_en) begin
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        A_r <= #Delay_rd B;
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        B_r <= 1'bz;
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      end else begin
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        B_r <= #Delay_g A;
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        A_r <= 1'bz;
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      end
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    end
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  end
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  always @(A or B) begin
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    if (!reset) begin
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      line_en <= 1'b0;
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    end else if (A !== A_r) begin
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      line_en <= 1'b0;
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    end else if (B_r !== B) begin
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      line_en <= 1'b1;
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    end else begin
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      line_en <= line_en;
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    end
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  end
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endmodule

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