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Actel place and route environment

Backend flow post-synthesis through to programming file can be performed here.

The scripts are designed to run the Actel backend tools in batch/shell mode.

All make commands should be run in the run/ path.

Performing place and route:

If the settings in bin/Makefile are what is desired, then a simple

$ make all

will perform all steps from synthesis through to layout. The result will be the

.adb file located in the run/ path.

To alter the configuration (partially seen by running 'make print-config')

inspect bin/Makefile to see the various options. To see the script generated

which is passed to the Actel Designer, run

$ make create-compile-par.tcl

while also setting all variables as desired on the command line, and inspect

the resulting TCL file to ensure it is correct.

When running 'make all', the constraint SDC and PDC files will be automatically

generated by the script, and will be left in the run/ path.

Both PDC and SDC are dependent upon the defines in the RTL Verilog file

design_defines.v - to see what modules and options are set in design_defines.v

run:

$ make print-defines

Among the printed information will be which modules where enabled, and the PDC

and SDCs are generated based on this.

See the main Makefile, bin/Makefile, and the rule for $(SDC_FILE) to add or

modify timing rules.

To print the configuration of the makefile (targeted FPGA part and family, tool

settings, and board I/O bonfiguration) run:

$ make print-config

PDC files:

The physical constraints generation system may seem overly compilcated to begin

with, but is design to make it easy and simple to add additional board and

module support, switch the design between boards, or modify existing

configurations.

The physical constraints file generation starts with defining some variables

with pin numbers, corresponding to the actual FPGA pins, depending on the FPGA

board. At present, the only CPU board supported is the ORSoC CPU board pin out.

The variables assigned pin numbers are in the bin/orsoccpuboard.mkpins file.

This file is design to be included by other files, wishing to use the ORSoC CPU

board variables (pin numbers). The variables in the CPU board file are then

used by other files, namely files which define uses for expansion pins on the

CPU board. For example, the two headers, JP1 and JP6, and their associated

variables from the ORSoC CPU board .mkpins file are used in the

orsocexpboard.mkpins file. Support for other I/O boards could be added by

creating a new .mkpins file, and creating a list of new, appropriate variable

names corresponding to the pins from the CPU board (in the ORSoC CPU board's

case, the JP1 and JP6 header pin variables.)

Finally, the variables for each actual I/O in the design must be assigned

something. The .mkpinassigns do this. They tie together the CPU and any I/O

board variable assigns, making it simple and easy to assign the variables used

in the Makefile during PDC generation, to the variables created in the .mkpins

files. The three main parts, then, the CPU board .mkpins file, expansion board

.mkpins file, overall board .mkpinassigns file and Makefile PDC rule are the

components to generating a PDC.

Of course, a .mkpinassigns file can also simply contain raw pin numbers for

each I/O port pin, or include a single .mkpins file with just a single board

definition. The idea is it's highly modular and configurable before doing the

final define of each I/O port's signal.

Every possible I/O from the design has an entry in the $(PDC_FILE) rule of the

Actel backend PAR Makefile. Almost all are surrounded by if statements checking

for the corresponding module's inclusion in the design.

Set the overall I/O config .mkpinassigns file by setting BOARD_CONFIG at make

time. The default is orsoccpuexpio.mkpinassigns. All these files should reside

in the bin/ path.

$ make all BOARD_CONFIG=mynew.mkpinassigns

To test the generated PDC file, do

$ make pdc_file BOARD_CONFIG=mynew.mkpinassigns