| 1 |
408 |
julius |
# Script to do compilation in Actel's tools then PAR.
|
| 2 |
|
|
# Need windows Libero for bitgen
|
| 3 |
|
|
#
|
| 4 |
|
|
# Is easy to target to other versions of ORSoC dev board:
|
| 5 |
|
|
# for old A3P1000, 25MHz board:
|
| 6 |
|
|
#$ make FPGA_FAMILY=ProASIC3 FPGA_PART=A3P1000 all
|
| 7 |
|
|
#
|
| 8 |
|
|
#
|
| 9 |
|
|
# Can also set following environment variables to have the correspondingly
|
| 10 |
|
|
# affect the placer:
|
| 11 |
|
|
# PLACE_INCREMENTAL=on
|
| 12 |
|
|
# ROUTE_INCREMENTAL=on
|
| 13 |
|
|
# PLACER_HIGH_EFFORT=on
|
| 14 |
|
|
#
|
| 15 |
|
|
# So command above would look like:
|
| 16 |
|
|
#$ make FPGA_FAMILY=ProASIC3 FPGA_PART=A3P1000 all PLACE_INCREMENTAL=on ROUTE_INCREMENTAL=on PLACER_HIGH_EFFORT=on
|
| 17 |
|
|
#
|
| 18 |
|
|
|
| 19 |
|
|
# Name of the directory we're currently in
|
| 20 |
|
|
CUR_DIR=$(shell pwd)
|
| 21 |
|
|
|
| 22 |
|
|
VENDOR=actel
|
| 23 |
|
|
VENDOR_TCL_SHELL=acttclsh
|
| 24 |
|
|
|
| 25 |
|
|
PROJECT_NAME=orpsoc
|
| 26 |
|
|
PROJECT_TOP_NAME=$(PROJECT_NAME)_top
|
| 27 |
|
|
PROJ_ADB_FILE_NAME=$(PROJECT_NAME).adb
|
| 28 |
|
|
PROJ_ADB_FILE=$(PROJ_ADB_FILE_NAME)
|
| 29 |
|
|
|
| 30 |
|
|
# The root path of the whole project
|
| 31 |
|
|
BOARD_DIR ?=$(CUR_DIR)/../../..
|
| 32 |
|
|
PROJECT_ROOT=$(BOARD_DIR)/../../..
|
| 33 |
|
|
|
| 34 |
|
|
BOARD_RTL_PATH=$(BOARD_DIR)/rtl
|
| 35 |
|
|
BOARD_RTL_VERILOG_PATH=$(BOARD_RTL_PATH)/verilog
|
| 36 |
|
|
BOARD_RTL_VERILOG_INCLUDES=$(BOARD_RTL_VERILOG_PATH)/include
|
| 37 |
|
|
PROJECT_VERILOG_DEFINES=$(BOARD_RTL_VERILOG_INCLUDES)/$(PROJECT_NAME)-defines.v
|
| 38 |
|
|
|
| 39 |
|
|
SYN_PATH=$(BOARD_DIR)/syn/synplify
|
| 40 |
|
|
|
| 41 |
|
|
SW_PATH=$(PROJECT_ROOT)/sw
|
| 42 |
|
|
|
| 43 |
|
|
PAR_PATH=$(BOARD_DIR)/backend/par
|
| 44 |
|
|
PAR_RUN_PATH=$(PAR_PATH)/run
|
| 45 |
|
|
PAR_OUT_PATH=$(PAR_PATH)/out
|
| 46 |
|
|
|
| 47 |
|
|
# Required EDIF file names
|
| 48 |
|
|
EDIF_NAME=$(PROJECT_TOP_NAME).edn
|
| 49 |
|
|
PROJ_EDF_FILE=$(SYN_PATH)/out/$(EDIF_NAME)
|
| 50 |
|
|
|
| 51 |
|
|
# TCL script names
|
| 52 |
|
|
TCL_SCRIPT_START=start.tcl
|
| 53 |
|
|
TCL_SCRIPT_COMPILE=compile.tcl
|
| 54 |
|
|
TCL_SCRIPT_PAR=par.tcl
|
| 55 |
|
|
TCL_SCRIPT_CREATE_COMPILE_PAR=create-compile-par.tcl
|
| 56 |
439 |
julius |
TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN=create-compile-par-bitgen.tcl
|
| 57 |
408 |
julius |
TCL_SCRIPT_REPORT=report.tcl
|
| 58 |
|
|
TCL_SCRIPT_BITGEN=bitgen.tcl
|
| 59 |
|
|
# Generate these every time
|
| 60 |
|
|
.PHONY: $(TCL_SCRIPT_START) $(TCL_SCRIPT_COMPILE) $(TCL_SCRIPT_PAR) $(TCL_SCRIPT_BITGEN)
|
| 61 |
|
|
|
| 62 |
|
|
|
| 63 |
|
|
# TCL script generation parameters
|
| 64 |
|
|
# Potentially we want more here!
|
| 65 |
|
|
# All are assigned with ?= allowing them to be redfined on the command line
|
| 66 |
|
|
|
| 67 |
|
|
FPGA_FAMILY ?=ProASIC3E
|
| 68 |
|
|
FPGA_PART ?=A3PE1500
|
| 69 |
|
|
FPGA_PACKAGE ?=\"208 PQFP\"
|
| 70 |
|
|
FPGA_VOLTAGE ?=1.5
|
| 71 |
|
|
#FPGA_SPEED_GRADE ?=-2
|
| 72 |
|
|
FPGA_SPEED_GRADE ?=STD
|
| 73 |
|
|
FPGA_TEMP_RANGE=COM # either COM or IND
|
| 74 |
|
|
FPGA_VOLT_RANGE=COM # either COM or IND
|
| 75 |
|
|
COMP_DIR ?=parcomp
|
| 76 |
|
|
|
| 77 |
|
|
# Tool effort settings
|
| 78 |
|
|
# Set to 'on' to enable them
|
| 79 |
|
|
PLACE_INCREMENTAL ?= off
|
| 80 |
|
|
ROUTE_INCREMENTAL ?= off
|
| 81 |
|
|
PLACER_HIGH_EFFORT ?= off
|
| 82 |
|
|
|
| 83 |
|
|
PDC_FILE ?=$(PROJECT_NAME).pdc
|
| 84 |
|
|
SDC_FILE ?=$(PROJECT_NAME).sdc
|
| 85 |
|
|
|
| 86 |
|
|
|
| 87 |
|
|
DEFINES_FILE_CUTOFF=$(shell grep -n "end of included module defines" $(PROJECT_VERILOG_DEFINES) | cut -d ':' -f 1)
|
| 88 |
|
|
DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
|
| 89 |
|
|
# Rule to look at what defines are being extracted from main file
|
| 90 |
|
|
print-defines:
|
| 91 |
|
|
@echo; echo "\t### Design defines ###"; echo
|
| 92 |
|
|
@echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
|
| 93 |
|
|
@echo $(DESIGN_DEFINES)
|
| 94 |
|
|
|
| 95 |
|
|
# Rule to print out current config of current session
|
| 96 |
|
|
print-config:
|
| 97 |
|
|
@echo; echo "\t### PAR make configuration ###"; echo
|
| 98 |
|
|
@echo "\tFPGA_FAMILY="$(FPGA_FAMILY)
|
| 99 |
|
|
@echo "\tFPGA_PART="$(FPGA_PART)
|
| 100 |
|
|
@echo "\tFPGA_PACKAGE="$(FPGA_PACKAGE)
|
| 101 |
|
|
@echo "\tFPGA_VOLTAGE="$(FPGA_VOLTAGE)
|
| 102 |
|
|
@echo "\tFPGA_SPEED_GRADE="$(FPGA_SPEED_GRADE)
|
| 103 |
|
|
@echo "\tFPGA_TEMP_RANGE="$(FPGA_TEMP_RANGE)
|
| 104 |
|
|
@echo "\tFPGA_VOLT_RANGE="$(FPGA_VOLT_RANGE)
|
| 105 |
|
|
@echo "\tPLACE_INCREMENTAL="$(PLACE_INCREMENTAL)
|
| 106 |
|
|
@echo "\tROUTE_INCREMENTAL="$(ROUTE_INCREMENTAL)
|
| 107 |
|
|
@echo "\tPLACER_HIGH_EFFORT="$(PLACER_HIGH_EFFORT)
|
| 108 |
|
|
@echo
|
| 109 |
|
|
@echo "\tBackend pinout script:"
|
| 110 |
|
|
@echo "\tBOARD_CONFIG="$(BOARD_CONFIG)
|
| 111 |
|
|
|
| 112 |
|
|
|
| 113 |
|
|
# Set V=1 when calling make to enable verbose output
|
| 114 |
|
|
# mainly for debugging purposes.
|
| 115 |
|
|
ifeq ($(V), 1)
|
| 116 |
|
|
Q=
|
| 117 |
|
|
else
|
| 118 |
|
|
Q ?=@
|
| 119 |
|
|
endif
|
| 120 |
|
|
|
| 121 |
|
|
TIME_CMD=time -p
|
| 122 |
|
|
|
| 123 |
|
|
# Rule for everything from, potentially, synthesis up to PAR
|
| 124 |
439 |
julius |
all: print-config print-defines create-compile-par-bitgen
|
| 125 |
408 |
julius |
|
| 126 |
|
|
# Not possible to do programming file generation under Linux
|
| 127 |
|
|
# not with the free tools
|
| 128 |
|
|
bitgen: $(TCL_SCRIPT_BITGEN)
|
| 129 |
|
|
$(TIME_CMD) $(VENDOR_TCL_SHELL) $<
|
| 130 |
|
|
|
| 131 |
|
|
# Leave this with no pre-reqs so we can call it seperately
|
| 132 |
|
|
create-compile-par: sdc-file pdc-file $(PROJ_EDF_FILE) $(TCL_SCRIPT_CREATE_COMPILE_PAR)
|
| 133 |
|
|
$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_CREATE_COMPILE_PAR)
|
| 134 |
|
|
|
| 135 |
439 |
julius |
create-compile-par-bitgen: sdc-file pdc-file $(PROJ_EDF_FILE) $(TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN)
|
| 136 |
|
|
$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN)
|
| 137 |
|
|
|
| 138 |
408 |
julius |
par: $(TCL_SCRIPT_PAR)
|
| 139 |
|
|
$(TIME_CMD) $(VENDOR_TCL_SHELL) $<
|
| 140 |
|
|
|
| 141 |
|
|
compile: $(TCL_SCRIPT_COMPILE)
|
| 142 |
|
|
$(TIME_CMD) $(VENDOR_TCL_SHELL) $<
|
| 143 |
|
|
|
| 144 |
|
|
create: print-config print-defines sdc-file pdc-file $(PROJ_ADB_FILE)
|
| 145 |
|
|
|
| 146 |
|
|
report: $(TCL_SCRIPT_REPORT)
|
| 147 |
|
|
$(TIME_CMD) $(VENDOR_TCL_SHELL) $<
|
| 148 |
|
|
|
| 149 |
|
|
$(PROJ_ADB_FILE): $(PROJ_EDF_FILE) $(TCL_SCRIPT_START)
|
| 150 |
|
|
$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_START)
|
| 151 |
|
|
|
| 152 |
|
|
$(PROJ_EDF_FILE):
|
| 153 |
|
|
$(MAKE) -C $(SYN_PATH)/run all
|
| 154 |
|
|
|
| 155 |
|
|
create-compile: create compile
|
| 156 |
|
|
|
| 157 |
|
|
clean:
|
| 158 |
|
|
rm -rf *.rpt *.log *~ *.tcl *.lok *.tmp *.dtf $(SDC_FILE) $(PDC_FILE) *.adb
|
| 159 |
|
|
|
| 160 |
|
|
clean-syn:
|
| 161 |
|
|
$(MAKE) -C $(SYN_PATH)/run clean-all
|
| 162 |
|
|
|
| 163 |
|
|
clean-sw:
|
| 164 |
|
|
$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
|
| 165 |
|
|
$(MAKE) -C $(SW_PATH)/lib clean-all
|
| 166 |
|
|
|
| 167 |
|
|
|
| 168 |
|
|
clean-all: clean-sw clean-syn clean
|
| 169 |
|
|
|
| 170 |
|
|
STEP_NAME=$(shell echo $(TCL_FILE) | cut -d '.' -f 1)
|
| 171 |
|
|
|
| 172 |
|
|
# Rule to create the different steps of compilation with the Actel Designer
|
| 173 |
|
|
# tool.
|
| 174 |
|
|
# We need to create dollar signs ($) to dereference variables in the TCL
|
| 175 |
|
|
# scripts, but we also don't want make or bash thinking the variables we write
|
| 176 |
|
|
# with $s on the front are for them.. so we separate them from the actual
|
| 177 |
|
|
# variable name with ending and beginning the strings again, eg: $$""varname ..
|
| 178 |
|
|
|
| 179 |
|
|
|
| 180 |
|
|
# Just create the project
|
| 181 |
|
|
$(TCL_SCRIPT_START):
|
| 182 |
|
|
TCL_FILE=$@ $(MAKE) tcl-common
|
| 183 |
|
|
$(Q)echo "run_designer \"Starting new project\" \"" >> $@
|
| 184 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-create-project-tcl
|
| 185 |
|
|
$(Q)echo "\"">> $@
|
| 186 |
|
|
$(Q)echo >> $@
|
| 187 |
|
|
|
| 188 |
|
|
# Open and compile the project's netlist
|
| 189 |
|
|
$(TCL_SCRIPT_COMPILE):
|
| 190 |
|
|
TCL_FILE=$@ $(MAKE) tcl-common
|
| 191 |
|
|
$(Q)echo "run_designer \"Compiling\" \" " >> $@
|
| 192 |
|
|
$(Q)echo " open_design $$""proj_name.adb " >> $(TCL_FILE)
|
| 193 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-compile-project-tcl
|
| 194 |
|
|
$(Q)echo "\"">> $@
|
| 195 |
|
|
|
| 196 |
|
|
# Import SDC and do place and route
|
| 197 |
|
|
$(TCL_SCRIPT_PAR):
|
| 198 |
|
|
TCL_FILE=$@ $(MAKE) tcl-common
|
| 199 |
|
|
$(Q)echo "run_designer \"PAR\" \" " >> $@
|
| 200 |
|
|
$(Q)echo " open_design $$""proj_name.adb " >> $@
|
| 201 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-par-project-tcl
|
| 202 |
|
|
$(Q)echo "\"">> $@
|
| 203 |
|
|
|
| 204 |
|
|
# Generate programming file
|
| 205 |
|
|
$(TCL_SCRIPT_BITGEN):
|
| 206 |
|
|
TCL_FILE=$@ $(MAKE) tcl-common
|
| 207 |
|
|
$(Q)echo "run_designer \"exporting PDB file\" \" " >> $@
|
| 208 |
|
|
$(Q)echo " open_design $$""proj_name.adb " >> $@
|
| 209 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-bitgen-project-tcl
|
| 210 |
|
|
$(Q)echo "\"">> $@
|
| 211 |
|
|
|
| 212 |
|
|
# Generate reports
|
| 213 |
|
|
$(TCL_SCRIPT_REPORT):
|
| 214 |
|
|
TCL_FILE=$@ $(MAKE) tcl-common
|
| 215 |
|
|
$(Q)echo "run_designer \"Generating timing reports\" \" " >> $@
|
| 216 |
|
|
$(Q)echo " open_design $$""proj_name.adb " >> $@
|
| 217 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-report-project-tcl
|
| 218 |
|
|
$(Q)echo "\"">> $@
|
| 219 |
|
|
|
| 220 |
|
|
# Do project creation, compile and PAR in one single run of the tool
|
| 221 |
|
|
$(TCL_SCRIPT_CREATE_COMPILE_PAR):
|
| 222 |
|
|
TCL_FILE=$@ $(MAKE) tcl-common
|
| 223 |
|
|
$(Q)echo "run_designer \"Create compile and PAR design project\" \" " >> $@
|
| 224 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-create-project-tcl
|
| 225 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-compile-project-tcl
|
| 226 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-par-project-tcl
|
| 227 |
|
|
$(Q)echo "\"">> $@
|
| 228 |
|
|
$(Q)echo >> $@
|
| 229 |
|
|
|
| 230 |
439 |
julius |
# Do project creation, compile and PAR in one single run of the tool
|
| 231 |
|
|
$(TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN):
|
| 232 |
|
|
TCL_FILE=$@ $(MAKE) tcl-common
|
| 233 |
|
|
$(Q)echo "run_designer \"Create compile and PAR and generate programming file\" \" " >> $@
|
| 234 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-create-project-tcl
|
| 235 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-compile-project-tcl
|
| 236 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-par-project-tcl
|
| 237 |
|
|
TCL_FILE=$@ $(MAKE) dump-actel-bitgen-project-tcl
|
| 238 |
|
|
$(Q)echo "\"">> $@
|
| 239 |
|
|
$(Q)echo >> $@
|
| 240 |
|
|
|
| 241 |
408 |
julius |
# The different texts that we dump out for the different sets of command files
|
| 242 |
|
|
|
| 243 |
|
|
# This is the common header, setting variables in the TCL file
|
| 244 |
|
|
tcl-common:
|
| 245 |
|
|
$(Q)rm -f $(TCL_FILE);
|
| 246 |
|
|
$(Q)echo; echo "\tGenerating "$(TCL_FILE); echo
|
| 247 |
|
|
$(Q)echo "set compile_directory "$(COMP_DIR) >> $(TCL_FILE)
|
| 248 |
|
|
$(Q)echo "set proj_name "$(PROJECT_NAME) >> $(TCL_FILE)
|
| 249 |
|
|
$(Q)echo "set top_name "$(PROJECT_TOP_NAME) >> $(TCL_FILE)
|
| 250 |
|
|
$(Q)echo "set family "$(FPGA_FAMILY) >> $(TCL_FILE)
|
| 251 |
|
|
$(Q)echo "set part "$(FPGA_PART) >> $(TCL_FILE)
|
| 252 |
|
|
$(Q)echo "set package "$(FPGA_PACKAGE) >> $(TCL_FILE)
|
| 253 |
|
|
$(Q)echo "set pdc_filename "$(PDC_FILE) >> $(TCL_FILE)
|
| 254 |
|
|
$(Q)echo "set sdc_filename "$(SDC_FILE) >> $(TCL_FILE)
|
| 255 |
|
|
$(Q)echo >> $(TCL_FILE)
|
| 256 |
|
|
$(Q)echo " proc run_designer {message script} {" >> $(TCL_FILE)
|
| 257 |
|
|
$(Q)echo " puts \"Designer: $$""message\"" >> $(TCL_FILE)
|
| 258 |
|
|
$(Q)echo " set f [open designer.tcl w]" >> $(TCL_FILE)
|
| 259 |
|
|
$(Q)echo " puts $$""f $$""script" >> $(TCL_FILE)
|
| 260 |
|
|
$(Q)echo " close $$""f " >> $(TCL_FILE)
|
| 261 |
|
|
$(Q)echo " puts [exec designer SCRIPT:designer.tcl LOGFILE:"$(STEP_NAME)".log]" >> $(TCL_FILE)
|
| 262 |
|
|
$(Q)echo "}" >> $(TCL_FILE)
|
| 263 |
|
|
$(Q)echo >> $(TCL_FILE)
|
| 264 |
|
|
|
| 265 |
|
|
# TCL commands to create and setup a new project in Designer
|
| 266 |
|
|
dump-actel-create-project-tcl:
|
| 267 |
|
|
$(Q)echo " new_design " \\ >> $(TCL_FILE)
|
| 268 |
|
|
$(Q)echo " -name $$""proj_name " \\ >> $(TCL_FILE)
|
| 269 |
|
|
$(Q)echo " -family $$""family " \\ >> $(TCL_FILE)
|
| 270 |
|
|
$(Q)echo " -path ." >> $(TCL_FILE)
|
| 271 |
|
|
$(Q)echo " set_device " \\ >> $(TCL_FILE)
|
| 272 |
|
|
$(Q)echo " -die $$""part " \\ >> $(TCL_FILE)
|
| 273 |
|
|
$(Q)echo " -package \\\"$$""package\\\" " \\ >> $(TCL_FILE)
|
| 274 |
|
|
$(Q)echo " -speed "$(FPGA_SPEED_GRADE)" " \\ >> $(TCL_FILE)
|
| 275 |
|
|
$(Q)echo " -voltage "$(FPGA_VOLTAGE)" " \\ >> $(TCL_FILE)
|
| 276 |
|
|
$(Q)echo " -iostd LVTTL " \\ >> $(TCL_FILE)
|
| 277 |
|
|
$(Q)echo " -jtag yes " \\ >> $(TCL_FILE)
|
| 278 |
|
|
$(Q)echo " -probe yes " \\ >> $(TCL_FILE)
|
| 279 |
|
|
$(Q)echo " -trst yes " \\ >> $(TCL_FILE)
|
| 280 |
|
|
$(Q)echo " -temprange "$(FPGA_TEMP_RANGE)" " \\ >> $(TCL_FILE)
|
| 281 |
|
|
$(Q)echo " -voltrange "$(FPGA_VOLT_RANGE)" " >> $(TCL_FILE)
|
| 282 |
|
|
$(Q)echo " import_source " \\ >> $(TCL_FILE)
|
| 283 |
|
|
$(Q)echo " -format edif " \\ >> $(TCL_FILE)
|
| 284 |
|
|
$(Q)echo " -edif_flavor GENERIC "$(PROJ_EDF_FILE)" "\\ >> $(TCL_FILE)
|
| 285 |
|
|
$(Q)echo " -format pdc " \\ >> $(TCL_FILE)
|
| 286 |
|
|
$(Q)echo " -abort_on_error yes $$""pdc_filename " \\ >> $(TCL_FILE)
|
| 287 |
|
|
$(Q)echo " -merge_physical yes " \\ >> $(TCL_FILE)
|
| 288 |
|
|
$(Q)echo " -merge_timing yes " >> $(TCL_FILE)
|
| 289 |
|
|
$(Q)echo " save_design $$""proj_name.adb " >> $(TCL_FILE)
|
| 290 |
|
|
|
| 291 |
|
|
# TCL commands to compile a project in Designer
|
| 292 |
|
|
dump-actel-compile-project-tcl:
|
| 293 |
|
|
$(Q)echo " compile " \\ >> $(TCL_FILE)
|
| 294 |
|
|
$(Q)echo " -pdc_abort_on_error on " \\ >> $(TCL_FILE)
|
| 295 |
|
|
$(Q)echo " -pdc_eco_display_unmatched_objects off " \\ >> $(TCL_FILE)
|
| 296 |
|
|
$(Q)echo " -pdc_eco_max_warnings 10000 " \\ >> $(TCL_FILE)
|
| 297 |
|
|
$(Q)echo " -demote_globals off " \\ >> $(TCL_FILE)
|
| 298 |
|
|
$(Q)echo " -demote_globals_max_fanout 12 " \\ >> $(TCL_FILE)
|
| 299 |
|
|
$(Q)echo " -promote_globals off " \\ >> $(TCL_FILE)
|
| 300 |
|
|
$(Q)echo " -promote_globals_min_fanout 200 " \\ >> $(TCL_FILE)
|
| 301 |
|
|
$(Q)echo " -promote_globals_max_limit 0 " \\ >> $(TCL_FILE)
|
| 302 |
|
|
$(Q)echo " -localclock_max_shared_instances 12 " \\ >> $(TCL_FILE)
|
| 303 |
|
|
$(Q)echo " -localclock_buffer_tree_max_fanout 12 " \\ >> $(TCL_FILE)
|
| 304 |
|
|
$(Q)echo " -combine_register off " \\ >> $(TCL_FILE)
|
| 305 |
|
|
$(Q)echo " -delete_buffer_tree off " \\ >> $(TCL_FILE)
|
| 306 |
|
|
$(Q)echo " -delete_buffer_tree_max_fanout 12 " \\ >> $(TCL_FILE)
|
| 307 |
|
|
$(Q)echo " -report_high_fanout_nets_limit 10 " >> $(TCL_FILE)
|
| 308 |
|
|
$(Q)echo " save_design $$""proj_name.adb " >> $(TCL_FILE)
|
| 309 |
|
|
|
| 310 |
|
|
# TCL commands to ipmort SDC and do PAR on project
|
| 311 |
|
|
dump-actel-par-project-tcl:
|
| 312 |
|
|
$(Q)echo " import_aux " \\ >> $(TCL_FILE)
|
| 313 |
|
|
$(Q)echo " -format sdc $$""sdc_filename " >> $(TCL_FILE)
|
| 314 |
|
|
$(Q)echo " layout " \\ >> $(TCL_FILE)
|
| 315 |
|
|
$(Q)echo " -timing_driven " \\ >> $(TCL_FILE)
|
| 316 |
|
|
$(Q)echo " -run_placer on " \\ >> $(TCL_FILE)
|
| 317 |
|
|
$(Q)echo " -place_incremental "$(PLACE_INCREMENTAL) \\ >> $(TCL_FILE)
|
| 318 |
|
|
$(Q)echo " -run_router on " \\ >> $(TCL_FILE)
|
| 319 |
|
|
$(Q)echo " -route_incremental "$(ROUTE_INCREMENTAL) \\ >> $(TCL_FILE)
|
| 320 |
|
|
$(Q)echo " -placer_high_effort "$(PLACER_HIGH_EFFORT) >> $(TCL_FILE)
|
| 321 |
|
|
$(Q)echo " save_design $$""proj_name.adb " >> $(TCL_FILE)
|
| 322 |
|
|
|
| 323 |
|
|
# TCL commands to generate programming file (PDB) from project
|
| 324 |
|
|
dump-actel-bitgen-project-tcl:
|
| 325 |
|
|
$(Q)echo " export " \\ >> $(TCL_FILE)
|
| 326 |
|
|
$(Q)echo " -format pdb " \\ >> $(TCL_FILE)
|
| 327 |
|
|
$(Q)echo " -feature prog_fpga " \\ >> $(TCL_FILE)
|
| 328 |
|
|
$(Q)echo " $$""proj_name.pdb " >> $(TCL_FILE)
|
| 329 |
|
|
$(Q)echo " save_design $$""proj_name.adb " >> $(TCL_FILE)
|
| 330 |
|
|
|
| 331 |
|
|
# TCL commands to generate timing reports of project
|
| 332 |
|
|
dump-actel-report-project-tcl:
|
| 333 |
|
|
$(Q)echo " report " \\ >> $(TCL_FILE)
|
| 334 |
|
|
$(Q)echo " -type timer " \\ >> $(TCL_FILE)
|
| 335 |
|
|
$(Q)echo " -analysis max " \\ >> $(TCL_FILE)
|
| 336 |
|
|
$(Q)echo " -print_summary yes " \\ >> $(TCL_FILE)
|
| 337 |
|
|
$(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE)
|
| 338 |
|
|
$(Q)echo " -print_paths yes " \\ >> $(TCL_FILE)
|
| 339 |
|
|
$(Q)echo " -max_paths 5 " \\ >> $(TCL_FILE)
|
| 340 |
|
|
$(Q)echo " -max_expanded_paths 1 " \\ >> $(TCL_FILE)
|
| 341 |
|
|
$(Q)echo " -include_user_sets no " \\ >> $(TCL_FILE)
|
| 342 |
|
|
$(Q)echo " -include_pin_to_pin yes " \\ >> $(TCL_FILE)
|
| 343 |
|
|
$(Q)echo " -select_clock_domains no " \\ >> $(TCL_FILE)
|
| 344 |
|
|
$(Q)echo " "$(PROJECT_NAME)"-timing.rpt " >> $(TCL_FILE)
|
| 345 |
|
|
$(Q)echo " report " \\ >> $(TCL_FILE)
|
| 346 |
|
|
$(Q)echo " -type timing_violations " \\ >> $(TCL_FILE)
|
| 347 |
|
|
$(Q)echo " -analysis max " \\ >> $(TCL_FILE)
|
| 348 |
|
|
$(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE)
|
| 349 |
|
|
$(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE)
|
| 350 |
|
|
$(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE)
|
| 351 |
|
|
$(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE)
|
| 352 |
|
|
$(Q)echo " "$(PROJECT_NAME)"-timviol.rpt " >> $(TCL_FILE)
|
| 353 |
|
|
$(Q)echo " report " \\ >> $(TCL_FILE)
|
| 354 |
|
|
$(Q)echo " -type timing_violations " \\ >> $(TCL_FILE)
|
| 355 |
|
|
$(Q)echo " -analysis min " \\ >> $(TCL_FILE)
|
| 356 |
|
|
$(Q)echo " -use_slack_threshold no " \\ >> $(TCL_FILE)
|
| 357 |
|
|
$(Q)echo " -limit_max_paths yes " \\ >> $(TCL_FILE)
|
| 358 |
|
|
$(Q)echo " -max_paths 100 " \\ >> $(TCL_FILE)
|
| 359 |
|
|
$(Q)echo " -max_expanded_paths 0 " \\ >> $(TCL_FILE)
|
| 360 |
|
|
$(Q)echo " "$(PROJECT_NAME)"-timmindly.rpt " >> $(TCL_FILE)
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
|
| 364 |
|
|
sdc-file:
|
| 365 |
|
|
$(Q)for define in $(DESIGN_DEFINES); do export $$define=1; done; \
|
| 366 |
|
|
$(MAKE) $(SDC_FILE)
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
#
|
| 370 |
|
|
# Constraint script generation
|
| 371 |
|
|
#
|
| 372 |
|
|
|
| 373 |
|
|
ETH_CLK_PERIOD_NS ?= 8.0000 # 125 MHz
|
| 374 |
|
|
ETH_CLK_PERIOD_HALF_NS ?= 4.0000 # 125 MHz
|
| 375 |
|
|
SDRAM_OUT_DELAY ?=1.5
|
| 376 |
|
|
SDRAM_IN_DELAY ?=0.8
|
| 377 |
|
|
# Whittle away at the defines until we have only the Wishbone frequency (MHz) integer
|
| 378 |
|
|
WB_FREQ_MHZ ?=$(shell echo $(DESIGN_DEFINES) | tr " " "\n" | grep BOARD | grep _WB | tr "_" "\n" | grep WB | cut -d 'B' -f 2)
|
| 379 |
|
|
XTAL_FREQ_MHZ ?=$(shell echo $(DESIGN_DEFINES) | tr " " "\n" | grep BOARD | grep _XTAL | tr "_" "\n" | grep XTAL | cut -d 'L' -f 2)
|
| 380 |
|
|
|
| 381 |
|
|
ifeq ($(XTAL_FREQ_MHZ), 64)
|
| 382 |
|
|
SYS_CLK_PERIOD_NS ?= 15.625 # 64 MHz
|
| 383 |
|
|
# These are for board clock with 64 MHz XTAL
|
| 384 |
|
|
ifeq ($(WB_FREQ_MHZ), 16)
|
| 385 |
|
|
WB_SDC_GENCLK_DIVIDE_BY ?=144
|
| 386 |
|
|
WB_SDC_GENCLK_MULTIPLY_BY ?=36
|
| 387 |
|
|
endif
|
| 388 |
|
|
ifeq ($(WB_FREQ_MHZ), 18)
|
| 389 |
|
|
WB_SDC_GENCLK_DIVIDE_BY ?=128
|
| 390 |
|
|
WB_SDC_GENCLK_MULTIPLY_BY ?=36
|
| 391 |
|
|
endif
|
| 392 |
|
|
ifeq ($(WB_FREQ_MHZ), 20)
|
| 393 |
|
|
WB_SDC_GENCLK_DIVIDE_BY ?=144
|
| 394 |
|
|
WB_SDC_GENCLK_MULTIPLY_BY ?=45
|
| 395 |
|
|
endif
|
| 396 |
|
|
endif # ifeq ($(XTAL_FREQ_MHZ), 64)
|
| 397 |
|
|
|
| 398 |
|
|
ifeq ($(XTAL_FREQ_MHZ), 25)
|
| 399 |
|
|
SYS_CLK_PERIOD_NS ?= 40.00 # 25 MHz
|
| 400 |
|
|
# These are for board with 25 MHz XTAL
|
| 401 |
|
|
ifeq ($(WB_FREQ_MHZ), 20)
|
| 402 |
|
|
WB_SDC_GENCLK_DIVIDE_BY ?=125
|
| 403 |
|
|
WB_SDC_GENCLK_MULTIPLY_BY ?=100
|
| 404 |
|
|
endif
|
| 405 |
|
|
ifeq ($(WB_FREQ_MHZ), 24)
|
| 406 |
|
|
WB_SDC_GENCLK_DIVIDE_BY ?=125
|
| 407 |
|
|
WB_SDC_GENCLK_MULTIPLY_BY ?=120
|
| 408 |
|
|
endif
|
| 409 |
|
|
endif # ifeq ($(XTAL_FREQ_MHZ), 25)
|
| 410 |
|
|
|
| 411 |
|
|
print-freq:
|
| 412 |
|
|
$(Q)echo "XTAL Freq: "$(XTAL_FREQ_MHZ)"MHz"
|
| 413 |
|
|
$(Q)echo "sys_clk_pad_i period: "$(SYS_CLK_PERIOD_NS)"ns"
|
| 414 |
|
|
$(Q)echo "Multiply XTAL by "$(WB_SDC_GENCLK_MULTIPLY_BY)" and divide by "$(WB_SDC_GENCLK_DIVIDE_BY)" to get WB frequency"
|
| 415 |
|
|
$(Q)echo "WB Freq: "$(WB_FREQ_MHZ)"MHz"
|
| 416 |
|
|
|
| 417 |
|
|
|
| 418 |
|
|
#
|
| 419 |
|
|
# Timing (SDC)
|
| 420 |
|
|
#
|
| 421 |
|
|
$(SDC_FILE):
|
| 422 |
|
|
$(Q)echo; echo "\t### Generating SDC file ###"; echo
|
| 423 |
|
|
$(Q)rm -f $@
|
| 424 |
|
|
$(Q) echo "set sdc_version 1.7" >> $@
|
| 425 |
|
|
$(Q) echo "######## Clock Constraints ########" >> $@
|
| 426 |
|
|
$(Q) echo "create_clock -name { sys_clk_pad_i } -period "$(SYS_CLK_PERIOD_NS)" { sys_clk_pad_i } " >> $@
|
| 427 |
|
|
$(Q)if [ ! -z $$JTAG_DEBUG ]; then \
|
| 428 |
|
|
echo "create_clock -name { tck_pad_i } -period 50.000 { tck_pad_i } " >> $@; \
|
| 429 |
|
|
fi
|
| 430 |
|
|
$(Q)if [ ! -z $$ETH_CLK ]; then \
|
| 431 |
|
|
echo "create_clock -name { eth_clk_pad_i } -period "$(ETH_CLK_PERIOD_NS)" { eth_clk_pad_i } " >> $@; \
|
| 432 |
|
|
fi
|
| 433 |
|
|
$(Q)if [ ! -z $$SMII0 ]; then \
|
| 434 |
|
|
echo "create_clock -name { smii0/smii_if0/mtx_clk_gen:Q } -period 40.000 { smii0/smii_if0/mtx_clk_gen:Q } " >> $@; \
|
| 435 |
|
|
echo "create_clock -name { smii0/smii_if0/mrx_clk_gen:Q } -period 40.000 { smii0/smii_if0/mrx_clk_gen:Q } " >> $@; \
|
| 436 |
|
|
echo "set_output_delay -max 3.000 -clock { eth_clk_pad_i } [get_ports { eth0_smii_sync_pad_o eth0_smii_tx_pad_o }] " >> $@; \
|
| 437 |
|
|
echo "set_output_delay -min -1.500 -clock { eth_clk_pad_i } [get_ports { eth0_smii_sync_pad_o eth0_smii_tx_pad_o }] " >> $@; \
|
| 438 |
|
|
fi
|
| 439 |
|
|
$(Q) echo "######## Specify Asynchronous paths between domains ########" >> $@
|
| 440 |
|
|
$(Q) echo "set_false_path -from [ get_clocks { clkgen0/pll0/Core:GLA }] -to [ get_clocks { clkgen0/pll0/Core:GLB }]" >> $@
|
| 441 |
|
|
$(Q) echo "set_false_path -from [ get_clocks { clkgen0/pll0/Core:GLB }] -to [ get_clocks { clkgen0/pll0/Core:GLA }]" >> $@
|
| 442 |
|
|
$(Q) echo "######## Input Delay Constraints ########" >> $@
|
| 443 |
|
|
$(Q) echo "set_input_delay -max "$(SDRAM_IN_DELAY)" -clock { clkgen0/pll0/Core:GLA } { sdram_dq_pad_io[*] }" >> $@
|
| 444 |
|
|
$(Q) echo "######## Output Delay Constraints ########" >> $@
|
| 445 |
|
|
$(Q) echo "set_output_delay -max "$(SDRAM_OUT_DELAY)" -clock { clkgen0/pll0/Core:GLA } { sdram_dq_pad_io[*] }" >> $@
|
| 446 |
|
|
$(Q) echo "set_output_delay -max "$(SDRAM_OUT_DELAY)" -clock { clkgen0/pll0/Core:GLA } { sdram_ras_pad_o }" >> $@
|
| 447 |
|
|
$(Q) echo "set_output_delay -max "$(SDRAM_OUT_DELAY)" -clock { clkgen0/pll0/Core:GLA } { sdram_cas_pad_o }" >> $@
|
| 448 |
|
|
$(Q) echo "set_output_delay -max "$(SDRAM_OUT_DELAY)" -clock { clkgen0/pll0/Core:GLA } { sdram_we_pad_o }" >> $@
|
| 449 |
|
|
$(Q) echo "set_output_delay -max "$(SDRAM_OUT_DELAY)" -clock { clkgen0/pll0/Core:GLA } { sdram_a_pad_o[*] }" >> $@
|
| 450 |
|
|
$(Q) echo "set_output_delay -max "$(SDRAM_OUT_DELAY)" -clock { clkgen0/pll0/Core:GLA } { sdram_ba_pad_o[*] }" >> $@
|
| 451 |
|
|
$(Q) echo "set_output_delay -max "$(SDRAM_OUT_DELAY)" -clock { clkgen0/pll0/Core:GLA } { sdram_cke_pad_o }" >> $@
|
| 452 |
|
|
$(Q) echo "set_output_delay -max "$(SDRAM_OUT_DELAY)" -clock { clkgen0/pll0/Core:GLA } { sdram_dqm_pad_o[*] }" >> $@
|
| 453 |
|
|
$(Q)echo >> $@
|
| 454 |
|
|
|
| 455 |
|
|
# $(Q) echo "######## Generated Clock Constraints ########" >> $@
|
| 456 |
|
|
# $(Q) echo "create_generated_clock -name { clkgen0/pll0/Core:GLA } -divide_by 36 -multiply_by 36 -source { clkgen0/pll0/Core:CLKA } { clkgen0/pll0/Core:GLA } " >> $@
|
| 457 |
|
|
# $(Q) echo "create_generated_clock -name { clkgen0/pll0/Core:GLB } -divide_by "$(WB_SDC_GENCLK_DIVIDE_BY)" -multiply_by "$(WB_SDC_GENCLK_MULTIPLY_BY)" -source { clkgen0/pll0/Core:CLKA } { clkgen0/pll0/Core:GLB } " >> $@
|
| 458 |
|
|
|
| 459 |
|
|
#
|
| 460 |
|
|
# Physical design constraints
|
| 461 |
|
|
#
|
| 462 |
|
|
|
| 463 |
|
|
# Pin settings, based on CPU board
|
| 464 |
|
|
PDC_MKPINS_PATH ?=../bin
|
| 465 |
|
|
PDC_MKPINASSIGNS_PATH ?=../bin
|
| 466 |
|
|
|
| 467 |
|
|
# Default board config
|
| 468 |
|
|
BOARD_CONFIG ?= orsoccpuexpio.mkpinassigns
|
| 469 |
|
|
|
| 470 |
|
|
include $(PDC_MKPINASSIGNS_PATH)/$(BOARD_CONFIG)
|
| 471 |
|
|
|
| 472 |
|
|
# PDC file generation - depending on Verilog defines file, we generate right PDC
|
| 473 |
|
|
|
| 474 |
|
|
pdc-file:
|
| 475 |
|
|
$(Q)for define in $(DESIGN_DEFINES); do export $$define=1; done; \
|
| 476 |
|
|
$(MAKE) $(PDC_FILE)
|
| 477 |
|
|
|
| 478 |
|
|
# To do - somehow figure out the top-level signals in the design, and then
|
| 479 |
|
|
# auto-generate this rule....?!
|
| 480 |
|
|
$(PDC_FILE): $(PROJECT_VERILOG_DEFINES)
|
| 481 |
|
|
$(Q)echo; echo "\t### Generating PDC file ###"; echo
|
| 482 |
|
|
$(Q)touch $@
|
| 483 |
|
|
$(Q)echo "#" >> $@
|
| 484 |
|
|
$(Q)echo "# IO banks setting" >> $@
|
| 485 |
|
|
$(Q)echo "#" >> $@
|
| 486 |
|
|
$(Q)echo "" >> $@
|
| 487 |
|
|
$(Q)if [ \"$(FPGA_FAMILY)\" = \"ProASIC3E\" ]; then \
|
| 488 |
|
|
echo "set_iobank Bank7 -vcci 3.30 -fixed no" >> $@; \
|
| 489 |
|
|
echo "set_iobank Bank6 -vcci 3.30 -fixed no" >> $@; \
|
| 490 |
|
|
echo "set_iobank Bank5 -vcci 3.30 -fixed no" >> $@; \
|
| 491 |
|
|
echo "set_iobank Bank4 -vcci 3.30 -fixed no" >> $@; \
|
| 492 |
|
|
fi
|
| 493 |
|
|
$(Q)echo "set_iobank Bank3 -vcci 3.30 -fixed no" >> $@
|
| 494 |
|
|
$(Q)echo "set_iobank Bank2 -vcci 3.30 -fixed no" >> $@
|
| 495 |
|
|
$(Q)echo "set_iobank Bank1 -vcci 3.30 -fixed no" >> $@
|
| 496 |
|
|
$(Q)echo "set_iobank Bank0 -vcci 3.30 -fixed no" >> $@
|
| 497 |
|
|
$(Q)echo "" >> $@
|
| 498 |
|
|
$(Q)echo "#" >> $@
|
| 499 |
|
|
$(Q)echo "# I/O constraints" >> $@
|
| 500 |
|
|
$(Q)echo "#" >> $@
|
| 501 |
|
|
$(Q)echo "" >> $@
|
| 502 |
|
|
$(Q)echo "set_io rst_n_pad_i "$(RST_BUS_SETTING) " -pinname "$(RST_PIN) >> $@
|
| 503 |
|
|
$(Q)echo "set_io sys_clk_pad_i "$(CLK_BUS_SETTING) " -pinname "$(CLK_PIN) >> $@
|
| 504 |
|
|
$(Q)if [ ! -z $$JTAG_DEBUG ]; then \
|
| 505 |
|
|
echo "set_io tck_pad_i "$(JTAG_DBG_SETTINGS)" -pinname "$(JTAG_DBG_TCK_PIN) >>$@; \
|
| 506 |
|
|
echo "set_io tdi_pad_i "$(JTAG_DBG_SETTINGS)" -pinname "$(JTAG_DBG_TDI_PIN) >>$@; \
|
| 507 |
|
|
echo "set_io tdo_pad_o "$(JTAG_DBG_SETTINGS)" -pinname "$(JTAG_DBG_TDO_PIN) >>$@; \
|
| 508 |
|
|
echo "set_io tms_pad_i "$(JTAG_DBG_SETTINGS)" -pinname "$(JTAG_DBG_TMS_PIN) >>$@; \
|
| 509 |
|
|
fi
|
| 510 |
|
|
$(Q)if [ ! -z $$GPIO0 ]; then \
|
| 511 |
|
|
echo "set_io gpio0_io\\[0\\] " $(GPIO_BUS_SETTINGS) " -pinname "$(GPIO0_PIN) >> $@; \
|
| 512 |
|
|
echo "set_io gpio0_io\\[1\\] " $(GPIO_BUS_SETTINGS) " -pinname "$(GPIO1_PIN) >> $@; \
|
| 513 |
|
|
echo "set_io gpio0_io\\[2\\] " $(GPIO_BUS_SETTINGS) " -pinname "$(GPIO2_PIN) >> $@; \
|
| 514 |
|
|
echo "set_io gpio0_io\\[3\\] " $(GPIO_BUS_SETTINGS) " -pinname "$(GPIO3_PIN) >> $@; \
|
| 515 |
|
|
echo "set_io gpio0_io\\[4\\] " $(GPIO_BUS_SETTINGS) " -pinname "$(GPIO4_PIN) >> $@; \
|
| 516 |
|
|
echo "set_io gpio0_io\\[5\\] " $(GPIO_BUS_SETTINGS) " -pinname "$(GPIO5_PIN) >> $@; \
|
| 517 |
|
|
echo "set_io gpio0_io\\[6\\] " $(GPIO_BUS_SETTINGS) " -pinname "$(GPIO6_PIN) >> $@; \
|
| 518 |
|
|
echo "set_io gpio0_io\\[7\\] " $(GPIO_BUS_SETTINGS) " -pinname "$(GPIO7_PIN) >> $@; \
|
| 519 |
|
|
fi
|
| 520 |
|
|
$(Q)if [ ! -z $$I2C0 ]; then \
|
| 521 |
|
|
echo "set_io i2c0_scl_io " $(I2C_BUS_SETTINGS) " -pinname "$(I2C_0_SCL_PIN) >> $@; \
|
| 522 |
|
|
echo "set_io i2c0_sda_io " $(I2C_BUS_SETTINGS) " -pinname "$(I2C_0_SDA_PIN) >> $@; \
|
| 523 |
|
|
fi
|
| 524 |
|
|
$(Q)if [ ! -z $$I2C1 ]; then \
|
| 525 |
|
|
echo "set_io i2c1_scl_io " $(I2C_BUS_SETTINGS) " -pinname "$(I2C_1_SCL_PIN) >> $@; \
|
| 526 |
|
|
echo "set_io i2c1_sda_io " $(I2C_BUS_SETTINGS) " -pinname "$(I2C_1_SDA_PIN) >> $@; \
|
| 527 |
|
|
fi
|
| 528 |
|
|
$(Q)if [ ! -z $$I2C2 ]; then \
|
| 529 |
|
|
echo "set_io i2c2_scl_io " $(I2C_BUS_SETTINGS) " -pinname "$(I2C_2_SCL_PIN) >> $@; \
|
| 530 |
|
|
echo "set_io i2c2_sda_io " $(I2C_BUS_SETTINGS) " -pinname "$(I2C_2_SDA_PIN) >> $@; \
|
| 531 |
|
|
fi
|
| 532 |
|
|
$(Q)if [ ! -z $$I2C3 ]; then \
|
| 533 |
|
|
echo "set_io i2c3_scl_io " $(I2C_BUS_SETTINGS) " -pinname "$(I2C_3_SCL_PIN) >> $@; \
|
| 534 |
|
|
echo "set_io i2c3_sda_io " $(I2C_BUS_SETTINGS) " -pinname "$(I2C_3_SDA_PIN) >> $@; \
|
| 535 |
|
|
fi
|
| 536 |
|
|
$(Q)if [ ! -z $$MP2_0 ]; then \
|
| 537 |
|
|
echo "set_io mp2_0_i -pinname "$(MP2_0_I_PIN) >> $@; \
|
| 538 |
|
|
echo "set_io mp2_0_o -pinname "$(MP2_0_O_PIN) >> $@; \
|
| 539 |
|
|
fi
|
| 540 |
|
|
$(Q)if [ ! -z $$MP2_1 ]; then \
|
| 541 |
|
|
echo "set_io mp2_1_i -pinname "$(MP2_1_I_PIN) >> $@; \
|
| 542 |
|
|
echo "set_io mp2_1_o -pinname "$(MP2_1_O_PIN) >> $@; \
|
| 543 |
|
|
fi
|
| 544 |
|
|
$(Q)if [ ! -z $$VERSATILE_SDRAM ]; then \
|
| 545 |
|
|
echo "set_io sdram_a_pad_o\\[0\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A0_PIN) >> $@; \
|
| 546 |
|
|
echo "set_io sdram_a_pad_o\\[1\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A1_PIN) >> $@; \
|
| 547 |
|
|
echo "set_io sdram_a_pad_o\\[2\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A2_PIN) >> $@; \
|
| 548 |
|
|
echo "set_io sdram_a_pad_o\\[3\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A3_PIN) >> $@; \
|
| 549 |
|
|
echo "set_io sdram_a_pad_o\\[4\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A4_PIN) >> $@; \
|
| 550 |
|
|
echo "set_io sdram_a_pad_o\\[5\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A5_PIN) >> $@; \
|
| 551 |
|
|
echo "set_io sdram_a_pad_o\\[6\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A6_PIN) >> $@; \
|
| 552 |
|
|
echo "set_io sdram_a_pad_o\\[7\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A7_PIN) >> $@; \
|
| 553 |
|
|
echo "set_io sdram_a_pad_o\\[8\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A8_PIN) >> $@; \
|
| 554 |
|
|
echo "set_io sdram_a_pad_o\\[9\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A9_PIN) >> $@; \
|
| 555 |
|
|
echo "set_io sdram_a_pad_o\\[10\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A10_PIN) >> $@; \
|
| 556 |
|
|
echo "set_io sdram_a_pad_o\\[11\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A11_PIN) >> $@; \
|
| 557 |
|
|
echo "set_io sdram_a_pad_o\\[12\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A12_PIN) >> $@; \
|
| 558 |
|
|
echo "set_io sdram_ba_pad_o\\[0\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A13_PIN) >> $@; \
|
| 559 |
|
|
echo "set_io sdram_ba_pad_o\\[1\\] "$(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_A14_PIN) >> $@; \
|
| 560 |
|
|
echo "set_io sdram_ras_pad_o " $(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_RAS_PIN) >> $@; \
|
| 561 |
|
|
echo "set_io sdram_cas_pad_o " $(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_CAS_PIN) >> $@; \
|
| 562 |
|
|
echo "set_io sdram_we_pad_o " $(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_WE_PIN) >> $@; \
|
| 563 |
|
|
echo "set_io sdram_cke_pad_o " $(SDRAM_CTRL_BUS_SETTINGS_NO_REG)" -pinname "$(SDRAM_CKE_PIN) >> $@; \
|
| 564 |
|
|
echo "set_io sdram_cs_n_pad_o" $(SDRAM_CTRL_BUS_SETTINGS_NO_REG)" -pinname "$(SDRAM_CS_PIN) >> $@; \
|
| 565 |
|
|
echo "set_io sdram_dqm_pad_o\\[0\\] " $(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_DQM0_PIN) >> $@; \
|
| 566 |
|
|
echo "set_io sdram_dqm_pad_o\\[1\\] " $(SDRAM_CTRL_BUS_SETTINGS)" -pinname "$(SDRAM_DQM1_PIN) >> $@; \
|
| 567 |
|
|
echo "set_io sdram_dq_pad_io\\[0\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ0_PIN) >> $@; \
|
| 568 |
|
|
echo "set_io sdram_dq_pad_io\\[1\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ1_PIN) >> $@; \
|
| 569 |
|
|
echo "set_io sdram_dq_pad_io\\[2\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ2_PIN) >> $@; \
|
| 570 |
|
|
echo "set_io sdram_dq_pad_io\\[3\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ3_PIN) >> $@; \
|
| 571 |
|
|
echo "set_io sdram_dq_pad_io\\[4\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ4_PIN) >> $@; \
|
| 572 |
|
|
echo "set_io sdram_dq_pad_io\\[5\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ5_PIN) >> $@; \
|
| 573 |
|
|
echo "set_io sdram_dq_pad_io\\[6\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ6_PIN) >> $@; \
|
| 574 |
|
|
echo "set_io sdram_dq_pad_io\\[7\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ7_PIN) >> $@; \
|
| 575 |
|
|
echo "set_io sdram_dq_pad_io\\[8\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ8_PIN) >> $@; \
|
| 576 |
|
|
echo "set_io sdram_dq_pad_io\\[9\\] " $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ9_PIN) >> $@; \
|
| 577 |
|
|
echo "set_io sdram_dq_pad_io\\[10\\]" $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ10_PIN) >> $@; \
|
| 578 |
|
|
echo "set_io sdram_dq_pad_io\\[11\\]" $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ11_PIN) >> $@; \
|
| 579 |
|
|
echo "set_io sdram_dq_pad_io\\[12\\]" $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ12_PIN) >> $@; \
|
| 580 |
|
|
echo "set_io sdram_dq_pad_io\\[13\\]" $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ13_PIN) >> $@; \
|
| 581 |
|
|
echo "set_io sdram_dq_pad_io\\[14\\]" $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ14_PIN) >> $@; \
|
| 582 |
|
|
echo "set_io sdram_dq_pad_io\\[15\\]" $(SDRAM_DATA_BUS_SETTINGS)" -pinname "$(SDRAM_DQ15_PIN) >> $@; \
|
| 583 |
|
|
fi
|
| 584 |
|
|
$(Q)if [ ! -z $$SPI0 ]; then \
|
| 585 |
|
|
echo "set_io spi0_miso_i "$(SPI_BUS_SETTINGS)" -pinname "$(SPI0_MISO_PIN) >> $@; \
|
| 586 |
|
|
echo "set_io spi0_mosi_o "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI0_MOSI_PIN) >> $@; \
|
| 587 |
|
|
echo "set_io spi0_sck_o "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI0_SCK_PIN) >> $@; \
|
| 588 |
|
|
echo "set_io spi0_hold_n_o "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI0_HOLD_N_PIN) >> $@; \
|
| 589 |
|
|
echo "set_io spi0_w_n_o "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI0_W_N_PIN) >> $@; \
|
| 590 |
|
|
fi
|
| 591 |
|
|
$(Q)if [ ! -z $$SPI0_SLAVE_SELECTS ]; then \
|
| 592 |
|
|
echo "set_io spi0_ss_o\\[0\\] "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI0_SS0_PIN) >> $@; \
|
| 593 |
|
|
fi
|
| 594 |
|
|
$(Q)if [ ! -z $$SPI1 ]; then \
|
| 595 |
|
|
echo "set_io spi1_miso_i "$(SPI_BUS_SETTINGS)" -pinname "$(SPI1_MISO_PIN) >> $@; \
|
| 596 |
|
|
echo "set_io spi1_mosi_o "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI1_MOSI_PIN) >> $@; \
|
| 597 |
|
|
echo "set_io spi1_sck_o "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI1_SCK_PIN) >> $@; \
|
| 598 |
|
|
if [ ! -z $$SPI1_SLAVE_SELECTS ]; then \
|
| 599 |
|
|
echo "set_io spi1_ss_o\\[0\\] "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI1_SS0_PIN) >> $@; \
|
| 600 |
|
|
fi; \
|
| 601 |
|
|
fi
|
| 602 |
|
|
$(Q)if [ ! -z $$SPI2 ]; then \
|
| 603 |
|
|
echo "set_io spi2_miso_i "$(SPI_BUS_SETTINGS)" -pinname "$(SPI2_MISO_PIN) >> $@; \
|
| 604 |
|
|
echo "set_io spi2_mosi_o "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI2_MOSI_PIN) >> $@; \
|
| 605 |
|
|
echo "set_io spi2_sck_o "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI2_SCK_PIN) >> $@; \
|
| 606 |
|
|
if [ ! -z $$SPI2_SLAVE_SELECTS ]; then \
|
| 607 |
|
|
echo "set_io spi2_ss_o\\[0\\] "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI2_SS0_PIN) >> $@; \
|
| 608 |
|
|
fi; \
|
| 609 |
|
|
fi
|
| 610 |
|
|
$(Q)if [ ! -z $$SPW0 ]; then \
|
| 611 |
|
|
echo "set_io spw0_rx_d "$(SPW_RX_BUS_SETTINGS)" -pinname "$(SPW0_RX_D_PIN) >> $@; \
|
| 612 |
|
|
echo "set_io spw0_rx_s "$(SPW_RX_BUS_SETTINGS)" -pinname "$(SPW0_RX_S_PIN) >> $@; \
|
| 613 |
|
|
echo "set_io spw0_tx_d "$(SPW_TX_BUS_SETTINGS)" -pinname "$(SPW0_TX_D_PIN) >> $@; \
|
| 614 |
|
|
echo "set_io spw0_tx_s "$(SPW_TX_BUS_SETTINGS)" -pinname "$(SPW0_TX_S_PIN) >> $@; \
|
| 615 |
|
|
fi
|
| 616 |
|
|
$(Q)if [ ! -z $$UART0 ]; then \
|
| 617 |
|
|
echo "set_io uart0_srx_pad_i "$(UART_RX_BUS_SETTINGS)" -pinname "$(UART0_RX_PIN) >> $@; \
|
| 618 |
|
|
echo "set_io uart0_stx_pad_o "$(UART_TX_BUS_SETTINGS)" -pinname "$(UART0_TX_PIN) >> $@; \
|
| 619 |
|
|
fi
|
| 620 |
|
|
$(Q)if [ ! -z $$UART1 ]; then \
|
| 621 |
|
|
echo "set_io uart1_srx_pad_i "$(UART_RX_BUS_SETTINGS)" -pinname "$(UART1_RX_PIN) >> $@; \
|
| 622 |
|
|
echo "set_io uart1_stx_pad_o "$(UART_TX_BUS_SETTINGS)" -pinname "$(UART1_TX_PIN) >> $@; \
|
| 623 |
|
|
if [ ! -z $$UART1_PPS ]; then \
|
| 624 |
|
|
echo "set_io uart1_pps_pad_i "$(UART_RX_BUS_SETTINGS)" -pinname "$(UART1_PPS_PIN) >> $@; \
|
| 625 |
|
|
fi; \
|
| 626 |
|
|
fi
|
| 627 |
|
|
$(Q)if [ ! -z $$UART2 ]; then \
|
| 628 |
|
|
echo "set_io uart2_srx_pad_i "$(UART_RX_BUS_SETTINGS)" -pinname "$(UART2_RX_PIN) >> $@; \
|
| 629 |
|
|
echo "set_io uart2_stx_pad_o "$(UART_TX_BUS_SETTINGS)" -pinname "$(UART2_TX_PIN) >> $@; \
|
| 630 |
|
|
if [ ! -z $$UART2_PPS ]; then \
|
| 631 |
|
|
echo "set_io uart2_pps_pad_i "$(UART_RX_BUS_SETTINGS)" -pinname "$(UART2_PPS_PIN) >> $@; \
|
| 632 |
|
|
fi; \
|
| 633 |
|
|
fi
|
| 634 |
|
|
$(Q)if [ ! -z $$USB0 ]; then \
|
| 635 |
|
|
echo "set_io usb0fullspeed_pad_o "$(USB_TX_BUS_SETTINGS)" -pinname "$(USB0_FULLSPEED) >> $@; \
|
| 636 |
|
|
echo "set_io usb0ctrl_pad_o "$(USB_TX_BUS_SETTINGS)" -pinname "$(USB0_WIRECTRLOUT) >> $@; \
|
| 637 |
|
|
echo "set_io usb0dat_pad_i\\[0\\] "$(USB_RX_DATA_SETTINGS)" -pinname "$(USB0_DATAIN0) >> $@; \
|
| 638 |
|
|
echo "set_io usb0dat_pad_i\\[1\\] "$(USB_RX_DATA_SETTINGS)" -pinname "$(USB0_DATAIN1) >> $@; \
|
| 639 |
|
|
echo "set_io usb0dat_pad_o\\[0\\] "$(USB_TX_DATA_SETTINGS)" -pinname "$(USB0_DATAOUT0) >> $@; \
|
| 640 |
|
|
echo "set_io usb0dat_pad_o\\[1\\] "$(USB_TX_DATA_SETTINGS)" -pinname "$(USB0_DATAOUT1) >> $@; \
|
| 641 |
|
|
fi
|
| 642 |
|
|
$(Q)if [ ! -z $$USB1 ]; then \
|
| 643 |
|
|
echo "set_io usb1fullspeed_pad_o "$(USB_TX_BUS_SETTINGS)" -pinname "$(USB1_FULLSPEED) >> $@; \
|
| 644 |
|
|
echo "set_io usb1ctrl_pad_o "$(USB_TX_BUS_SETTINGS)" -pinname "$(USB1_WIRECTRLOUT) >> $@; \
|
| 645 |
|
|
echo "set_io usb1dat_pad_i\\[0\\] "$(USB_RX_DATA_SETTINGS)" -pinname "$(USB1_DATAIN0) >> $@; \
|
| 646 |
|
|
echo "set_io usb1dat_pad_i\\[1\\] "$(USB_RX_DATA_SETTINGS)" -pinname "$(USB1_DATAIN1) >> $@; \
|
| 647 |
|
|
echo "set_io usb1dat_pad_o\\[0\\] "$(USB_TX_DATA_SETTINGS)" -pinname "$(USB1_DATAOUT0) >> $@; \
|
| 648 |
|
|
echo "set_io usb1dat_pad_o\\[1\\] "$(USB_TX_DATA_SETTINGS)" -pinname "$(USB1_DATAOUT1) >> $@; \
|
| 649 |
|
|
fi
|
| 650 |
|
|
$(Q)if [ ! -z $$ETH_CLK ]; then \
|
| 651 |
|
|
echo "set_io eth_clk_pad_i "$(ETHERNET_BUS_SETTINGS)" -REGISTER No -pinname "$(ETH_CLK_PIN) >> $@; \
|
| 652 |
|
|
fi
|
| 653 |
|
|
$(Q)if [ ! -z $$ETH0 ]; then \
|
| 654 |
|
|
echo "set_io eth0_md_pad_io "$(ETHERNET_BUS_SETTINGS)" -pinname "$(ETH0_MDIO_PIN) >> $@; \
|
| 655 |
|
|
echo "set_io eth0_mdc_pad_o "$(ETHERNET_BUS_SETTINGS)" "$(ETHERNET_OUT_BUS_SETTINGS)" -pinname "$(ETH0_MDC_PIN) >> $@; \
|
| 656 |
|
|
echo "set_io eth0_smii_rx_pad_i "$(ETHERNET_BUS_SETTINGS)" -REGISTER Yes -pinname "$(ETH0_SMII_RX_PIN) >> $@; \
|
| 657 |
|
|
echo "set_io eth0_smii_sync_pad_o "$(ETHERNET_BUS_SETTINGS)" "$(ETHERNET_OUT_REG_BUS_SETTINGS)" -pinname "$(ETH0_SMII_SYNC_PIN) >> $@; \
|
| 658 |
|
|
echo "set_io eth0_smii_tx_pad_o "$(ETHERNET_BUS_SETTINGS)" "$(ETHERNET_OUT_REG_BUS_SETTINGS)" -pinname "$(ETH0_SMII_TX_PIN) >> $@; \
|
| 659 |
|
|
if [ ! -z $$ETH0_PHY_RST ]; then \
|
| 660 |
|
|
echo "set_io eth0_rst_n_o "$(RST_BUS_SETTING)" -pinname "$(ETH0_PHY_RSTN_PIN) >> $@; \
|
| 661 |
|
|
fi; \
|
| 662 |
|
|
fi
|
| 663 |
|
|
$(Q)echo "" >> $@
|
| 664 |
|
|
|
| 665 |
|
|
|
| 666 |
|
|
# Removed due to SPI slave selects numbering only 1
|
| 667 |
|
|
# echo "set_io spi1_ss_o\\[1\\] "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI1_SS1_PIN) >> $@;
|
| 668 |
|
|
# echo "set_io spi1_ss_o\\[2\\] "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI1_SS2_PIN) >> $@; \
|
| 669 |
|
|
# echo "set_io spi2_ss_o\\[1\\] "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI2_SS1_PIN) >> $@; \
|
| 670 |
|
|
# echo "set_io spi2_ss_o\\[2\\] "$(SPI_BUS_SETTINGS)" "$(SPI_BUS_OUT_SETTINGS)" -pinname "$(SPI2_SS2_PIN) >> $@; \
|
| 671 |
|
|
|
