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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [backend/] [rtl/] [verilog/] [README] - Blame information for rev 650

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Actel Verilog RTL files
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The files in this directory are Actel specific RTL
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These are all, at present, wrappers for Actel primitives. Most, if not all, were
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generated with Actel's smartgen tool
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eth_pll.v:
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                 PLL for the 125MHz ethernet clock on the ORDB1 with as little
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                 insertion delay as possible.
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gbuf.v:
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                 Buffer for clocks (used in clkgen module)
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pll_xtalXX_wbYY:
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                PLL taking external oscillator at XX MHz and generating Wishbone
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                clock at frequency YY.
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reset_buffer.v:
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                Buffer for reset (used in clkgen module)
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orpsoc_flashROM.v:
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                Instantiation of UFR.

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