OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [backend/] [rtl/] [verilog/] [orpsoc_flashROM.v] - Blame information for rev 650

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius
`timescale 1 ns/100 ps
2
// Version: 8.6 8.6.0.34
3
 
4
 
5
module orpsoc_flashROM(CLK,ADDR,DOUT);
6
input CLK;
7
input [6:0] ADDR;
8
output [7:0] DOUT;
9
 
10
    wire U_7_PIN2;
11
 
12
    GND GND_1_net(.Y(U_7_PIN2));
13
    UFROMH #( .MEMORYFILE("devboard_flashROM.mem"), .ACT_PROGFILE("devboard_flashROM.ufc")
14
         )  UFROM0(.CLK(CLK), .DO0(DOUT[0]), .DO1(DOUT[1]), .DO2(
15
        DOUT[2]), .DO3(DOUT[3]), .DO4(DOUT[4]), .DO5(DOUT[5]),
16
        .DO6(DOUT[6]), .DO7(DOUT[7]), .ADDR0(ADDR[0]), .ADDR1(
17
        ADDR[1]), .ADDR2(ADDR[2]), .ADDR3(ADDR[3]), .ADDR4(
18
        ADDR[4]), .ADDR5(ADDR[5]), .ADDR6(ADDR[6]));
19
 
20
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.