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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [backend/] [rtl/] [verilog/] [reset_buffer.v] - Blame information for rev 408

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Line No. Rev Author Line
1 408 julius
`timescale 1 ns/100 ps
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// Version: 8.6 8.6.0.34
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module reset_buffer(GL,CLK);
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output GL;
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input  CLK;
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    wire CLKP, GND;
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    GND GND_1_net(.Y(GND));
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    PLLINT pllint1(.A(CLK), .Y(CLKP));
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    CLKDLY Inst1(.CLK(CLKP), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
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        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND));
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endmodule

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