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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [bench/] [verilog/] [include/] [eth_stim.v] - Blame information for rev 530

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1 408 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Ethernet MAC Stimulus                                       ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Ethernet MAC stimulus tasks. Taken from the project         ////
7
////  testbench in the ethmac core.                               ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////                                                              ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Tadej Markovic, tadej@opencores.org                   ////
14
////      - Igor Mohor,     igorM@opencores.org                   ////
15
////      - Julius Baxter   julius.baxter@orsoc.se                ////
16
////                                                              ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
`define TIME $display("Time: %0t", $time)
45
 
46
// Defines for ethernet test to trigger sending/receiving
47
// Is straight forward when using RTL design, but if using netlist then paths to
48
// the RX/TX enabled bits depend on synthesis tool, etc, but ones here appear to
49
// work with design put through Synplify, with hierarchy maintained.
50 409 julius
`define ETH_TOP dut.ethmac0
51 408 julius
`define ETH_BD_RAM_PATH `ETH_TOP.wishbone.bd_ram
52
`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0
53
 
54
`ifdef RTL_SIM
55 411 julius
 `ifdef ethmac_IS_GATELEVEL
56 408 julius
  `define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
57
  `define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
58
 `else
59
  `define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.DataOut[1];
60
  `define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.DataOut[0];
61
 `endif
62
`endif
63
 
64
`ifdef GATE_SIM
65
 `define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
66
 `define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
67
`endif
68
 
69
reg [15:0] eth_stim_rx_packet_length;
70
reg [7:0] st_data;
71
reg [31:0] lfsr;
72
integer lfsr_last_byte;
73
 
74
// Is number of ethernet packets to send if doing the eth-rx test.
75 411 julius
parameter eth_stim_num_rx_only_num_packets = 500; // Set to 0 for continuous RX
76
parameter eth_stim_num_rx_only_packet_size = 512;
77
parameter eth_stim_num_rx_only_packet_size_change = 2'b01;  // 2'b01: Increment
78
parameter eth_stim_num_rx_only_packet_size_change_amount = 1;
79
parameter eth_stim_num_rx_only_IPG = 800000; // ns
80 408 julius
 
81 411 julius
// Do call/response test
82
reg eth_stim_do_rx_reponse_to_tx;
83 530 julius
reg eth_stim_do_overflow_test;
84 411 julius
 
85 408 julius
 
86
parameter num_tx_bds = 16;
87
parameter num_tx_bds_mask = 4'hf;
88
parameter num_rx_bds = 16;
89
parameter num_rx_bds_mask = 4'hf;
90
parameter max_eth_packet_size = 16'h0600;
91 411 julius
 
92 408 julius
// If running eth-rxtxbig test (sending and receiving maximum packets), then
93
// set this parameter to the max packet size, otherwise min packet size
94
//parameter rx_while_tx_min_packet_size = max_eth_packet_size;
95
parameter rx_while_tx_min_packet_size = 32;
96
 
97
// Use the smallest possible IPG
98
parameter eth_stim_use_min_IPG = 0;
99
parameter eth_stim_IPG_delay_max = 500_000; // Maximum 500uS ga
100
//parameter eth_stim_IPG_delay_max = 100_000_000; // Maximum 100mS between packets
101
parameter eth_stim_IPG_min_10mb = 9600; // 9.6 uS
102
parameter eth_stim_IPG_min_100mb = 800; // 860+~100 = 960 nS 100MBit min IPG
103
parameter eth_stim_check_rx_packet_contents = 1;
104
parameter eth_stim_check_tx_packet_contents = 1;
105
 
106
parameter eth_inject_errors = 0;
107
 
108
// When running simulations where you don't want to feed packets to the design
109
// like this...
110
parameter eth_stim_disable_rx_stim = 0;
111
 
112
// Delay between seeing that the buffer descriptor for an RX packet says it's
113
// been received and ending up in the memory.
114
// For 25MHz sdram controller, use following:
115
//parameter  Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 2000);
116
// For 64MHz sdram controller, use following:
117
parameter  Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 500);
118
 
119
 
120
 
121
integer expected_rxbd;// init to 0
122
integer expected_txbd;
123
 
124
wire ethmac_rxen;
125
wire ethmac_txen;
126
assign ethmac_rxen = eth_stim_disable_rx_stim ? 0 : `ETH_MODER_RXEN_BIT;
127
assign ethmac_txen = `ETH_MODER_TXEN_BIT;
128
 
129
integer eth_rx_num_packets_sent = 0;
130
integer eth_rx_num_packets_checked = 0;
131
integer num_tx_packets = 1;
132
 
133
integer rx_packet_lengths [0:1023]; // Array of packet lengths
134
 
135
 
136
integer speed_loop;
137
 
138
// When txen is (re)enabled, the tx bd pointer goes back to 0
139
always @(posedge ethmac_txen)
140
  expected_txbd = 0;
141
 
142
   reg  eth_stim_waiting;
143
 
144
initial
145
  begin
146
     #1;
147
     //lfsr = 32'h84218421; // Init pseudo lfsr
148
     lfsr = 32'h00700001; // Init pseudo lfsr
149
     lfsr_last_byte = 0;
150
 
151
     eth_stim_waiting = 1;
152 411 julius
     expected_rxbd = num_tx_bds; // init this here
153
 
154
     eth_stim_do_rx_reponse_to_tx = 0;
155 530 julius
     eth_stim_do_overflow_test = 0;
156 408 julius
 
157 411 julius
 
158 408 julius
     while (eth_stim_waiting) // Loop, waiting for enabling of MAC by software
159
       begin
160
          #100;
161
          // If RX enable and not TX enable...
162
          if(ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
163
            begin
164
               if (eth_inject_errors)
165
                 begin
166 411 julius
                    do_rx_only_stim(16, 64, 0, 0);
167
                    do_rx_only_stim(128, 64, 1'b1, 8);
168
                    do_rx_only_stim(256, 64, 1'b1, 4);
169 408 julius
                    eth_stim_waiting = 0;
170
                 end
171
               else
172
                 begin
173 411 julius
                    //do_rx_only_stim(eth_stim_num_rx_only_num_packets, 
174
                    //eth_stim_num_rx_only_packet_size, 0, 0);
175
 
176
                    // Call packet send loop directly. No error injection.
177
                    send_packet_loop(eth_stim_num_rx_only_num_packets,
178
                                     eth_stim_num_rx_only_packet_size,
179
                                     eth_stim_num_rx_only_packet_size_change,
180
                                     eth_stim_num_rx_only_packet_size_change_amount,
181
                                     eth_phy0.eth_speed,     // Speed
182
                                     eth_stim_num_rx_only_IPG, // IPG
183
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
184 530 julius
                               0, 0, 0);
185 411 julius
 
186 408 julius
                    eth_stim_waiting = 0;
187
                 end
188
            end // if (ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
189
          // If both RX and TX enabled
190
          else if (ethmac_rxen === 1'b1 & ethmac_txen===1'b1)
191
            begin
192 411 julius
               // Both enabled - let's wait for the first packet transmitted
193
               // to see what stimulus we should provide
194
               while (num_tx_packets==1)
195
                 #1000;
196
 
197
               $display("* ethmac RX/TX test request: %x", eth_phy0.tx_mem[0]);
198
 
199
               // Check the first received byte's value
200
                 case (eth_phy0.tx_mem[0])
201
                   0:
202
                     begin
203
                        // kickoff call/response here
204
                        eth_stim_do_rx_reponse_to_tx = 1;
205
                     end
206 530 julius
                   1:
207
                     begin
208
                        // kickoff overflow test here
209
                        eth_stim_do_overflow_test = 1;
210
                     end
211 411 julius
                   default:
212
                     begin
213
                        do_rx_while_tx_stim(1400);
214
                     end
215
                 endcase // case (eth_phy0.tx_mem[0])
216
 
217 408 julius
               eth_stim_waiting = 0;
218
            end
219
       end // while (eth_stim_waiting)     
220
 
221
  end // initial begin
222
 
223
   // Main Ethernet RX testing stimulus task.
224
   // Sends a set of packets at both speeds
225
   task do_rx_only_stim;
226
      input [31:0] num_packets;
227 411 julius
      input [31:0] start_packet_size;
228 408 julius
      input        inject_errors;
229
      input [31:0] inject_errors_mod;
230
 
231
      begin
232
 
233
         for(speed_loop=1;speed_loop<3;speed_loop=speed_loop+1)
234
           begin
235
 
236 411 julius
              send_packet_loop(num_packets, start_packet_size, 2'b01, 1,
237
                               speed_loop[0], 10000,
238 408 julius
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
239 530 julius
                               inject_errors, inject_errors_mod, 0);
240 408 julius
 
241
           end
242
 
243
      end
244
   endtask // do_rx_stim
245
 
246
   // Generate RX packets while there's TX going on
247
   // Sends a set of packets at both speeds
248
   task do_rx_while_tx_stim;
249
      input [31:0] num_packets;
250
      reg [31:0] IPG; // Inter-packet gap
251
      reg [31:0] packet_size;
252
 
253
      integer    j;
254
      begin
255
 
256
         for(j=0;j<num_packets;j=j+1)
257
           begin
258
              // Determine delay between RX packets:
259
 
260
              if (eth_stim_use_min_IPG)
261
                begin
262
                   // Assign based on whether we're in 100mbit or 10mbit mode
263
                   IPG = eth_phy0.eth_speed ? eth_stim_IPG_min_100mb :
264
                         eth_stim_IPG_min_10mb;
265
                   // Add a little bit of variability
266
                   // Add up to 15
267
                   IPG = IPG + ($random & 32'h000000f);
268
                end
269
              else
270
                begin
271
                   IPG = $random;
272
 
273
                   while (IPG > eth_stim_IPG_delay_max)
274
                     IPG = IPG / 2;
275
 
276
 
277
                end
278
              $display("do_rx_while_tx IPG = %0d", IPG);
279
              // Determine size of next packet:
280
              if (rx_while_tx_min_packet_size == max_eth_packet_size)
281
                // We want to transmit biggest packets possible, easy case
282
                packet_size = max_eth_packet_size - 4;
283
              else
284
                begin
285
                   // Constrained random sized packets
286
                   packet_size = $random;
287
 
288
                   while (packet_size > (max_eth_packet_size-4))
289
                     packet_size = packet_size / 2;
290
 
291
                   // Now divide by least significant bits of j
292
                   packet_size = packet_size / {29'd0,j[1:0],1'b1};
293
                   if (packet_size < 60)
294
                     packet_size = packet_size + 60;
295
                end
296
 
297
              $display("do_rx_while_tx packet_size = %0d", packet_size);
298
              send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
299
                               IPG, 48'h0012_3456_789a,
300 530 julius
                               48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
301 408 julius
 
302
              // If RX enable went low, wait for it go high again
303
              if (ethmac_rxen===1'b0)
304
                begin
305
 
306
                   while (ethmac_rxen===1'b0)
307
                     begin
308
                        @(posedge ethmac_rxen);
309
                        #10000;
310
                     end
311
 
312
                   // RX disabled and when re-enabled we reset the buffer descriptor number
313
                   expected_rxbd = num_tx_bds;
314
 
315
                end
316
 
317
           end // for (j=0;j<num_packets;j=j+1)
318
      end
319
   endtask // do_rx_stim
320
 
321 411 julius
   // Registers used in detecting transmitted packets
322
   reg eth_stim_tx_loop_keep_polling;
323
   reg [31:0] ethmac_txbd_lenstat, ethmac_last_txbd_lenstat;
324
   reg        eth_stim_detected_packet_tx;
325
 
326
   // If in call-response mode, whenever we receive a TX packet, we generate
327
   // one and send it back
328
   always @(negedge eth_stim_detected_packet_tx)
329
     begin
330
        if (eth_stim_do_rx_reponse_to_tx & ethmac_rxen)
331
          // Continue if we are enabled
332
          do_rx_response_to_tx();
333
     end
334 530 julius
 
335
   // If in call-response mode, whenever we receive a TX packet, we generate
336
   // one and send it back
337
   always @(posedge eth_stim_do_overflow_test)
338
     begin
339
          // Continue if we are enabled
340
          do_overflow_stimulus();
341
     end
342 411 julius
 
343
   // Generate RX packet in rsponse to TX packet
344
   task do_rx_response_to_tx;
345
      //input unused;
346
 
347
     reg [31:0] IPG; // Inter-packet gap
348
      reg [31:0] packet_size;
349
 
350
      integer    j;
351
      begin
352
 
353
         // Get packet size test wants us to send
354
         packet_size = {eth_phy0.tx_mem[0],eth_phy0.tx_mem[1],
355
                        eth_phy0.tx_mem[2],eth_phy0.tx_mem[3]};
356
 
357
 
358
         IPG = {eth_phy0.tx_mem[4],eth_phy0.tx_mem[5],
359
                eth_phy0.tx_mem[6],eth_phy0.tx_mem[7]};
360
 
361
 
362
         $display("do_rx_response_to_tx IPG = %0d", IPG);
363
         if (packet_size == 0)
364
           begin
365
              // Constrained random sized packets
366
              packet_size = $random;
367
 
368
              while (packet_size > (max_eth_packet_size-4))
369
                packet_size = packet_size / 2;
370
 
371
              if (packet_size < 60)
372
                packet_size = packet_size + 60;
373
           end
374
 
375
         $display("do_rx_response_to_tx packet_size = %0d", packet_size);
376
         send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
377
                          IPG, 48'h0012_3456_789a,
378 530 julius
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
379 411 julius
 
380
         // If RX enable went low, wait for it go high again
381
         if (ethmac_rxen===1'b0)
382
           begin
383
 
384
              while (ethmac_rxen===1'b0)
385
                begin
386
                   @(posedge ethmac_rxen);
387
                   #10000;
388
                end
389
 
390
              // RX disabled and when re-enabled we reset the buffer 
391
              // descriptor number
392
              expected_rxbd = num_tx_bds;
393
 
394
           end
395
 
396
      end
397
   endtask // do_rx_response_to_tx
398
 
399 530 julius
 
400
   // Generate RX packet in rsponse to TX packet
401
   task do_overflow_stimulus;
402
      //input unused;
403
      reg [31:0] IPG; // Inter-packet gap
404
      reg [31:0] packet_size;
405
 
406
      integer    j;
407
 
408
      begin
409
 
410
         // Maximum packet size
411
         packet_size = 1500;
412
 
413
         // Minimum IPG
414
         IPG = eth_stim_IPG_min_100mb;
415
 
416
         $display("do_overflow_stimulus IPG = %0d", IPG);
417
 
418
 
419
         $display("do_overflow_stimulus packetsize = %0d", packet_size);
420
 
421
         send_packet_loop(num_rx_bds, packet_size, 2'b01, 1,
422
                          eth_phy0.eth_speed,
423
                          IPG, 48'h0012_3456_789a,
424
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
425
 
426
         // This one should cause overflow, don't check it gets there OK
427
         send_packet_loop(1, packet_size, 2'b01, 1,
428
                          eth_phy0.eth_speed,
429
                          IPG, 48'h0012_3456_789a,
430
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
431
 
432
         // Wind back expected RXBD number
433
         if (expected_rxbd == num_tx_bds)
434
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
435
         else
436
           expected_rxbd = expected_rxbd - 1;
437
 
438
         // This one should cause overflow, don't check it gets there OK
439
         send_packet_loop(1, packet_size, 2'b01, 1,
440
                          eth_phy0.eth_speed,
441
                          IPG, 48'h0012_3456_789a,
442
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
443
 
444
         // Wind back expected RXBD number
445
         if (expected_rxbd == num_tx_bds)
446
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
447
         else
448
           expected_rxbd = expected_rxbd - 1;
449
 
450
 
451
         // This one should cause overflow, don't check it gets there OK
452
         send_packet_loop(1, packet_size, 2'b01, 1,
453
                          eth_phy0.eth_speed,
454
                          IPG, 48'h0012_3456_789a,
455
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
456
 
457
         // Wind back expected RXBD number
458
         if (expected_rxbd == num_tx_bds)
459
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
460
         else
461
           expected_rxbd = expected_rxbd - 1;
462
 
463
 
464
         // This one should cause overflow, don't check it gets there OK
465
         send_packet_loop(1, packet_size, 2'b01, 1,
466
                          eth_phy0.eth_speed,
467
                          IPG, 48'h0012_3456_789a,
468
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
469
 
470
         // Wind back expected RXBD number
471
         if (expected_rxbd == num_tx_bds)
472
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
473
         else
474
           expected_rxbd = expected_rxbd - 1;
475
 
476
 
477
         // Wait until a buffer descriptor becomes available
478
         while(`ETH_TOP.wishbone.RxBDRead==1'b1)
479
           #1000;
480
 
481
         $display("%t: RxBDRead gone low",$time);
482
         #10000;
483
 
484
 
485
 
486
         send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
487
                          IPG, 48'h0012_3456_789a,
488
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
489
 
490
 
491
         // If RX enable went low, wait for it go high again
492
         if (ethmac_rxen===1'b0)
493
           begin
494
 
495
              while (ethmac_rxen===1'b0)
496
                begin
497
                   @(posedge ethmac_rxen);
498
                   #10000;
499
                end
500
 
501
              // RX disabled and when re-enabled we reset the buffer 
502
              // descriptor number
503
              expected_rxbd = num_tx_bds;
504
 
505
           end
506
 
507
      end
508
   endtask // do_overflow_stimulus
509 411 julius
 
510 408 julius
   //
511
   // always@() to check the TX buffer descriptors
512
   //
513
   always @(posedge ethmac_txen)
514
     begin
515 411 julius
         ethmac_last_txbd_lenstat = 0;
516
         eth_stim_tx_loop_keep_polling=1;
517 408 julius
         // Wait on the TxBD Ready bit
518 411 julius
         while(eth_stim_tx_loop_keep_polling)
519 408 julius
           begin
520
              #10;
521 411 julius
              get_bd_lenstat(expected_txbd, ethmac_txbd_lenstat);
522 408 julius
              // Check if we've finished transmitting this BD
523 411 julius
              if (!ethmac_txbd_lenstat[15] & ethmac_last_txbd_lenstat[15])
524 408 julius
                // Falling edge of TX BD Ready
525 411 julius
                eth_stim_detected_packet_tx = 1;
526 408 julius
 
527 411 julius
              ethmac_last_txbd_lenstat = ethmac_txbd_lenstat;
528 408 julius
 
529
              // If TX en goes low then exit
530
              if (!ethmac_txen)
531 411 julius
                eth_stim_tx_loop_keep_polling = 0;
532
              else if (eth_stim_detected_packet_tx)
533 408 julius
                begin
534
                   // Wait until the eth_phy has finished receiving it
535
                   while (eth_phy0.mtxen_i === 1'b1)
536
                     #10;
537
 
538
                   $display("(%t) Check TX packet: bd %d: 0x%h",$time,
539 411 julius
                            expected_txbd, ethmac_txbd_lenstat);
540 408 julius
 
541
                   // Check the TXBD, see if the packet transmitted OK
542 411 julius
                   if (ethmac_txbd_lenstat[8] | ethmac_txbd_lenstat[3])
543 408 julius
                     begin
544
                        // Error occured
545
                        `TIME;
546
                        $display("*E TX Error of packet %0d detected.",
547
                                 num_tx_packets);
548
                        $display(" TX BD %0d = 0x%h", expected_txbd,
549 411 julius
                                 ethmac_txbd_lenstat);
550
                        if (ethmac_txbd_lenstat[8])
551 408 julius
                          $display(" Underrun in MAC during TX");
552 411 julius
                        if (ethmac_txbd_lenstat[3])
553 408 julius
                          $display(" Retransmission limit hit");
554
 
555
                        $finish;
556
                     end
557
                   else
558
                     begin
559 411 julius
                        // Packet was OK, let's compare the contents we 
560
                        // received with those that were meant to be transmitted
561 408 julius
                        if (eth_stim_check_tx_packet_contents)
562
                          begin
563
                             check_tx_packet(expected_txbd);
564
                             expected_txbd = (expected_txbd + 1) &
565
                                             num_tx_bds_mask;
566
                             num_tx_packets = num_tx_packets + 1;
567 411 julius
                             eth_stim_detected_packet_tx = 0;
568 408 julius
                          end
569
                     end
570
                end
571 411 julius
           end // while (eth_stim_tx_loop_keep_polling)
572 408 julius
     end // always @ (posedge ethmac_txen)
573
 
574
 
575
 
576
   //
577
   // Check packet TX'd by MAC was good
578
   // 
579
   task check_tx_packet;
580
      input [31:0] tx_bd_num;
581
 
582
      reg [31:0]   tx_bd_addr;
583
      reg [7:0]    phy_byte;
584
 
585
      reg [31:0]   txpnt_wb; // Pointer in array to where data should be
586 411 julius
      reg [24:0]   txpnt_sdram; // Index in array of shorts for data in SDRAM 
587
                                // part
588 408 julius
      reg [21:0]   buffer;
589 439 julius
      reg [7:0]    destram_byte;
590 408 julius
      reg [31:0]   tx_len_bd;
591
 
592 439 julius
      integer      i,j;
593 408 julius
      integer      failure;
594
      begin
595
         failure = 0;
596
 
597
         get_bd_lenstat(tx_bd_num, tx_len_bd);
598
 
599
         tx_len_bd = {15'd0,tx_len_bd[31:16]};
600
 
601
         // Check, if length didn't have to be padded, that
602
         // amount transmitted was correct
603
         if ((tx_len_bd > 60)&(tx_len_bd != (eth_phy0.tx_len-4)))
604
           begin
605
              $display("*E TX packet sent length, %0d != length in TX BD, %0d",
606
                       eth_phy0.tx_len-4, tx_len_bd);
607
              #100;
608
              $finish;
609
           end
610
 
611
         get_bd_addr(tx_bd_num, tx_bd_addr);
612
 
613
         // We're never going to be using more than about 256K of receive buffer
614
         // so let's lop off the top bit of the address pointer - we only want
615
         // the offset from the base of the memory bank
616
         txpnt_wb = {14'd0,tx_bd_addr[17:0]};
617
         txpnt_sdram = tx_bd_addr[24:0];
618
 
619
         // Variable we'll use for index in the PHY's TX buffer
620
         buffer = 0; // Start of TX data
621 439 julius
`ifdef RAM_WB
622 408 julius
         for (i=0;i<tx_len_bd;i=i+1)
623
           begin
624
              //$display("Checking address in tx bd 0x%0h",txpnt_sdram);
625
 
626 439 julius
              destram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram);
627
 
628
              phy_byte = eth_phy0.tx_mem[buffer];
629
 
630
              // Debugging output
631
              //$display("txpnt_sdram = 0x%h, destram_byte = 0x%h, buffer = 0x%h,
632
              //phy_byte = 0x%h", txpnt_sdram,  destram_byte, buffer, phy_byte);
633
 
634
              if (phy_byte !== destram_byte)
635
                begin
636
                   `TIME;
637
                   $display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, destram_byte, phy_byte);
638
                   failure = 1;
639
                end
640
 
641
              buffer = buffer + 1;
642
 
643
              txpnt_sdram = txpnt_sdram+1;
644
 
645
           end // for (i=0;i<tx_len_bd;i=i+1)
646
`else
647
 `ifdef VERSATILE_SDRAM
648
         for (i=0;i<tx_len_bd;i=i+1)
649
           begin
650
              //$display("Checking address in tx bd 0x%0h",txpnt_sdram);
651
 
652
              sdram0.get_byte(txpnt_sdram,destram_byte);
653 408 julius
 
654
              phy_byte = eth_phy0.tx_mem[buffer];
655
              // Debugging output
656 439 julius
              //$display("txpnt_sdram = 0x%h, destram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram,  destram_byte, buffer, phy_byte);
657
              if (phy_byte !== destram_byte)
658 408 julius
                begin
659
                   `TIME;
660 439 julius
                   $display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, destram_byte, phy_byte);
661 408 julius
                   failure = 1;
662
                end
663
 
664
              buffer = buffer + 1;
665
 
666
              txpnt_sdram = txpnt_sdram+1;
667
 
668
           end // for (i=0;i<tx_len_bd;i=i+1)
669
 
670 439 julius
 `else // !`ifdef VERSATILE_SDRAM
671 530 julius
 
672 439 julius
         $display("eth_stim.v: CANNOT INSPECT RAM. PLEASE CONFIGURE CORRECTLY");
673 408 julius
         $display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
674
                  tx_bd_addr, txpnt_wb);
675
         $finish;
676 530 julius
 
677 439 julius
 `endif // !`ifdef VERSATILE_SDRAM
678
`endif // !`ifdef RAM_WB         
679
 
680 408 julius
         if (failure)
681
           begin
682
              #100
683
                `TIME;
684
              $display("*E Error transmitting packet %0d (%0d bytes). Finishing simulation", num_tx_packets, tx_len_bd);
685
              get_bd_lenstat(tx_bd_num, tx_len_bd);
686
              $display("   TXBD lenstat: 0x%0h",tx_len_bd);
687
              $display("   TXBD address: 0x%0h",tx_bd_addr);
688
              $finish;
689
           end
690
         else
691
           begin
692
              #1 $display( "(%0t)(%m) TX packet %0d: %0d bytes in memory OK!",$time,num_tx_packets, tx_len_bd);
693
 
694
           end
695
 
696
 
697
      end
698
   endtask // check_tx_packet
699
 
700 530 julius
 
701
   // Local buffer of "sent" data to the ethernet MAC, we will check against
702
   // Size of our local buffer in bytes
703
   parameter eth_rx_sent_circbuf_size = (16*1024);
704
   parameter eth_rx_sent_circbuf_size_mask = eth_rx_sent_circbuf_size - 1;
705
   integer eth_rx_sent_circbuf_fill_ptr = 0;
706
   integer eth_rx_sent_circbuf_read_ptr = 0;
707
   // The actual buffer
708
   reg [7:0] eth_rx_sent_circbuf [0:eth_rx_sent_circbuf_size-1];
709
 
710
 
711 408 julius
   //
712
   // Task to send a set of packets
713
   //
714
   task send_packet_loop;
715
      input [31:0] num_packets;
716
      input [31:0] length;
717
      input [1:0]  length_change; // 0 = none, 1 = incr, 2 = decrement
718
      input [31:0] length_change_size; // Size to change by
719
      input        speed;
720
      input [31:0] back_to_back_delay; // #delay setting between packets
721
      input [47:0] dst_mac;
722
      input [47:0] src_mac;
723
      input        random_fill;
724
      input        random_errors;
725 530 julius
      input [31:0] random_error_mod;
726
      input        dont_confirm_rx;
727
      integer      j, k;
728 408 julius
      reg          error_this_time;
729
      integer      error_type; // 0 = rxerr, 1=bad preamble 2=bad crc 3=TODO
730
      reg [31:0]   rx_bd_lenstat;
731
      begin
732
         error_type = 0;
733
         error_this_time = 0;
734 411 julius
 
735
         if (num_packets == 0)
736
           // Loop forever when num_packets is 0
737
           num_packets = 32'h7fffffff;
738 408 julius
 
739 411 julius
 
740 408 julius
         if (speed & !(eth_phy0.control_bit14_10[13] === 1'b1))
741
           begin
742
              // write to phy's control register for 100Mbps
743
              eth_phy0.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
744
              // Swapping speeds, give some delay
745
              #10000;
746
           end
747
         else if (!speed & !(eth_phy0.control_bit14_10[13] === 1'b0))
748
           begin
749
              eth_phy0.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
750
              // Swapping speeds, give some delay
751
              #10000;
752
           end
753
 
754
         eth_phy0.control_bit8_0   = 9'h1_00;
755
 
756
         for(j=0;j<num_packets | length <32;j=j+1)
757
           begin
758
              eth_stim_rx_packet_length = length[15:0]; // Bytes
759
              st_data = 8'h0F;
760
 
761
              // setup RX packet in buffer - length is without CRC
762
              set_rx_packet(0, eth_stim_rx_packet_length, 1'b0, dst_mac,
763
                            src_mac, 16'h0D0E, st_data, random_fill);
764
 
765
              set_rx_addr_type(0, dst_mac, src_mac, 16'h0D0E);
766
 
767
              // Error type 2 is cause CRC error
768
              append_rx_crc(0, eth_stim_rx_packet_length, 1'b0,
769
                            (error_type==2));
770
 
771
              if (error_this_time)
772
                begin
773
                   if (error_type == 0)
774
                     // RX ERR assert during transmit
775
                     eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7,
776
                                             8'hD5, 0,
777
                                             eth_stim_rx_packet_length+4,
778
                                             1'b0, 1'b1);
779
                   else if (error_type == 1)
780
                     // Incorrect preamble
781
                     eth_phy0.send_rx_packet(64'h0055_5f55_5555_5555, 4'h7,
782
                                             8'hD5, 0,
783
                                             eth_stim_rx_packet_length+4,
784
                                             1'b0, 1'b0);
785
                   else
786
                     // Normal datapacket
787
                     eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7,
788
                                             8'hD5, 0,
789
                                             eth_stim_rx_packet_length+4,
790
                                             1'b0, 1'b0);
791
                end
792
              else
793
                eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5,
794
                                        0, eth_stim_rx_packet_length+4, 1'b0,
795
                                        1'b0);
796
 
797
 
798
              // if RX enable still set (might have gone low during this packet
799
              if (ethmac_rxen)
800
                begin
801 530 julius
                   if (error_this_time || dont_confirm_rx) begin
802 408 julius
                     // Put in dummy length, checking function will skip...
803
                     rx_packet_lengths[(eth_rx_num_packets_sent& 12'h3ff)]=32'heeeeeeee;
804 530 julius
 
805
                      for(k=0;k<length;k=k+1)
806
                      // skip data  in verify buffer
807
                        eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
808
                                                       eth_rx_sent_circbuf_size_mask;
809
 
810
                   end
811 408 julius
                   else
812
                     rx_packet_lengths[(eth_rx_num_packets_sent & 12'h3ff)] = length;
813
 
814
                   eth_rx_num_packets_sent = eth_rx_num_packets_sent + 1;
815
 
816
                end // if (ethmac_rxen)
817
              else
818
                begin
819
                   // Force the loop to finish up                  
820
                   j = num_packets;
821
                end
822
 
823
 
824
              // Inter-packet gap
825
              #back_to_back_delay;
826
 
827
              // Update length
828
              if (length_change == 2'b01)
829
                length = length + length_change_size;
830
 
831
              if ((length_change == 2'b10) &&
832
                  ((length - length_change_size) > 32))
833
                length = length - length_change_size;
834
 
835
              // Increment error type
836
              if (error_this_time)
837
                error_type = error_type + 1;
838
              if (error_type > 3)
839
                error_type = 0;
840
 
841
 
842
              // Check if we should put in an error this time
843
              if (j%random_error_mod == 0)
844
                error_this_time = 1;
845
              else
846
                error_this_time = 0;
847
 
848
              eth_phy0.rx_err(0);
849
 
850
              // Now wait to check if we have filled up all the RX BDs and
851
              // the this packet would start writing over them. Only really an
852
              // issue when doing minimum IPG tests.
853
              while(((eth_rx_num_packets_sent+1) - eth_rx_num_packets_checked)
854
                    == num_rx_bds)
855
                #100;
856
 
857
 
858
           end // for (j=0;j<num_packets | length <32;j=j+1)
859
      end
860
   endtask // send_packet_loop
861
 
862
   /*
863
    TASKS for set and check RX packets:
864
    -----------------------------------
865
    set_rx_packet
866
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
867
    check_rx_packet
868
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
869
    */
870
   task set_rx_packet;
871
      input  [31:0] rxpnt; // pointer to place in in the phy rx buffer we'll start at
872
      input [15:0]  len;
873
      input         plus_dribble_nibble; // if length is longer for one nibble
874
      input [47:0]  eth_dest_addr;
875
      input [47:0]  eth_source_addr;
876
      input [15:0]  eth_type_len;
877
      input [7:0]   eth_start_data;
878
      input         random_fill;
879
      integer       i, sd;
880
      reg [47:0]    dest_addr;
881
      reg [47:0]    source_addr;
882
      reg [15:0]    type_len;
883
      reg [21:0]    buffer;
884
      reg           delta_t;
885
 
886
      begin
887
         buffer = rxpnt[21:0];
888
         dest_addr = eth_dest_addr;
889
         source_addr = eth_source_addr;
890
         type_len = eth_type_len;
891
         sd = eth_start_data;
892
         delta_t = 0;
893
         for(i = 0; i < len; i = i + 1)
894
           begin
895
              if (i < 6)
896
                begin
897
                   eth_phy0.rx_mem[buffer] = dest_addr[47:40];
898
                   dest_addr = dest_addr << 8;
899
                end
900
              else if (i < 12)
901
                begin
902
                   eth_phy0.rx_mem[buffer] = source_addr[47:40];
903
                   source_addr = source_addr << 8;
904
                end
905
              else if (i < 14)
906
                begin
907
                   eth_phy0.rx_mem[buffer] = type_len[15:8];
908
                   type_len = type_len << 8;
909
                end
910
              else
911
                begin
912
                   if (random_fill)
913
                     begin
914
                        if (lfsr_last_byte == 0)
915
                          eth_phy0.rx_mem[buffer] = lfsr[15:8];
916
                        if (lfsr_last_byte == 1)
917
                          eth_phy0.rx_mem[buffer] = lfsr[23:16];
918
                        if (lfsr_last_byte == 2)
919
                          eth_phy0.rx_mem[buffer] = lfsr[31:24];
920
                        if (lfsr_last_byte == 3)
921
                          begin
922
                             eth_phy0.rx_mem[buffer] = lfsr[7:0];
923
                             lfsr = {lfsr[30:0],(((lfsr[31] ^ lfsr[6]) ^
924
                                                  lfsr[5]) ^ lfsr[1])};
925
                             lfsr_last_byte =  0;
926
                          end
927
                        else
928
                          lfsr_last_byte = lfsr_last_byte + 1;
929
 
930
                     end // if (random_fill)               
931
                   else
932
                     eth_phy0.rx_mem[buffer] = sd[7:0];
933
                   sd = sd + 1;
934
                end // else: !if(i < 14)
935
 
936
              // Update our local buffer
937
              eth_rx_sent_circbuf[eth_rx_sent_circbuf_fill_ptr]
938
                = eth_phy0.rx_mem[buffer];
939
              eth_rx_sent_circbuf_fill_ptr = (eth_rx_sent_circbuf_fill_ptr+1)&
940
                                             eth_rx_sent_circbuf_size_mask;
941
 
942
              buffer = buffer + 1;
943
           end // for (i = 0; i < len; i = i + 1)
944
 
945
         delta_t = !delta_t;
946
         if (plus_dribble_nibble)
947
           eth_phy0.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
948
         delta_t = !delta_t;
949
      end
950
   endtask // set_rx_packet
951
 
952
 
953
 
954
 
955
   task set_rx_addr_type;
956
      input  [31:0] rxpnt;
957
      input [47:0]  eth_dest_addr;
958
      input [47:0]  eth_source_addr;
959
      input [15:0]  eth_type_len;
960
      integer       i;
961
      reg [47:0]    dest_addr;
962
      reg [47:0]    source_addr;
963
      reg [15:0]    type_len;
964
      reg [21:0]    buffer;
965
      reg           delta_t;
966
      begin
967
         buffer = rxpnt[21:0];
968
         dest_addr = eth_dest_addr;
969
         source_addr = eth_source_addr;
970
         type_len = eth_type_len;
971
         delta_t = 0;
972
         for(i = 0; i < 14; i = i + 1)
973
           begin
974
              if (i < 6)
975
                begin
976
                   eth_phy0.rx_mem[buffer] = dest_addr[47:40];
977
                   dest_addr = dest_addr << 8;
978
                end
979
              else if (i < 12)
980
                begin
981
                   eth_phy0.rx_mem[buffer] = source_addr[47:40];
982
                   source_addr = source_addr << 8;
983
                end
984
              else // if (i < 14)
985
                begin
986
                   eth_phy0.rx_mem[buffer] = type_len[15:8];
987
                   type_len = type_len << 8;
988
                end
989
              buffer = buffer + 1;
990
           end
991
         delta_t = !delta_t;
992
      end
993
   endtask // set_rx_addr_type
994
 
995
 
996 411 julius
   // Check if we're using a synthesized version of eth module
997
`ifdef ethmac_IS_GATELEVEL
998
 
999 408 julius
   // Get the length/status register of the ethernet buffer descriptor
1000
   task get_bd_lenstat;
1001
      input [31:0] bd_num;// Number of ethernet BD to check
1002
      output [31:0] bd_lenstat;
1003
 `ifdef ACTEL
1004
      reg [8:0]    tmp;
1005
      integer      raddr;
1006
 `endif
1007
      begin
1008
 `ifdef ACTEL
1009
 
1010
         // Pull from the Actel memory model
1011
         raddr = `ETH_BD_RAM_PATH.\mem_tile.I_1 .get_address((bd_num*2));
1012
 
1013
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)];
1014
         bd_lenstat[8:0] = tmp[8:0];
1015
 
1016
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)+1];
1017
         bd_lenstat[17:9] = tmp[8:0];
1018
 
1019
         raddr = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .get_address((bd_num*2));
1020
 
1021
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)];
1022
         bd_lenstat[26:18] = tmp[8:0];
1023
 
1024
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)+1];
1025
         bd_lenstat[31:27] = tmp[4:0];
1026
 
1027
         //$display("(%t) read eth bd lenstat %h",$time, bd_lenstat);
1028
 `endif
1029
      end
1030
   endtask // get_bd_lenstat
1031
 
1032
   // Get the length/status register of the ethernet buffer descriptor
1033
   task get_bd_addr;
1034
      input [31:0] bd_num;// Number of the ethernet BD to check
1035
      output [31:0] bd_addr;
1036
 `ifdef ACTEL
1037
      reg [8:0]    tmp;
1038
      integer       raddr;
1039
 `endif
1040
      begin
1041
 `ifdef ACTEL
1042
         // Pull from the Actel memory model
1043
         raddr = `ETH_BD_RAM_PATH.\mem_tile.I_1 .get_address((bd_num*2)+1);
1044
 
1045
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)];
1046
         bd_addr[8:0] = tmp[8:0];
1047
 
1048
         tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)+1];
1049
         bd_addr[17:9] = tmp[8:0];
1050
 
1051
         raddr = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .get_address((bd_num*2)+1);
1052
 
1053
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)];
1054
         bd_addr[26:18] = tmp[8:0];
1055
 
1056
         tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)+1];
1057
         bd_addr[31:27] = tmp[4:0];
1058
 
1059
         //$display("(%t) read eth bd%d addr %h",$time,bd_num, bd_addr);
1060
 `endif
1061
      end
1062
   endtask // get_bd_addr
1063
 
1064 411 julius
`else // !`ifdef ethmac_IS_GATELEVEL
1065 408 julius
 
1066
   // Get the length/status register of the ethernet buffer descriptor
1067
   task get_bd_lenstat;
1068
      input [31:0] bd_num;// Number of ethernet BD to check
1069
      output [31:0] bd_lenstat;
1070
      begin
1071
         bd_lenstat = `ETH_BD_RAM_PATH.mem[(bd_num*2)];
1072
      end
1073
   endtask // get_bd_lenstat
1074
 
1075
   // Get the length/status register of the ethernet buffer descriptor
1076
   task get_bd_addr;
1077
      input [31:0] bd_num;// Number of the ethernet BD to check
1078
      output [31:0] bd_addr;
1079
      begin
1080
         bd_addr = `ETH_BD_RAM_PATH.mem[((bd_num*2)+1)];
1081
         //$display("(%t) read eth bd%d addr %h",$time,bd_num, bd_addr);
1082
      end
1083
   endtask // get_bd_addr
1084
`endif
1085
 
1086
   // Always block triggered by finishing of transmission of new packet from 
1087
   // send_packet_loop
1088
   integer eth_rx_packet_length_to_check;
1089
 
1090
   always @*
1091
     begin
1092 411 julius
        // Loop here until:
1093
        // 1 - packets sent is not equal to packets checked (ie. some to check)
1094
        // 2 - we're explicitly disabled for some reason
1095
        // 3 - Receive has been disabled in the MAC
1096 408 julius
        while((eth_rx_num_packets_sent == eth_rx_num_packets_checked) ||
1097 411 julius
              !eth_stim_check_rx_packet_contents || !(ethmac_rxen===1'b1))
1098 408 julius
          #1000;
1099 411 julius
 
1100 408 julius
        eth_rx_packet_length_to_check
1101
          = rx_packet_lengths[(eth_rx_num_packets_checked & 12'h3ff)];
1102
 
1103
        if ( eth_rx_packet_length_to_check !==  32'heeeeeeee)
1104
          check_rx_packet(expected_rxbd, 0, eth_rx_packet_length_to_check);
1105
 
1106
        eth_rx_num_packets_checked = eth_rx_num_packets_checked + 1;
1107
 
1108
        expected_rxbd = expected_rxbd + 1;
1109
 
1110
        // Wrap
1111
        if (expected_rxbd == (num_tx_bds + num_rx_bds))
1112
          expected_rxbd = num_tx_bds;
1113
     end
1114
 
1115
   task check_rx_packet;
1116
 
1117
      input [31:0] rx_bd_num;
1118
      input [31:0] rxpnt_phy; // Pointer in array of data in PHY
1119
      input [31:0] len;
1120
 
1121
      reg [31:0]   rx_bd_lenstat;
1122
      reg [31:0]   rx_bd_addr;
1123
      reg [7:0]    phy_byte;
1124
 
1125
      reg [31:0]   rxpnt_wb; // Pointer in array to where data should be
1126
      reg [24:0]   rxpnt_sdram; // byte address from CPU in RAM
1127
      reg [15:0]   sdram_short;
1128 439 julius
      reg [7:0]    destram_byte;
1129 408 julius
 
1130
      integer      i;
1131
      integer      failure;
1132
 
1133
      begin
1134
 
1135
         failure = 0;
1136
 
1137
         // Wait until the buffer descriptor indicates the packet has been 
1138
         // received...
1139
         get_bd_lenstat(rx_bd_num, rx_bd_lenstat);
1140
         while (rx_bd_lenstat & 32'h00008000)// Check Empty bit
1141
           begin
1142
              #10;
1143
              get_bd_lenstat(rx_bd_num, rx_bd_lenstat);
1144
              //$display("(%t) check_rx_packet: poll bd %d: 0x%h",$time,
1145
                //        rx_bd_num, rx_bd_lenstat);
1146
           end
1147
 
1148
 
1149
         // Delay some time - takes a bit for the Wishbone FSM to pipe out the
1150
         // packet over Wishbone and into whatever memory it's going into
1151
         #Td_rx_packet_check;
1152
 
1153
         // Ok, buffer filled, let's get its offset in memory
1154
         get_bd_addr(rx_bd_num, rx_bd_addr);
1155
 
1156
         $display("(%t) Check RX packet: bd %d: 0x%h, addr 0x%h",$time,
1157
                  rx_bd_num, rx_bd_lenstat, rx_bd_addr);
1158
 
1159
 
1160
         // We're never going to be using more than about 256KB of receive buffer
1161
         // so let's lop off the top bit of the address pointer - we only want
1162
         // the offset from the base of the memory bank
1163
 
1164
         rxpnt_wb = {14'd0,rx_bd_addr[17:0]};
1165
         rxpnt_sdram = rx_bd_addr[24:0];
1166 439 julius
 
1167
 
1168
`ifdef RAM_WB
1169
         for (i=0;i<len;i=i+1)
1170
           begin
1171
 
1172
              destram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(rxpnt_sdram);
1173
 
1174
              phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];
1175
 
1176
              if (phy_byte !== destram_byte)
1177
                begin
1178
                   $display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
1179
                            i, eth_rx_num_packets_checked, phy_byte, destram_byte);
1180
                   failure = 1;
1181
                end
1182
 
1183
              eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
1184
                                             eth_rx_sent_circbuf_size_mask;
1185
 
1186
              rxpnt_sdram = rxpnt_sdram+1;
1187
 
1188
           end
1189
`else
1190
 `ifdef VERSATILE_SDRAM
1191 408 julius
         // We'll look inside the SDRAM array
1192
         // Hard coded for the SDRAM buffer area to be from the halfway mark in
1193
         // memory (so starting in Bank2)
1194
         // We'll be passed the offset from the beginning of the buffer area
1195
         // in rxpnt_wb. This value will be in bytes.
1196
 
1197
         //$display("RAM pointer for BD is 0x%h, SDRAM addr is 0x%h", rx_bd_addr, rxpnt_sdram);
1198
 
1199
 
1200
         for (i=0;i<len;i=i+1)
1201
           begin
1202
 
1203 439 julius
              sdram0.get_byte(rxpnt_sdram,destram_byte);
1204 408 julius
 
1205
              phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];//phy_rx_mem[buffer]; //eth_phy0.rx_mem[buffer];
1206
 
1207 439 julius
              if (phy_byte !== destram_byte)
1208 408 julius
                begin
1209 411 julius
//                 `TIME;                 
1210
                   $display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
1211 439 julius
                            i, eth_rx_num_packets_checked, phy_byte, destram_byte);
1212 408 julius
                   failure = 1;
1213
                end
1214
 
1215
              eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
1216
                                             eth_rx_sent_circbuf_size_mask;
1217
 
1218
              rxpnt_sdram = rxpnt_sdram+1;
1219
 
1220
           end // for (i=0;i<len;i=i+2)
1221 439 julius
 `else
1222 408 julius
 
1223 439 julius
         $display("eth_stim.v: CANNOT INSPECT RAM. PLEASE CONFIGURE CORRECTLY");
1224 408 julius
         $display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
1225
                  rx_bd_addr, rxpnt_wb);
1226
         $finish;
1227
 
1228 439 julius
 `endif // !`ifdef VERSATILE_SDRAM
1229
`endif // !`ifdef RAM_WB
1230
 
1231 408 julius
 
1232
         if (failure)
1233
           begin
1234
              #100
1235
                `TIME;
1236
              $display("*E Recieved packet %0d, length %0d bytes, had an error. Finishing simulation.", eth_rx_num_packets_checked, len);
1237
              $finish;
1238
           end
1239
         else
1240
           begin
1241
              #1 $display( "(%0t)(%m) RX packet %0d: %0d bytes in memory OK!",$time,eth_rx_num_packets_checked, len);
1242
 
1243
           end
1244
      end
1245
   endtask // check_rx_packet
1246
 
1247
 
1248
   //////////////////////////////////////////////////////////////
1249
   // Ethernet CRC Basic tasks
1250
   //////////////////////////////////////////////////////////////
1251
 
1252
   task append_rx_crc;
1253
      input  [31:0] rxpnt_phy; // source
1254
      input [15:0]  len; // length in bytes without CRC
1255
      input         plus_dribble_nibble; // if length is longer for one nibble
1256
      input         negated_crc; // if appended CRC is correct or not
1257
      reg [31:0]    crc;
1258
      reg [7:0]     tmp;
1259
      reg [31:0]    addr_phy;
1260
      reg           delta_t;
1261
      begin
1262
         addr_phy = rxpnt_phy + len;
1263
         delta_t = 0;
1264
         // calculate CRC from prepared packet
1265
         paralel_crc_phy_rx(rxpnt_phy, {16'h0, len}, plus_dribble_nibble, crc);
1266
         if (negated_crc)
1267
           crc = ~crc;
1268
         delta_t = !delta_t;
1269
 
1270
         if (plus_dribble_nibble)
1271
           begin
1272
              tmp = eth_phy0.rx_mem[addr_phy];
1273
              eth_phy0.rx_mem[addr_phy]     = {crc[27:24], tmp[3:0]};
1274
              eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
1275
              eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
1276
              eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
1277
              eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
1278
           end
1279
         else
1280
           begin
1281
              eth_phy0.rx_mem[addr_phy]     = crc[31:24];
1282
              eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
1283
              eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
1284
              eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
1285
           end
1286
      end
1287
   endtask // append_rx_crc
1288
 
1289
   task append_rx_crc_delayed;
1290
      input  [31:0] rxpnt_phy; // source
1291
      input [15:0]  len; // length in bytes without CRC
1292
      input         plus_dribble_nibble; // if length is longer for one nibble
1293
      input         negated_crc; // if appended CRC is correct or not
1294
      reg [31:0]    crc;
1295
      reg [7:0]     tmp;
1296
      reg [31:0]    addr_phy;
1297
      reg           delta_t;
1298
      begin
1299
         addr_phy = rxpnt_phy + len;
1300
         delta_t = 0;
1301
         // calculate CRC from prepared packet
1302
         paralel_crc_phy_rx(rxpnt_phy+4, {16'h0, len}-4, plus_dribble_nibble, crc);
1303
         if (negated_crc)
1304
           crc = ~crc;
1305
         delta_t = !delta_t;
1306
 
1307
         if (plus_dribble_nibble)
1308
           begin
1309
              tmp = eth_phy0.rx_mem[addr_phy];
1310
              eth_phy0.rx_mem[addr_phy]     = {crc[27:24], tmp[3:0]};
1311
              eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
1312
              eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
1313
              eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
1314
              eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
1315
           end
1316
         else
1317
           begin
1318
              eth_phy0.rx_mem[addr_phy]     = crc[31:24];
1319
              eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
1320
              eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
1321
              eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
1322
           end
1323
      end
1324
   endtask // append_rx_crc_delayed
1325
 
1326
 
1327
   // paralel CRC calculating for PHY RX
1328
   task paralel_crc_phy_rx;
1329
      input  [31:0] start_addr; // start address
1330
      input [31:0]  len; // length of frame in Bytes without CRC length
1331
      input         plus_dribble_nibble; // if length is longer for one nibble
1332
      output [31:0] crc_out;
1333
      reg [21:0]    addr_cnt; // only 22 address lines
1334
      integer       word_cnt;
1335
      integer       nibble_cnt;
1336
      reg [31:0]    load_reg;
1337
      reg           delta_t;
1338
      reg [31:0]    crc_next;
1339
      reg [31:0]    crc;
1340
      reg           crc_error;
1341
      reg [3:0]     data_in;
1342
      integer       i;
1343
      begin
1344
         #1 addr_cnt = start_addr[21:0];
1345
         word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
1346
         crc = 32'hFFFF_FFFF; // INITIAL value
1347
         delta_t = 0;
1348
         // length must include 4 bytes of ZEROs, to generate CRC
1349
         // get number of nibbles from Byte length (2^1 = 2)
1350
         if (plus_dribble_nibble)
1351
           nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
1352
         else
1353
           nibble_cnt = ((len + 4) << 1);
1354
         // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
1355
         load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
1356
         addr_cnt = addr_cnt + 1;
1357
         load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
1358
         addr_cnt = addr_cnt + 1;
1359
         load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
1360
         addr_cnt = addr_cnt + 1;
1361
         load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
1362
         addr_cnt = addr_cnt + 1;
1363
         while (nibble_cnt > 0)
1364
           begin
1365
              // wait for delta time
1366
              delta_t = !delta_t;
1367
              // shift data in
1368
 
1369
              if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
1370
                data_in[3:0] = 4'h0;
1371
              else
1372
 
1373
                data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
1374
              crc_next[0]  = (data_in[0] ^ crc[28]);
1375
              crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
1376
              crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
1377
              crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
1378
              crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
1379
              crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
1380
              crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
1381
              crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
1382
              crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
1383
              crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
1384
              crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
1385
              crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
1386
              crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
1387
              crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
1388
              crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
1389
              crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
1390
              crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
1391
              crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
1392
              crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
1393
              crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
1394
              crc_next[20] =  crc[16];
1395
              crc_next[21] =  crc[17];
1396
              crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
1397
              crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
1398
              crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
1399
              crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
1400
              crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
1401
              crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
1402
              crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
1403
              crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
1404
              crc_next[30] =  crc[26];
1405
              crc_next[31] =  crc[27];
1406
 
1407
              crc = crc_next;
1408
              crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
1409
              case (nibble_cnt)
1410
                9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
1411
                              !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
1412
                              !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
1413
                              !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
1414
                default: crc_out = crc_out;
1415
              endcase
1416
              // wait for delta time
1417
              delta_t = !delta_t;
1418
              // increment address and load new data
1419
              if ((word_cnt+3) == 7)//4)
1420
                begin
1421
                   // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
1422
                   load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
1423
                   addr_cnt = addr_cnt + 1;
1424
                   load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
1425
                   addr_cnt = addr_cnt + 1;
1426
                   load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
1427
                   addr_cnt = addr_cnt + 1;
1428
                   load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
1429
                   addr_cnt = addr_cnt + 1;
1430
                end
1431
              // set new load bit position
1432
              if((word_cnt+3) == 31)
1433
                word_cnt = 16;
1434
              else if ((word_cnt+3) == 23)
1435
                word_cnt = 8;
1436
              else if ((word_cnt+3) == 15)
1437
                word_cnt = 0;
1438
              else if ((word_cnt+3) == 7)
1439
                word_cnt = 24;
1440
              else
1441
                word_cnt = word_cnt + 4;// - 4;
1442
              // decrement nibble counter
1443
              nibble_cnt = nibble_cnt - 1;
1444
              // wait for delta time
1445
              delta_t = !delta_t;
1446
           end // while
1447
         #1;
1448
      end
1449
   endtask // paralel_crc_phy_rx
1450
 
1451
 
1452
 
1453
 

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