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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 592

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1 408 julius
//////////////////////////////////////////////////////////////////////
2
///                                                               //// 
3
/// ORPSoC testbench                                              ////
4
///                                                               ////
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/// Instantiate ORPSoC, monitors, provide stimulus                ////
6
///                                                               ////
7
/// Julius Baxter, julius@opencores.org                           ////
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///                                                               ////
9
//////////////////////////////////////////////////////////////////////
10
////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
12
////                                                              ////
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//// This source file may be used and distributed without         ////
14
//// restriction provided that this copyright statement is not    ////
15
//// removed from the file and that any derivative work contains  ////
16
//// the original copyright notice and the associated disclaimer. ////
17
////                                                              ////
18
//// This source file is free software; you can redistribute it   ////
19
//// and/or modify it under the terms of the GNU Lesser General   ////
20
//// Public License as published by the Free Software Foundation; ////
21
//// either version 2.1 of the License, or (at your option) any   ////
22
//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
25
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
26
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
27
//// PURPOSE.  See the GNU Lesser General Public License for more ////
28
//// details.                                                     ////
29
////                                                              ////
30
//// You should have received a copy of the GNU Lesser General    ////
31
//// Public License along with this source; if not, download it   ////
32
//// from http://www.opencores.org/lgpl.shtml                     ////
33
////                                                              ////
34
//////////////////////////////////////////////////////////////////////
35
 
36
`include "orpsoc-defines.v"
37
`include "orpsoc-testbench-defines.v"
38
`include "test-defines.v"
39
 
40
`include "timescale.v"
41
 
42
module orpsoc_testbench;
43
 
44
   // Clock and reset signal registers
45
   reg clk = 0;
46
   reg rst_n = 1; // Active LOW
47
   reg eth_clk = 0;
48
 
49
   always
50
     #((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
51
 
52
`ifdef ETH_CLK
53
   always
54
     #((`ETHERNET_CLOCK_PERIOD)/2) eth_clk <= ~eth_clk;
55
`endif
56
 
57
 
58
   // Reset, ACTIVE LOW
59
   initial
60
     begin
61
        #1;
62
        repeat (32) @(negedge clk)
63
          rst_n <= 1;
64
        repeat (32) @(negedge clk)
65
          rst_n <= 0;
66
        repeat (32) @(negedge clk)
67
          rst_n <= 1;
68
     end
69
 
70
   // Include design parameters file
71
`include "orpsoc-params.v"
72
 
73
   // Pullup bus for I2C
74
   tri1 i2c_scl, i2c_sda;
75
 
76
`ifdef JTAG_DEBUG
77
   wire                      tdo_pad_o;
78
   wire                      tck_pad_i;
79
   wire                      tms_pad_i;
80
   wire                      tdi_pad_i;
81
`endif
82
`ifdef UART0
83
   wire                      uart0_stx_pad_o;
84
   wire                      uart0_srx_pad_i;
85
`endif
86
`ifdef GPIO0
87
   wire [gpio0_io_width-1:0] gpio0_io;
88
`endif
89
`ifdef VERSATILE_SDRAM
90
   wire [12:0]                sdram_a_pad_o;
91
   wire [1:0]                 sdram_ba_pad_o;
92
   wire                      sdram_cas_pad_o;
93
   wire                      sdram_cke_pad_o;
94
   wire                      sdram_cs_n_pad_o;
95
   wire [15:0]                sdram_dq_pad_io;
96
   wire [1:0]                 sdram_dqm_pad_o;
97
   wire                      sdram_ras_pad_o;
98
   wire                      sdram_we_pad_o;
99
`endif
100
`ifdef SPI0
101
   wire                      spi0_mosi_o;
102
   wire                      spi0_miso_i;
103
   wire                      spi0_sck_o;
104
   wire                      spi0_hold_n_o;
105
   wire                      spi0_w_n_o;
106
   wire [spi0_ss_width-1:0]  spi0_ss_o;
107
`endif
108
`ifdef SPI1
109
   wire                      spi1_mosi_o;
110
   wire                      spi1_miso_i;
111
   wire                      spi1_sck_o;
112
   wire [spi1_ss_width-1:0]  spi1_ss_o;
113
`endif
114
`ifdef SPI2
115
   wire                      spi2_mosi_o;
116
   wire                      spi2_miso_i;
117
   wire                      spi2_sck_o;
118
   wire [spi2_ss_width-1:0]  spi2_ss_o;
119
`endif
120
`ifdef USB0
121
   wire                      usb0fullspeed_pad_o;
122
   wire                      usb0ctrl_pad_o;
123
   wire [1:0]                 usb0dat_pad_o;
124
   wire [1:0]                 usb0dat_pad_i;
125
`endif
126
`ifdef USB1
127
   wire                      usb1fullspeed_pad_o;
128
   wire                      usb1ctrl_pad_o;
129
   wire [1:0]                 usb1dat_pad_o;
130
   wire [1:0]                 usb1dat_pad_i;
131
`endif
132
`ifdef ETH0
133
 `ifdef SMII0
134
   parameter Td_smii = 2;
135
   wire                      #Td_smii eth0_smii_sync_pad_o;
136
   wire                      #Td_smii eth0_smii_tx_pad_o;
137
   wire                      #Td_smii eth0_smii_rx_pad_i;
138
 `endif
139
   wire                      mtx_clk_o;
140
   wire [3:0]                 ethphy_mii_tx_d;
141
   wire                      ethphy_mii_tx_en;
142
   wire                      ethphy_mii_tx_err;
143
   wire                      mrx_clk_o;
144
   wire [3:0]                 mrxd_o;
145
   wire                      mrxdv_o;
146
   wire                      mrxerr_o;
147
   wire                      mcoll_o;
148
   wire                      mcrs_o;
149
   wire                      ethphy_rst_n;
150
 
151
   wire                      eth0_mdc_pad_o;
152
   wire                      eth0_md_pad_io;
153
`endif
154
 
155
   orpsoc_top dut
156
     (
157
`ifdef JTAG_DEBUG
158
      .tms_pad_i                        (tms_pad_i),
159
      .tck_pad_i                        (tck_pad_i),
160
      .tdi_pad_i                        (tdi_pad_i),
161
      .tdo_pad_o                        (tdo_pad_o),
162
`endif
163
`ifdef VERSATILE_SDRAM
164
      .sdram_dq_pad_io                  (sdram_dq_pad_io),
165
      .sdram_ba_pad_o                   (sdram_ba_pad_o),
166
      .sdram_a_pad_o                    (sdram_a_pad_o),
167
      .sdram_cs_n_pad_o                 (sdram_cs_n_pad_o),
168
      .sdram_ras_pad_o                  (sdram_ras_pad_o),
169
      .sdram_cas_pad_o                  (sdram_cas_pad_o),
170
      .sdram_we_pad_o                   (sdram_we_pad_o),
171
      .sdram_dqm_pad_o                  (sdram_dqm_pad_o),
172
      .sdram_cke_pad_o                  (sdram_cke_pad_o),
173
`endif
174
`ifdef UART0
175
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
176
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
177
`endif
178
`ifdef SPI0
179
      .spi0_sck_o                       (spi0_sck_o),
180
      .spi0_mosi_o                      (spi0_mosi_o),
181
      .spi0_miso_i                      (spi0_miso_i),
182
 `ifdef SPI0_SLAVE_SELECTS
183
      .spi0_ss_o                        (spi0_ss_o),
184
 `endif
185
      .spi0_hold_n_o                    (spi0_hold_n_o),
186
      .spi0_w_n_o                       (spi0_w_n_o),
187
`endif
188
`ifdef SPI1
189
      .spi1_sck_o                       (spi1_sck_o),
190
      .spi1_mosi_o                      (spi1_mosi_o),
191
      .spi1_miso_i                      (spi1_miso_i),
192
 `ifdef SPI1_SLAVE_SELECTS
193
      .spi1_ss_o                        (spi1_ss_o),
194
 `endif
195
`endif
196
`ifdef SPI2
197
      .spi2_sck_o                       (spi2_sck_o),
198
      .spi2_mosi_o                      (spi2_mosi_o),
199
      .spi2_miso_i                      (spi2_miso_i),
200
 `ifdef SPI2_SLAVE_SELECTS
201
      .spi2_ss_o                        (spi2_ss_o),
202
 `endif
203
`endif
204
`ifdef USB0
205
      .usb0dat_pad_o                    (usb0dat_pad_o),
206
      .usb0ctrl_pad_o                   (usb0ctrl_pad_o),
207
      .usb0fullspeed_pad_o              (usb0fullspeed_pad_o),
208
      .usb0dat_pad_i                    (usb0dat_pad_i),
209
`endif
210
`ifdef USB1
211
      .usb1dat_pad_o                    (usb1dat_pad_o),
212
      .usb1ctrl_pad_o                   (usb1ctrl_pad_o),
213
      .usb1fullspeed_pad_o              (usb1fullspeed_pad_o),
214
      .usb1dat_pad_i                    (usb1dat_pad_i),
215
`endif
216
`ifdef I2C0
217
      .i2c0_sda_io                      (i2c_sda),
218
      .i2c0_scl_io                      (i2c_scl),
219
`endif
220
`ifdef I2C1
221
      .i2c1_sda_io                      (i2c_sda),
222
      .i2c1_scl_io                      (i2c_scl),
223
`endif
224
`ifdef I2C2
225
      .i2c2_sda_io                      (i2c_sda),
226
      .i2c2_scl_io                      (i2c_scl),
227
`endif
228
`ifdef I2C3
229
      .i2c3_sda_io                      (i2c_sda),
230
      .i2c3_scl_io                      (i2c_scl),
231
`endif
232
`ifdef GPIO0
233
      .gpio0_io                         (gpio0_io),
234
`endif
235
`ifdef ETH0
236
 `ifdef SMII0
237
      .eth0_smii_sync_pad_o                  (eth0_smii_sync_pad_o),
238
      .eth0_smii_tx_pad_o                    (eth0_smii_tx_pad_o),
239
      .eth0_smii_rx_pad_i                    (eth0_smii_rx_pad_i),
240
 `else
241
      .eth0_tx_clk                      (mtx_clk_o),
242
      .eth0_tx_data                     (ethphy_mii_tx_d),
243
      .eth0_tx_en                       (ethphy_mii_tx_en),
244
      .eth0_tx_er                       (ethphy_mii_tx_err),
245
      .eth0_rx_clk                      (mrx_clk_o),
246
      .eth0_rx_data                     (mrxd_o),
247
      .eth0_dv                          (mrxdv_o),
248
      .eth0_rx_er                       (mrxerr_o),
249
      .eth0_col                         (mcoll_o),
250
      .eth0_crs                         (mcrs_o),
251
 `endif // !`ifdef SMII0
252
 `ifdef ETH0_PHY_RST
253
      .eth0_rst_n_o                     (ethphy_rst_n),
254
 `endif
255
      .eth0_mdc_pad_o                   (eth0_mdc_pad_o),
256
      .eth0_md_pad_io                   (eth0_md_pad_io),
257
`endif //  `ifdef ETH0
258
`ifdef ETH_CLK
259
      .eth_clk_pad_i                    (eth_clk),
260
`endif
261 544 julius
`ifdef SDC_CONTROLLER
262
      .sdc_cmd_pad_io                   (),
263
      .sdc_dat_pad_io                   (),
264
      .sdc_clk_pad_o                    (),
265
      .sdc_card_detect_pad_i            (1'b0),
266
`endif
267 408 julius
 
268
      .sys_clk_pad_i                    (clk),
269
      .rst_n_pad_i                      (rst_n)
270
      );
271
 
272
   //
273
   // Instantiate OR1200 monitor
274
   //
275
   or1200_monitor monitor();
276
 
277
`ifndef SIM_QUIET
278
 `define CPU_ic_top or1200_ic_top
279
 `define CPU_dc_top or1200_dc_top
280
   wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
281
   always @(posedge ic_en)
282
     $display("Or1200 IC enabled at %t", $time);
283
 
284
   wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
285
   always @(posedge dc_en)
286
     $display("Or1200 DC enabled at %t", $time);
287
`endif
288
 
289
 
290
`ifdef JTAG_DEBUG
291
 `ifdef VPI_DEBUG
292
   // Debugging interface
293
   vpi_debug_module vpi_dbg
294
     (
295
      .tms(tms_pad_i),
296
      .tck(tck_pad_i),
297
      .tdi(tdi_pad_i),
298
      .tdo(tdo_pad_o)
299
      );
300
 `else
301
   // If no VPI debugging, tie off JTAG inputs
302
   assign tdi_pad_i = 1;
303
   assign tck_pad_i = 0;
304
   assign tms_pad_i = 1;
305
 `endif // !`ifdef VPI_DEBUG_ENABLE
306
`endif //  `ifdef JTAG_DEBUG
307
 
308
`ifdef SPI0
309
   // SPI Flash
310
   AT26DFxxx spi0_flash
311
     (// Outputs
312
      .SO                                       (spi0_miso_i),
313
      // Inputs
314
      .CSB                                      (spi0_ss_o),
315
      .SCK                                      (spi0_sck_o),
316
      .SI                                       (spi0_mosi_o),
317
      .WPB                                      (spi0_w_n_o)
318
      );
319
`endif //  `ifdef SPI0
320
 
321
`ifdef ETH0
322
   // ORDB1 with OREEB1 always uses SMII, but keep this anyway.
323
 `ifdef SMII0
324
 
325
   wire                      fast_ethernet, duplex, link;
326
   wire                      eth_clk_smii_phy;
327
 
328
   assign eth_clk_smii_phy = eth_clk;
329
 
330
   /* Converts SMII back to MII */
331
   smii_phy smii_phyend
332
     (
333
      // Outputs
334
      .smii_rx                          (/*eth0_smii_rx_pad_i*/), /* SMII RX */
335
      .ethphy_mii_tx_d                  (ethphy_mii_tx_d[3:0]), /* MII TX */
336
      .ethphy_mii_tx_en                 (ethphy_mii_tx_en),     /* MII TX */
337
      .ethphy_mii_tx_err                (ethphy_mii_tx_err),    /* MII TX */
338
      // Inputs
339
      .smii_tx                          (eth0_smii_tx_pad_o),   /* SMII TX */
340
      .smii_sync                        (eth0_smii_sync_pad_o), /* SMII SYNC */
341
      .ethphy_mii_tx_clk                (mtx_clk_o),            /* MII TX */
342
 
343
      .ethphy_mii_rx_d                  (mrxd_o[3:0]), /* MII RX */
344
      .ethphy_mii_rx_dv                 (mrxdv_o),     /* MII RX */
345
      .ethphy_mii_rx_err                (mrxerr_o),    /* MII RX */
346
      .ethphy_mii_rx_clk                (mrx_clk_o),   /* MII RX */
347
 
348
      .ethphy_mii_mcoll                 (),
349
      .ethphy_mii_crs                   (mcrs_o),
350
      .fast_ethernet                    (fast_ethernet),
351
      .duplex                           (duplex),
352
      .link                             (link),
353
      .clk                              (eth_clk_smii_phy),
354
      .rst_n                            (rst_n));
355
 
356
 `endif //  `ifdef SMII0
357
 
358
   /* TX/RXes packets and checks them, enabled when ethernet MAC is */
359
 `include "eth_stim.v"
360
 
361
   eth_phy eth_phy0
362
     (
363
      // Outputs
364
      .mtx_clk_o                        (mtx_clk_o),
365
      .mrx_clk_o                        (mrx_clk_o),
366
      .mrxd_o                           (mrxd_o[3:0]),
367
      .mrxdv_o                          (mrxdv_o),
368
      .mrxerr_o                         (mrxerr_o),
369
      .mcoll_o                          (mcoll_o),
370
      .mcrs_o                           (mcrs_o),
371
      // Sideband outputs for smii converter --jb
372
      .link_o                             (link),
373
      .speed_o                            (fast_ethernet),
374
      .duplex_o                           (duplex),
375
      .smii_clk_i                       (eth_clk),
376
      .smii_sync_i                      (eth0_smii_sync_pad_o),
377
      .smii_rx_o                        (eth0_smii_rx_pad_i),
378
      // Inouts
379
      .md_io                            (eth0_md_pad_io),
380
      // Inputs
381
 `ifndef ETH0_PHY_RST
382
      // If no reset out from the design, hook up to the board's active low rst
383
      .m_rst_n_i                        (rst_n),
384
 `else
385
      .m_rst_n_i                        (ethphy_rst_n),
386
 `endif
387
      .mtxd_i                           (ethphy_mii_tx_d[3:0]),
388
      .mtxen_i                          (ethphy_mii_tx_en),
389
      .mtxerr_i                         (ethphy_mii_tx_err),
390
      .mdc_i                            (eth0_mdc_pad_o));
391
 
392
`endif //  `ifdef ETH0
393
 
394
   // Simple slaves to test the SPI masters
395
`ifdef SPI1
396
 `ifdef SPI1_SLAVE_SELECTS
397
   wire [spi1_ss_width-1:0]  spi1_leds;
398
   genvar                    spi1;
399
   generate
400
      for (spi1 = 0; spi1 < spi1_ss_width; spi1 = spi1+1) begin : spi1_gen
401
         spi_slave spi1_slave
402
           (.clk(clk),
403
            .SCK(spi1_sck_o), .MOSI(spi1_mosi_o),
404
            .MISO(spi1_miso_i), .SSEL(spi1_ss_o[spi1]),
405
            .LED(spi1_leds[spi1]));
406
      end
407
   endgenerate
408
 `else // !`ifdef SPI1_SLAVE_SELECTS
409
   spi_slave spi1_slave
410
     (.clk(clk),
411
      .SCK(spi1_sck_o), .MOSI(spi1_mosi_o),
412
      .MISO(spi1_miso_i), .SSEL(1'b0),
413
      .LED());
414
 `endif // !`ifdef SPI1_SLAVE_SELECTS   
415
`endif
416
 
417
`ifdef SPI2
418
 `ifdef SPI2_SLAVE_SELECTS
419
   wire [spi2_ss_width-1:0] spi2_leds;
420
   genvar                   spi2;
421
   generate
422
      for (spi2 = 0; spi2 < spi2_ss_width; spi2 = spi2+1) begin : spi2_gen
423
         spi_slave spi2_slave
424
           (.clk(clk),
425
            .SCK(spi2_sck_o), .MOSI(spi2_mosi_o),
426
            .MISO(spi2_miso_i), .SSEL(spi2_ss_o[spi2]),
427
            .LED(spi2_leds[spi2]));
428
      end
429
   endgenerate
430
 `else // !`ifdef SPI2_SLAVE_SELECTS
431
   spi_slave spi2_slave
432
     (.clk(clk),
433
      .SCK(spi2_sck_o), .MOSI(spi2_mosi_o),
434
      .MISO(spi2_miso_i), .SSEL(1'b0),
435
      .LED());
436
 `endif // !`ifdef SPI2_SLAVE_SELECTS   
437
`endif
438
 
439
`ifdef VERSATILE_SDRAM
440
   parameter TPROP_PCB = 2.0;
441
   reg [12:0]                 sdram_a_pad_o_to_sdram;
442
   reg [1:0]                  sdram_ba_pad_o_to_sdram;
443
   reg                       sdram_cas_pad_o_to_sdram;
444
   reg                       sdram_cke_pad_o_to_sdram;
445
   reg                       sdram_cs_n_pad_o_to_sdram;
446
   wire [15:0]                sdram_dq_pad_io_to_sdram;
447
   reg [1:0]                  sdram_dqm_pad_o_to_sdram;
448
   reg                       sdram_ras_pad_o_to_sdram;
449
   reg                       sdram_we_pad_o_to_sdram;
450
 
451
   always @( * ) begin
452
      sdram_a_pad_o_to_sdram    <= #(TPROP_PCB) sdram_a_pad_o;
453
      sdram_ba_pad_o_to_sdram   <= #(TPROP_PCB) sdram_ba_pad_o;
454
      sdram_cas_pad_o_to_sdram  <= #(TPROP_PCB) sdram_cas_pad_o;
455
      sdram_cke_pad_o_to_sdram  <= #(TPROP_PCB) sdram_cke_pad_o;
456
      sdram_cs_n_pad_o_to_sdram <= #(TPROP_PCB) sdram_cs_n_pad_o;
457
      sdram_dqm_pad_o_to_sdram  <= #(TPROP_PCB) sdram_dqm_pad_o;
458
      sdram_ras_pad_o_to_sdram  <= #(TPROP_PCB) sdram_ras_pad_o;
459
      sdram_we_pad_o_to_sdram   <= #(TPROP_PCB) sdram_we_pad_o;
460
   end
461
 
462
   genvar dqwd;
463
   generate
464
      for (dqwd = 0;dqwd < 16 ;dqwd = dqwd+1) begin : dq_delay
465
         wiredelay #
466
           (
467
            .Delay_g     (TPROP_PCB),
468
            .Delay_rd    (TPROP_PCB)
469
            )
470
         u_delay_dq
471
           (
472
            .A           (sdram_dq_pad_io[dqwd]),
473
            .B           (sdram_dq_pad_io_to_sdram[dqwd]),
474
            .reset       (rst_n)
475
            );
476
      end
477
   endgenerate
478
 
479
   // SDRAM
480
   mt48lc16m16a2 sdram0
481
     (
482
      // Inouts
483
      .Dq    (sdram_dq_pad_io_to_sdram),
484
      // Inputs
485
      .Addr  (sdram_a_pad_o_to_sdram),
486
      .Ba    (sdram_ba_pad_o_to_sdram),
487
      .Clk   (clk),
488
      .Cke   (sdram_cke_pad_o_to_sdram),
489
      .Cs_n  (sdram_cs_n_pad_o_to_sdram),
490
      .Ras_n (sdram_ras_pad_o_to_sdram),
491
      .Cas_n (sdram_cas_pad_o_to_sdram),
492
      .We_n  (sdram_we_pad_o_to_sdram),
493
      .Dqm   (sdram_dqm_pad_o_to_sdram));
494
`endif //  `ifdef VERSATILE_SDRAM
495
 
496 411 julius
`ifdef VCD
497
   reg vcd_go = 0;
498
   always @(vcd_go)
499 408 julius
     begin
500 411 julius
 
501 408 julius
 `ifdef VCD_DELAY
502
        #(`VCD_DELAY);
503
 `endif
504
 
505
        // Delay by x insns
506
 `ifdef VCD_DELAY_INSNS
507
        #10; // Delay until after the value becomes valid
508
        while (monitor.insns < `VCD_DELAY_INSNS)
509
          @(posedge clk);
510
 `endif
511
 
512
 `ifdef SIMULATOR_MODELSIM
513
        // Modelsim can GZip VCDs on the fly if given in the suffix
514
  `define VCD_SUFFIX   ".vcd.gz"
515
 `else
516
  `define VCD_SUFFIX   ".vcd"
517
 `endif
518
 
519
`ifndef SIM_QUIET
520
        $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
521
`endif
522
        $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
523
 `ifndef VCD_DEPTH
524
  `define VCD_DEPTH 0
525
 `endif
526
        $dumpvars(`VCD_DEPTH);
527 411 julius
 
528
     end
529
`endif //  `ifdef VCD
530
 
531
   initial
532
     begin
533
`ifndef SIM_QUIET
534
        $display("\n* Starting simulation of design RTL.\n* Test: %s\n",
535
                 `TEST_NAME_STRING );
536
`endif
537
 
538
`ifdef VCD
539
        vcd_go = 1;
540 408 julius
`endif
541 411 julius
 
542
     end // initial begin
543 408 julius
 
544
`ifdef END_TIME
545
   initial begin
546
      #(`END_TIME);
547
`ifndef SIM_QUIET
548
      $display("* Finish simulation due to END_TIME being set at %t", $time);
549
`endif
550
      $finish;
551
   end
552
`endif
553
 
554
`ifdef END_INSNS
555
   initial begin
556
      #10
557
        while (monitor.insns < `END_INSNS)
558
          @(posedge clk);
559
 `ifndef SIM_QUIET
560
      $display("* Finish simulation due to END_INSNS count (%d) reached at %t",
561
               `END_INSNS, $time);
562
 `endif
563
      $finish;
564
   end
565
`endif
566
 
567
`ifdef UART0
568
   //   
569
   // UART0 decoder
570
   //   
571
   uart_decoder
572
     #(
573
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
574
        )
575
   uart0_decoder
576
     (
577
      .clk(clk),
578
      .uart_tx(uart0_stx_pad_o)
579
      );
580
 
581
   // Loopback UART lines
582
   assign uart0_srx_pad_i = uart0_stx_pad_o;
583
 
584
`endif //  `ifdef UART0
585
 
586
`ifdef USB0
587
   // USB testbench setup...
588
    // All USB testbenches disabled for now
589
 `include "usbHostControl_h.v"
590
 `include "wishBoneBus_h.v"
591
 `include "usbHostSlave_h.v"
592
 `include "usbSlaveControl_h.v"
593
 `include "usbHostSlave_h.v"
594
 `include "usbConstants_h.v"
595
   // The actual file with stimulus:
596
 `include "usb_hostslave_tb.v"
597
 
598
`endif
599
 
600
endmodule // orpsoc_testbench
601
 
602
// Local Variables:
603
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
604
// verilog-library-files:()
605
// verilog-library-extensions:(".v" ".h")
606
// End:
607
 

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