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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 425

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//////////////////////////////////////////////////////////////////////
///                                                               //// 
/// ORPSoC testbench                                              ////
///                                                               ////
/// Instantiate ORPSoC, monitors, provide stimulus                ////
///                                                               ////
/// Julius Baxter, julius@opencores.org                           ////
///                                                               ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "orpsoc-defines.v"
`include "orpsoc-testbench-defines.v"
`include "test-defines.v"
 
`include "timescale.v"
 
module orpsoc_testbench;
 
   // Clock and reset signal registers
   reg clk = 0;
   reg rst_n = 1; // Active LOW
   reg eth_clk = 0;
 
   always
     #((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
 
`ifdef ETH_CLK
   always
     #((`ETHERNET_CLOCK_PERIOD)/2) eth_clk <= ~eth_clk;
`endif
 
 
   // Reset, ACTIVE LOW
   initial
     begin
        #1;
        repeat (32) @(negedge clk)
          rst_n <= 1;
        repeat (32) @(negedge clk)
          rst_n <= 0;
        repeat (32) @(negedge clk)
          rst_n <= 1;
     end
 
   // Include design parameters file
`include "orpsoc-params.v"
 
   // Pullup bus for I2C
   tri1 i2c_scl, i2c_sda;
 
`ifdef JTAG_DEBUG
   wire                      tdo_pad_o;
   wire                      tck_pad_i;
   wire                      tms_pad_i;
   wire                      tdi_pad_i;
`endif
`ifdef UART0
   wire                      uart0_stx_pad_o;
   wire                      uart0_srx_pad_i;
`endif
`ifdef GPIO0
   wire [gpio0_io_width-1:0] gpio0_io;
`endif
`ifdef VERSATILE_SDRAM
   wire [12:0]                sdram_a_pad_o;
   wire [1:0]                 sdram_ba_pad_o;
   wire                      sdram_cas_pad_o;
   wire                      sdram_cke_pad_o;
   wire                      sdram_cs_n_pad_o;
   wire [15:0]                sdram_dq_pad_io;
   wire [1:0]                 sdram_dqm_pad_o;
   wire                      sdram_ras_pad_o;
   wire                      sdram_we_pad_o;
`endif
`ifdef SPI0
   wire                      spi0_mosi_o;
   wire                      spi0_miso_i;
   wire                      spi0_sck_o;
   wire                      spi0_hold_n_o;
   wire                      spi0_w_n_o;
   wire [spi0_ss_width-1:0]  spi0_ss_o;
`endif
`ifdef SPI1
   wire                      spi1_mosi_o;
   wire                      spi1_miso_i;
   wire                      spi1_sck_o;
   wire [spi1_ss_width-1:0]  spi1_ss_o;
`endif
`ifdef SPI2
   wire                      spi2_mosi_o;
   wire                      spi2_miso_i;
   wire                      spi2_sck_o;
   wire [spi2_ss_width-1:0]  spi2_ss_o;
`endif
`ifdef USB0
   wire                      usb0fullspeed_pad_o;
   wire                      usb0ctrl_pad_o;
   wire [1:0]                 usb0dat_pad_o;
   wire [1:0]                 usb0dat_pad_i;
`endif
`ifdef USB1
   wire                      usb1fullspeed_pad_o;
   wire                      usb1ctrl_pad_o;
   wire [1:0]                 usb1dat_pad_o;
   wire [1:0]                 usb1dat_pad_i;
`endif
`ifdef ETH0
 `ifdef SMII0
   parameter Td_smii = 2;
   wire                      #Td_smii eth0_smii_sync_pad_o;
   wire                      #Td_smii eth0_smii_tx_pad_o;
   wire                      #Td_smii eth0_smii_rx_pad_i;
 `endif
   wire                      mtx_clk_o;
   wire [3:0]                 ethphy_mii_tx_d;
   wire                      ethphy_mii_tx_en;
   wire                      ethphy_mii_tx_err;
   wire                      mrx_clk_o;
   wire [3:0]                 mrxd_o;
   wire                      mrxdv_o;
   wire                      mrxerr_o;
   wire                      mcoll_o;
   wire                      mcrs_o;
   wire                      ethphy_rst_n;
 
   wire                      eth0_mdc_pad_o;
   wire                      eth0_md_pad_io;
`endif
 
   orpsoc_top dut
     (
`ifdef JTAG_DEBUG
      .tms_pad_i                        (tms_pad_i),
      .tck_pad_i                        (tck_pad_i),
      .tdi_pad_i                        (tdi_pad_i),
      .tdo_pad_o                        (tdo_pad_o),
`endif
`ifdef VERSATILE_SDRAM
      .sdram_dq_pad_io                  (sdram_dq_pad_io),
      .sdram_ba_pad_o                   (sdram_ba_pad_o),
      .sdram_a_pad_o                    (sdram_a_pad_o),
      .sdram_cs_n_pad_o                 (sdram_cs_n_pad_o),
      .sdram_ras_pad_o                  (sdram_ras_pad_o),
      .sdram_cas_pad_o                  (sdram_cas_pad_o),
      .sdram_we_pad_o                   (sdram_we_pad_o),
      .sdram_dqm_pad_o                  (sdram_dqm_pad_o),
      .sdram_cke_pad_o                  (sdram_cke_pad_o),
`endif
`ifdef UART0
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
`endif
`ifdef SPI0
      .spi0_sck_o                       (spi0_sck_o),
      .spi0_mosi_o                      (spi0_mosi_o),
      .spi0_miso_i                      (spi0_miso_i),
 `ifdef SPI0_SLAVE_SELECTS
      .spi0_ss_o                        (spi0_ss_o),
 `endif
      .spi0_hold_n_o                    (spi0_hold_n_o),
      .spi0_w_n_o                       (spi0_w_n_o),
`endif
`ifdef SPI1
      .spi1_sck_o                       (spi1_sck_o),
      .spi1_mosi_o                      (spi1_mosi_o),
      .spi1_miso_i                      (spi1_miso_i),
 `ifdef SPI1_SLAVE_SELECTS
      .spi1_ss_o                        (spi1_ss_o),
 `endif
`endif
`ifdef SPI2
      .spi2_sck_o                       (spi2_sck_o),
      .spi2_mosi_o                      (spi2_mosi_o),
      .spi2_miso_i                      (spi2_miso_i),
 `ifdef SPI2_SLAVE_SELECTS
      .spi2_ss_o                        (spi2_ss_o),
 `endif
`endif
`ifdef USB0
      .usb0dat_pad_o                    (usb0dat_pad_o),
      .usb0ctrl_pad_o                   (usb0ctrl_pad_o),
      .usb0fullspeed_pad_o              (usb0fullspeed_pad_o),
      .usb0dat_pad_i                    (usb0dat_pad_i),
`endif
`ifdef USB1
      .usb1dat_pad_o                    (usb1dat_pad_o),
      .usb1ctrl_pad_o                   (usb1ctrl_pad_o),
      .usb1fullspeed_pad_o              (usb1fullspeed_pad_o),
      .usb1dat_pad_i                    (usb1dat_pad_i),
`endif
`ifdef I2C0
      .i2c0_sda_io                      (i2c_sda),
      .i2c0_scl_io                      (i2c_scl),
`endif
`ifdef I2C1
      .i2c1_sda_io                      (i2c_sda),
      .i2c1_scl_io                      (i2c_scl),
`endif
`ifdef I2C2
      .i2c2_sda_io                      (i2c_sda),
      .i2c2_scl_io                      (i2c_scl),
`endif
`ifdef I2C3
      .i2c3_sda_io                      (i2c_sda),
      .i2c3_scl_io                      (i2c_scl),
`endif
`ifdef GPIO0
      .gpio0_io                         (gpio0_io),
`endif
`ifdef ETH0
 `ifdef SMII0
      .eth0_smii_sync_pad_o                  (eth0_smii_sync_pad_o),
      .eth0_smii_tx_pad_o                    (eth0_smii_tx_pad_o),
      .eth0_smii_rx_pad_i                    (eth0_smii_rx_pad_i),
 `else
      .eth0_tx_clk                      (mtx_clk_o),
      .eth0_tx_data                     (ethphy_mii_tx_d),
      .eth0_tx_en                       (ethphy_mii_tx_en),
      .eth0_tx_er                       (ethphy_mii_tx_err),
      .eth0_rx_clk                      (mrx_clk_o),
      .eth0_rx_data                     (mrxd_o),
      .eth0_dv                          (mrxdv_o),
      .eth0_rx_er                       (mrxerr_o),
      .eth0_col                         (mcoll_o),
      .eth0_crs                         (mcrs_o),
 `endif // !`ifdef SMII0
 `ifdef ETH0_PHY_RST
      .eth0_rst_n_o                     (ethphy_rst_n),
 `endif
      .eth0_mdc_pad_o                   (eth0_mdc_pad_o),
      .eth0_md_pad_io                   (eth0_md_pad_io),
`endif //  `ifdef ETH0
`ifdef ETH_CLK
      .eth_clk_pad_i                    (eth_clk),
`endif
 
      .sys_clk_pad_i                    (clk),
      .rst_n_pad_i                      (rst_n)
      );
 
   //
   // Instantiate OR1200 monitor
   //
   or1200_monitor monitor();
 
`ifndef SIM_QUIET
 `define CPU_ic_top or1200_ic_top
 `define CPU_dc_top or1200_dc_top
   wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
   always @(posedge ic_en)
     $display("Or1200 IC enabled at %t", $time);
 
   wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
   always @(posedge dc_en)
     $display("Or1200 DC enabled at %t", $time);
`endif
 
 
`ifdef JTAG_DEBUG
 `ifdef VPI_DEBUG
   // Debugging interface
   vpi_debug_module vpi_dbg
     (
      .tms(tms_pad_i),
      .tck(tck_pad_i),
      .tdi(tdi_pad_i),
      .tdo(tdo_pad_o)
      );
 `else
   // If no VPI debugging, tie off JTAG inputs
   assign tdi_pad_i = 1;
   assign tck_pad_i = 0;
   assign tms_pad_i = 1;
 `endif // !`ifdef VPI_DEBUG_ENABLE
`endif //  `ifdef JTAG_DEBUG
 
`ifdef SPI0
   // SPI Flash
   AT26DFxxx spi0_flash
     (// Outputs
      .SO                                       (spi0_miso_i),
      // Inputs
      .CSB                                      (spi0_ss_o),
      .SCK                                      (spi0_sck_o),
      .SI                                       (spi0_mosi_o),
      .WPB                                      (spi0_w_n_o)
      );
`endif //  `ifdef SPI0
 
`ifdef ETH0
   // ORDB1 with OREEB1 always uses SMII, but keep this anyway.
 `ifdef SMII0
 
   wire                      fast_ethernet, duplex, link;
   wire                      eth_clk_smii_phy;
 
   assign eth_clk_smii_phy = eth_clk;
 
   /* Converts SMII back to MII */
   smii_phy smii_phyend
     (
      // Outputs
      .smii_rx                          (/*eth0_smii_rx_pad_i*/), /* SMII RX */
      .ethphy_mii_tx_d                  (ethphy_mii_tx_d[3:0]), /* MII TX */
      .ethphy_mii_tx_en                 (ethphy_mii_tx_en),     /* MII TX */
      .ethphy_mii_tx_err                (ethphy_mii_tx_err),    /* MII TX */
      // Inputs
      .smii_tx                          (eth0_smii_tx_pad_o),   /* SMII TX */
      .smii_sync                        (eth0_smii_sync_pad_o), /* SMII SYNC */
      .ethphy_mii_tx_clk                (mtx_clk_o),            /* MII TX */
 
      .ethphy_mii_rx_d                  (mrxd_o[3:0]), /* MII RX */
      .ethphy_mii_rx_dv                 (mrxdv_o),     /* MII RX */
      .ethphy_mii_rx_err                (mrxerr_o),    /* MII RX */
      .ethphy_mii_rx_clk                (mrx_clk_o),   /* MII RX */
 
      .ethphy_mii_mcoll                 (),
      .ethphy_mii_crs                   (mcrs_o),
      .fast_ethernet                    (fast_ethernet),
      .duplex                           (duplex),
      .link                             (link),
      .clk                              (eth_clk_smii_phy),
      .rst_n                            (rst_n));
 
 `endif //  `ifdef SMII0
 
   /* TX/RXes packets and checks them, enabled when ethernet MAC is */
 `include "eth_stim.v"
 
   eth_phy eth_phy0
     (
      // Outputs
      .mtx_clk_o                        (mtx_clk_o),
      .mrx_clk_o                        (mrx_clk_o),
      .mrxd_o                           (mrxd_o[3:0]),
      .mrxdv_o                          (mrxdv_o),
      .mrxerr_o                         (mrxerr_o),
      .mcoll_o                          (mcoll_o),
      .mcrs_o                           (mcrs_o),
      // Sideband outputs for smii converter --jb
      .link_o                             (link),
      .speed_o                            (fast_ethernet),
      .duplex_o                           (duplex),
      .smii_clk_i                       (eth_clk),
      .smii_sync_i                      (eth0_smii_sync_pad_o),
      .smii_rx_o                        (eth0_smii_rx_pad_i),
      // Inouts
      .md_io                            (eth0_md_pad_io),
      // Inputs
 `ifndef ETH0_PHY_RST
      // If no reset out from the design, hook up to the board's active low rst
      .m_rst_n_i                        (rst_n),
 `else
      .m_rst_n_i                        (ethphy_rst_n),
 `endif
      .mtxd_i                           (ethphy_mii_tx_d[3:0]),
      .mtxen_i                          (ethphy_mii_tx_en),
      .mtxerr_i                         (ethphy_mii_tx_err),
      .mdc_i                            (eth0_mdc_pad_o));
 
`endif //  `ifdef ETH0
 
   // Simple slaves to test the SPI masters
`ifdef SPI1
 `ifdef SPI1_SLAVE_SELECTS
   wire [spi1_ss_width-1:0]  spi1_leds;
   genvar                    spi1;
   generate
      for (spi1 = 0; spi1 < spi1_ss_width; spi1 = spi1+1) begin : spi1_gen
         spi_slave spi1_slave
           (.clk(clk),
            .SCK(spi1_sck_o), .MOSI(spi1_mosi_o),
            .MISO(spi1_miso_i), .SSEL(spi1_ss_o[spi1]),
            .LED(spi1_leds[spi1]));
      end
   endgenerate
 `else // !`ifdef SPI1_SLAVE_SELECTS
   spi_slave spi1_slave
     (.clk(clk),
      .SCK(spi1_sck_o), .MOSI(spi1_mosi_o),
      .MISO(spi1_miso_i), .SSEL(1'b0),
      .LED());
 `endif // !`ifdef SPI1_SLAVE_SELECTS   
`endif
 
`ifdef SPI2
 `ifdef SPI2_SLAVE_SELECTS
   wire [spi2_ss_width-1:0] spi2_leds;
   genvar                   spi2;
   generate
      for (spi2 = 0; spi2 < spi2_ss_width; spi2 = spi2+1) begin : spi2_gen
         spi_slave spi2_slave
           (.clk(clk),
            .SCK(spi2_sck_o), .MOSI(spi2_mosi_o),
            .MISO(spi2_miso_i), .SSEL(spi2_ss_o[spi2]),
            .LED(spi2_leds[spi2]));
      end
   endgenerate
 `else // !`ifdef SPI2_SLAVE_SELECTS
   spi_slave spi2_slave
     (.clk(clk),
      .SCK(spi2_sck_o), .MOSI(spi2_mosi_o),
      .MISO(spi2_miso_i), .SSEL(1'b0),
      .LED());
 `endif // !`ifdef SPI2_SLAVE_SELECTS   
`endif
 
`ifdef VERSATILE_SDRAM
   parameter TPROP_PCB = 2.0;
   reg [12:0]                 sdram_a_pad_o_to_sdram;
   reg [1:0]                  sdram_ba_pad_o_to_sdram;
   reg                       sdram_cas_pad_o_to_sdram;
   reg                       sdram_cke_pad_o_to_sdram;
   reg                       sdram_cs_n_pad_o_to_sdram;
   wire [15:0]                sdram_dq_pad_io_to_sdram;
   reg [1:0]                  sdram_dqm_pad_o_to_sdram;
   reg                       sdram_ras_pad_o_to_sdram;
   reg                       sdram_we_pad_o_to_sdram;
 
   always @( * ) begin
      sdram_a_pad_o_to_sdram    <= #(TPROP_PCB) sdram_a_pad_o;
      sdram_ba_pad_o_to_sdram   <= #(TPROP_PCB) sdram_ba_pad_o;
      sdram_cas_pad_o_to_sdram  <= #(TPROP_PCB) sdram_cas_pad_o;
      sdram_cke_pad_o_to_sdram  <= #(TPROP_PCB) sdram_cke_pad_o;
      sdram_cs_n_pad_o_to_sdram <= #(TPROP_PCB) sdram_cs_n_pad_o;
      sdram_dqm_pad_o_to_sdram  <= #(TPROP_PCB) sdram_dqm_pad_o;
      sdram_ras_pad_o_to_sdram  <= #(TPROP_PCB) sdram_ras_pad_o;
      sdram_we_pad_o_to_sdram   <= #(TPROP_PCB) sdram_we_pad_o;
   end
 
   genvar dqwd;
   generate
      for (dqwd = 0;dqwd < 16 ;dqwd = dqwd+1) begin : dq_delay
         wiredelay #
           (
            .Delay_g     (TPROP_PCB),
            .Delay_rd    (TPROP_PCB)
            )
         u_delay_dq
           (
            .A           (sdram_dq_pad_io[dqwd]),
            .B           (sdram_dq_pad_io_to_sdram[dqwd]),
            .reset       (rst_n)
            );
      end
   endgenerate
 
   // SDRAM
   mt48lc16m16a2 sdram0
     (
      // Inouts
      .Dq    (sdram_dq_pad_io_to_sdram),
      // Inputs
      .Addr  (sdram_a_pad_o_to_sdram),
      .Ba    (sdram_ba_pad_o_to_sdram),
      .Clk   (clk),
      .Cke   (sdram_cke_pad_o_to_sdram),
      .Cs_n  (sdram_cs_n_pad_o_to_sdram),
      .Ras_n (sdram_ras_pad_o_to_sdram),
      .Cas_n (sdram_cas_pad_o_to_sdram),
      .We_n  (sdram_we_pad_o_to_sdram),
      .Dqm   (sdram_dqm_pad_o_to_sdram));
`endif //  `ifdef VERSATILE_SDRAM
 
`ifdef VCD
   reg vcd_go = 0;
   always @(vcd_go)
     begin
 
 `ifdef VCD_DELAY
        #(`VCD_DELAY);
 `endif
 
        // Delay by x insns
 `ifdef VCD_DELAY_INSNS
        #10; // Delay until after the value becomes valid
        while (monitor.insns < `VCD_DELAY_INSNS)
          @(posedge clk);
 `endif
 
 `ifdef SIMULATOR_MODELSIM
        // Modelsim can GZip VCDs on the fly if given in the suffix
  `define VCD_SUFFIX   ".vcd.gz"
 `else
  `define VCD_SUFFIX   ".vcd"
 `endif
 
`ifndef SIM_QUIET
        $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
`endif
        $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 `ifndef VCD_DEPTH
  `define VCD_DEPTH 0
 `endif
        $dumpvars(`VCD_DEPTH);
 
     end
`endif //  `ifdef VCD
 
   initial
     begin
`ifndef SIM_QUIET
        $display("\n* Starting simulation of design RTL.\n* Test: %s\n",
                 `TEST_NAME_STRING );
`endif
 
`ifdef VCD
        vcd_go = 1;
`endif
 
     end // initial begin
 
`ifdef END_TIME
   initial begin
      #(`END_TIME);
`ifndef SIM_QUIET
      $display("* Finish simulation due to END_TIME being set at %t", $time);
`endif
      $finish;
   end
`endif
 
`ifdef END_INSNS
   initial begin
      #10
        while (monitor.insns < `END_INSNS)
          @(posedge clk);
 `ifndef SIM_QUIET
      $display("* Finish simulation due to END_INSNS count (%d) reached at %t",
               `END_INSNS, $time);
 `endif
      $finish;
   end
`endif
 
`ifdef UART0
   //   
   // UART0 decoder
   //   
   uart_decoder
     #(
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
        )
   uart0_decoder
     (
      .clk(clk),
      .uart_tx(uart0_stx_pad_o)
      );
 
   // Loopback UART lines
   assign uart0_srx_pad_i = uart0_stx_pad_o;
 
`endif //  `ifdef UART0
 
`ifdef USB0
   // USB testbench setup...
    // All USB testbenches disabled for now
 `include "usbHostControl_h.v"
 `include "wishBoneBus_h.v"
 `include "usbHostSlave_h.v"
 `include "usbSlaveControl_h.v"
 `include "usbHostSlave_h.v"
 `include "usbConstants_h.v"
   // The actual file with stimulus:
 `include "usb_hostslave_tb.v"
 
`endif
 
endmodule // orpsoc_testbench
 
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
// verilog-library-files:()
// verilog-library-extensions:(".v" ".h")
// End:
 

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 425

Line No.	Rev	Author	Line
1	408	julius	`//////////////////////////////////////////////////////////////////////`
2			`/// ////`
3			`/// ORPSoC testbench ////`
4			`/// ////`
5			`/// Instantiate ORPSoC, monitors, provide stimulus ////`
6			`/// ////`
7			`/// Julius Baxter, julius@opencores.org ////`
8			`/// ////`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35
36			`include "orpsoc-defines.v"
37			`include "orpsoc-testbench-defines.v"
38			`include "test-defines.v"
39
40			`include "timescale.v"
41
42			`module orpsoc_testbench;`
43
44			`// Clock and reset signal registers`
45			`reg clk = 0;`
46			`reg rst_n = 1; // Active LOW`
47			`reg eth_clk = 0;`
48
49			`always`
50			#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
51
52			`ifdef ETH_CLK
53			`always`
54			#((`ETHERNET_CLOCK_PERIOD)/2) eth_clk <= ~eth_clk;
55			`endif
56
57
58			`// Reset, ACTIVE LOW`
59			`initial`
60			`begin`
61			`#1;`
62			`repeat (32) @(negedge clk)`
63			`rst_n <= 1;`
64			`repeat (32) @(negedge clk)`
65			`rst_n <= 0;`
66			`repeat (32) @(negedge clk)`
67			`rst_n <= 1;`
68			`end`
69
70			`// Include design parameters file`
71			`include "orpsoc-params.v"
72
73			`// Pullup bus for I2C`
74			`tri1 i2c_scl, i2c_sda;`
75
76			`ifdef JTAG_DEBUG
77			`wire tdo_pad_o;`
78			`wire tck_pad_i;`
79			`wire tms_pad_i;`
80			`wire tdi_pad_i;`
81			`endif
82			`ifdef UART0
83			`wire uart0_stx_pad_o;`
84			`wire uart0_srx_pad_i;`
85			`endif
86			`ifdef GPIO0
87			`wire [gpio0_io_width-1:0] gpio0_io;`
88			`endif
89			`ifdef VERSATILE_SDRAM
90			`wire [12:0] sdram_a_pad_o;`
91			`wire [1:0] sdram_ba_pad_o;`
92			`wire sdram_cas_pad_o;`
93			`wire sdram_cke_pad_o;`
94			`wire sdram_cs_n_pad_o;`
95			`wire [15:0] sdram_dq_pad_io;`
96			`wire [1:0] sdram_dqm_pad_o;`
97			`wire sdram_ras_pad_o;`
98			`wire sdram_we_pad_o;`
99			`endif
100			`ifdef SPI0
101			`wire spi0_mosi_o;`
102			`wire spi0_miso_i;`
103			`wire spi0_sck_o;`
104			`wire spi0_hold_n_o;`
105			`wire spi0_w_n_o;`
106			`wire [spi0_ss_width-1:0] spi0_ss_o;`
107			`endif
108			`ifdef SPI1
109			`wire spi1_mosi_o;`
110			`wire spi1_miso_i;`
111			`wire spi1_sck_o;`
112			`wire [spi1_ss_width-1:0] spi1_ss_o;`
113			`endif
114			`ifdef SPI2
115			`wire spi2_mosi_o;`
116			`wire spi2_miso_i;`
117			`wire spi2_sck_o;`
118			`wire [spi2_ss_width-1:0] spi2_ss_o;`
119			`endif
120			`ifdef USB0
121			`wire usb0fullspeed_pad_o;`
122			`wire usb0ctrl_pad_o;`
123			`wire [1:0] usb0dat_pad_o;`
124			`wire [1:0] usb0dat_pad_i;`
125			`endif
126			`ifdef USB1
127			`wire usb1fullspeed_pad_o;`
128			`wire usb1ctrl_pad_o;`
129			`wire [1:0] usb1dat_pad_o;`
130			`wire [1:0] usb1dat_pad_i;`
131			`endif
132			`ifdef ETH0
133			`ifdef SMII0
134			`parameter Td_smii = 2;`
135			`wire #Td_smii eth0_smii_sync_pad_o;`
136			`wire #Td_smii eth0_smii_tx_pad_o;`
137			`wire #Td_smii eth0_smii_rx_pad_i;`
138			`endif
139			`wire mtx_clk_o;`
140			`wire [3:0] ethphy_mii_tx_d;`
141			`wire ethphy_mii_tx_en;`
142			`wire ethphy_mii_tx_err;`
143			`wire mrx_clk_o;`
144			`wire [3:0] mrxd_o;`
145			`wire mrxdv_o;`
146			`wire mrxerr_o;`
147			`wire mcoll_o;`
148			`wire mcrs_o;`
149			`wire ethphy_rst_n;`
150
151			`wire eth0_mdc_pad_o;`
152			`wire eth0_md_pad_io;`
153			`endif
154
155			`orpsoc_top dut`
156			`(`
157			`ifdef JTAG_DEBUG
158			`.tms_pad_i (tms_pad_i),`
159			`.tck_pad_i (tck_pad_i),`
160			`.tdi_pad_i (tdi_pad_i),`
161			`.tdo_pad_o (tdo_pad_o),`
162			`endif
163			`ifdef VERSATILE_SDRAM
164			`.sdram_dq_pad_io (sdram_dq_pad_io),`
165			`.sdram_ba_pad_o (sdram_ba_pad_o),`
166			`.sdram_a_pad_o (sdram_a_pad_o),`
167			`.sdram_cs_n_pad_o (sdram_cs_n_pad_o),`
168			`.sdram_ras_pad_o (sdram_ras_pad_o),`
169			`.sdram_cas_pad_o (sdram_cas_pad_o),`
170			`.sdram_we_pad_o (sdram_we_pad_o),`
171			`.sdram_dqm_pad_o (sdram_dqm_pad_o),`
172			`.sdram_cke_pad_o (sdram_cke_pad_o),`
173			`endif
174			`ifdef UART0
175			`.uart0_stx_pad_o (uart0_stx_pad_o),`
176			`.uart0_srx_pad_i (uart0_srx_pad_i),`
177			`endif
178			`ifdef SPI0
179			`.spi0_sck_o (spi0_sck_o),`
180			`.spi0_mosi_o (spi0_mosi_o),`
181			`.spi0_miso_i (spi0_miso_i),`
182			`ifdef SPI0_SLAVE_SELECTS
183			`.spi0_ss_o (spi0_ss_o),`
184			`endif
185			`.spi0_hold_n_o (spi0_hold_n_o),`
186			`.spi0_w_n_o (spi0_w_n_o),`
187			`endif
188			`ifdef SPI1
189			`.spi1_sck_o (spi1_sck_o),`
190			`.spi1_mosi_o (spi1_mosi_o),`
191			`.spi1_miso_i (spi1_miso_i),`
192			`ifdef SPI1_SLAVE_SELECTS
193			`.spi1_ss_o (spi1_ss_o),`
194			`endif
195			`endif
196			`ifdef SPI2
197			`.spi2_sck_o (spi2_sck_o),`
198			`.spi2_mosi_o (spi2_mosi_o),`
199			`.spi2_miso_i (spi2_miso_i),`
200			`ifdef SPI2_SLAVE_SELECTS
201			`.spi2_ss_o (spi2_ss_o),`
202			`endif
203			`endif
204			`ifdef USB0
205			`.usb0dat_pad_o (usb0dat_pad_o),`
206			`.usb0ctrl_pad_o (usb0ctrl_pad_o),`
207			`.usb0fullspeed_pad_o (usb0fullspeed_pad_o),`
208			`.usb0dat_pad_i (usb0dat_pad_i),`
209			`endif
210			`ifdef USB1
211			`.usb1dat_pad_o (usb1dat_pad_o),`
212			`.usb1ctrl_pad_o (usb1ctrl_pad_o),`
213			`.usb1fullspeed_pad_o (usb1fullspeed_pad_o),`
214			`.usb1dat_pad_i (usb1dat_pad_i),`
215			`endif
216			`ifdef I2C0
217			`.i2c0_sda_io (i2c_sda),`
218			`.i2c0_scl_io (i2c_scl),`
219			`endif
220			`ifdef I2C1
221			`.i2c1_sda_io (i2c_sda),`
222			`.i2c1_scl_io (i2c_scl),`
223			`endif
224			`ifdef I2C2
225			`.i2c2_sda_io (i2c_sda),`
226			`.i2c2_scl_io (i2c_scl),`
227			`endif
228			`ifdef I2C3
229			`.i2c3_sda_io (i2c_sda),`
230			`.i2c3_scl_io (i2c_scl),`
231			`endif
232			`ifdef GPIO0
233			`.gpio0_io (gpio0_io),`
234			`endif
235			`ifdef ETH0
236			`ifdef SMII0
237			`.eth0_smii_sync_pad_o (eth0_smii_sync_pad_o),`
238			`.eth0_smii_tx_pad_o (eth0_smii_tx_pad_o),`
239			`.eth0_smii_rx_pad_i (eth0_smii_rx_pad_i),`
240			`else
241			`.eth0_tx_clk (mtx_clk_o),`
242			`.eth0_tx_data (ethphy_mii_tx_d),`
243			`.eth0_tx_en (ethphy_mii_tx_en),`
244			`.eth0_tx_er (ethphy_mii_tx_err),`
245			`.eth0_rx_clk (mrx_clk_o),`
246			`.eth0_rx_data (mrxd_o),`
247			`.eth0_dv (mrxdv_o),`
248			`.eth0_rx_er (mrxerr_o),`
249			`.eth0_col (mcoll_o),`
250			`.eth0_crs (mcrs_o),`
251			`endif // !`ifdef SMII0
252			`ifdef ETH0_PHY_RST
253			`.eth0_rst_n_o (ethphy_rst_n),`
254			`endif
255			`.eth0_mdc_pad_o (eth0_mdc_pad_o),`
256			`.eth0_md_pad_io (eth0_md_pad_io),`
257			`endif // `ifdef ETH0
258			`ifdef ETH_CLK
259			`.eth_clk_pad_i (eth_clk),`
260			`endif
261
262			`.sys_clk_pad_i (clk),`
263			`.rst_n_pad_i (rst_n)`
264			`);`
265
266			`//`
267			`// Instantiate OR1200 monitor`
268			`//`
269			`or1200_monitor monitor();`
270
271			`ifndef SIM_QUIET
272			`define CPU_ic_top or1200_ic_top
273			`define CPU_dc_top or1200_dc_top
274			`wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;`
275			`always @(posedge ic_en)`
276			`$display("Or1200 IC enabled at %t", $time);`
277
278			`wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;`
279			`always @(posedge dc_en)`
280			`$display("Or1200 DC enabled at %t", $time);`
281			`endif
282
283
284			`ifdef JTAG_DEBUG
285			`ifdef VPI_DEBUG
286			`// Debugging interface`
287			`vpi_debug_module vpi_dbg`
288			`(`
289			`.tms(tms_pad_i),`
290			`.tck(tck_pad_i),`
291			`.tdi(tdi_pad_i),`
292			`.tdo(tdo_pad_o)`
293			`);`
294			`else
295			`// If no VPI debugging, tie off JTAG inputs`
296			`assign tdi_pad_i = 1;`
297			`assign tck_pad_i = 0;`
298			`assign tms_pad_i = 1;`
299			`endif // !`ifdef VPI_DEBUG_ENABLE
300			`endif // `ifdef JTAG_DEBUG
301
302			`ifdef SPI0
303			`// SPI Flash`
304			`AT26DFxxx spi0_flash`
305			`(// Outputs`
306			`.SO (spi0_miso_i),`
307			`// Inputs`
308			`.CSB (spi0_ss_o),`
309			`.SCK (spi0_sck_o),`
310			`.SI (spi0_mosi_o),`
311			`.WPB (spi0_w_n_o)`
312			`);`
313			`endif // `ifdef SPI0
314
315			`ifdef ETH0
316			`// ORDB1 with OREEB1 always uses SMII, but keep this anyway.`
317			`ifdef SMII0
318
319			`wire fast_ethernet, duplex, link;`
320			`wire eth_clk_smii_phy;`
321
322			`assign eth_clk_smii_phy = eth_clk;`
323
324			`/* Converts SMII back to MII */`
325			`smii_phy smii_phyend`
326			`(`
327			`// Outputs`
328			`.smii_rx (/eth0_smii_rx_pad_i/), /* SMII RX */`
329			`.ethphy_mii_tx_d (ethphy_mii_tx_d[3:0]), /* MII TX */`
330			`.ethphy_mii_tx_en (ethphy_mii_tx_en), /* MII TX */`
331			`.ethphy_mii_tx_err (ethphy_mii_tx_err), /* MII TX */`
332			`// Inputs`
333			`.smii_tx (eth0_smii_tx_pad_o), /* SMII TX */`
334			`.smii_sync (eth0_smii_sync_pad_o), /* SMII SYNC */`
335			`.ethphy_mii_tx_clk (mtx_clk_o), /* MII TX */`
336
337			`.ethphy_mii_rx_d (mrxd_o[3:0]), /* MII RX */`
338			`.ethphy_mii_rx_dv (mrxdv_o), /* MII RX */`
339			`.ethphy_mii_rx_err (mrxerr_o), /* MII RX */`
340			`.ethphy_mii_rx_clk (mrx_clk_o), /* MII RX */`
341
342			`.ethphy_mii_mcoll (),`
343			`.ethphy_mii_crs (mcrs_o),`
344			`.fast_ethernet (fast_ethernet),`
345			`.duplex (duplex),`
346			`.link (link),`
347			`.clk (eth_clk_smii_phy),`
348			`.rst_n (rst_n));`
349
350			`endif // `ifdef SMII0
351
352			`/* TX/RXes packets and checks them, enabled when ethernet MAC is */`
353			`include "eth_stim.v"
354
355			`eth_phy eth_phy0`
356			`(`
357			`// Outputs`
358			`.mtx_clk_o (mtx_clk_o),`
359			`.mrx_clk_o (mrx_clk_o),`
360			`.mrxd_o (mrxd_o[3:0]),`
361			`.mrxdv_o (mrxdv_o),`
362			`.mrxerr_o (mrxerr_o),`
363			`.mcoll_o (mcoll_o),`
364			`.mcrs_o (mcrs_o),`
365			`// Sideband outputs for smii converter --jb`
366			`.link_o (link),`
367			`.speed_o (fast_ethernet),`
368			`.duplex_o (duplex),`
369			`.smii_clk_i (eth_clk),`
370			`.smii_sync_i (eth0_smii_sync_pad_o),`
371			`.smii_rx_o (eth0_smii_rx_pad_i),`
372			`// Inouts`
373			`.md_io (eth0_md_pad_io),`
374			`// Inputs`
375			`ifndef ETH0_PHY_RST
376			`// If no reset out from the design, hook up to the board's active low rst`
377			`.m_rst_n_i (rst_n),`
378			`else
379			`.m_rst_n_i (ethphy_rst_n),`
380			`endif
381			`.mtxd_i (ethphy_mii_tx_d[3:0]),`
382			`.mtxen_i (ethphy_mii_tx_en),`
383			`.mtxerr_i (ethphy_mii_tx_err),`
384			`.mdc_i (eth0_mdc_pad_o));`
385
386			`endif // `ifdef ETH0
387
388			`// Simple slaves to test the SPI masters`
389			`ifdef SPI1
390			`ifdef SPI1_SLAVE_SELECTS
391			`wire [spi1_ss_width-1:0] spi1_leds;`
392			`genvar spi1;`
393			`generate`
394			`for (spi1 = 0; spi1 < spi1_ss_width; spi1 = spi1+1) begin : spi1_gen`
395			`spi_slave spi1_slave`
396			`(.clk(clk),`
397			`.SCK(spi1_sck_o), .MOSI(spi1_mosi_o),`
398			`.MISO(spi1_miso_i), .SSEL(spi1_ss_o[spi1]),`
399			`.LED(spi1_leds[spi1]));`
400			`end`
401			`endgenerate`
402			`else // !`ifdef SPI1_SLAVE_SELECTS
403			`spi_slave spi1_slave`
404			`(.clk(clk),`
405			`.SCK(spi1_sck_o), .MOSI(spi1_mosi_o),`
406			`.MISO(spi1_miso_i), .SSEL(1'b0),`
407			`.LED());`
408			`endif // !`ifdef SPI1_SLAVE_SELECTS
409			`endif
410
411			`ifdef SPI2
412			`ifdef SPI2_SLAVE_SELECTS
413			`wire [spi2_ss_width-1:0] spi2_leds;`
414			`genvar spi2;`
415			`generate`
416			`for (spi2 = 0; spi2 < spi2_ss_width; spi2 = spi2+1) begin : spi2_gen`
417			`spi_slave spi2_slave`
418			`(.clk(clk),`
419			`.SCK(spi2_sck_o), .MOSI(spi2_mosi_o),`
420			`.MISO(spi2_miso_i), .SSEL(spi2_ss_o[spi2]),`
421			`.LED(spi2_leds[spi2]));`
422			`end`
423			`endgenerate`
424			`else // !`ifdef SPI2_SLAVE_SELECTS
425			`spi_slave spi2_slave`
426			`(.clk(clk),`
427			`.SCK(spi2_sck_o), .MOSI(spi2_mosi_o),`
428			`.MISO(spi2_miso_i), .SSEL(1'b0),`
429			`.LED());`
430			`endif // !`ifdef SPI2_SLAVE_SELECTS
431			`endif
432
433			`ifdef VERSATILE_SDRAM
434			`parameter TPROP_PCB = 2.0;`
435			`reg [12:0] sdram_a_pad_o_to_sdram;`
436			`reg [1:0] sdram_ba_pad_o_to_sdram;`
437			`reg sdram_cas_pad_o_to_sdram;`
438			`reg sdram_cke_pad_o_to_sdram;`
439			`reg sdram_cs_n_pad_o_to_sdram;`
440			`wire [15:0] sdram_dq_pad_io_to_sdram;`
441			`reg [1:0] sdram_dqm_pad_o_to_sdram;`
442			`reg sdram_ras_pad_o_to_sdram;`
443			`reg sdram_we_pad_o_to_sdram;`
444
445			`always @( * ) begin`
446			`sdram_a_pad_o_to_sdram <= #(TPROP_PCB) sdram_a_pad_o;`
447			`sdram_ba_pad_o_to_sdram <= #(TPROP_PCB) sdram_ba_pad_o;`
448			`sdram_cas_pad_o_to_sdram <= #(TPROP_PCB) sdram_cas_pad_o;`
449			`sdram_cke_pad_o_to_sdram <= #(TPROP_PCB) sdram_cke_pad_o;`
450			`sdram_cs_n_pad_o_to_sdram <= #(TPROP_PCB) sdram_cs_n_pad_o;`
451			`sdram_dqm_pad_o_to_sdram <= #(TPROP_PCB) sdram_dqm_pad_o;`
452			`sdram_ras_pad_o_to_sdram <= #(TPROP_PCB) sdram_ras_pad_o;`
453			`sdram_we_pad_o_to_sdram <= #(TPROP_PCB) sdram_we_pad_o;`
454			`end`
455
456			`genvar dqwd;`
457			`generate`
458			`for (dqwd = 0;dqwd < 16 ;dqwd = dqwd+1) begin : dq_delay`
459			`wiredelay #`
460			`(`
461			`.Delay_g (TPROP_PCB),`
462			`.Delay_rd (TPROP_PCB)`
463			`)`
464			`u_delay_dq`
465			`(`
466			`.A (sdram_dq_pad_io[dqwd]),`
467			`.B (sdram_dq_pad_io_to_sdram[dqwd]),`
468			`.reset (rst_n)`
469			`);`
470			`end`
471			`endgenerate`
472
473			`// SDRAM`
474			`mt48lc16m16a2 sdram0`
475			`(`
476			`// Inouts`
477			`.Dq (sdram_dq_pad_io_to_sdram),`
478			`// Inputs`
479			`.Addr (sdram_a_pad_o_to_sdram),`
480			`.Ba (sdram_ba_pad_o_to_sdram),`
481			`.Clk (clk),`
482			`.Cke (sdram_cke_pad_o_to_sdram),`
483			`.Cs_n (sdram_cs_n_pad_o_to_sdram),`
484			`.Ras_n (sdram_ras_pad_o_to_sdram),`
485			`.Cas_n (sdram_cas_pad_o_to_sdram),`
486			`.We_n (sdram_we_pad_o_to_sdram),`
487			`.Dqm (sdram_dqm_pad_o_to_sdram));`
488			`endif // `ifdef VERSATILE_SDRAM
489
490	411	julius	`ifdef VCD
491			`reg vcd_go = 0;`
492			`always @(vcd_go)`
493	408	julius	`begin`
494	411	julius
495	408	julius	`ifdef VCD_DELAY
496			#(`VCD_DELAY);
497			`endif
498
499			`// Delay by x insns`
500			`ifdef VCD_DELAY_INSNS
501			`#10; // Delay until after the value becomes valid`
502			while (monitor.insns < `VCD_DELAY_INSNS)
503			`@(posedge clk);`
504			`endif
505
506			`ifdef SIMULATOR_MODELSIM
507			`// Modelsim can GZip VCDs on the fly if given in the suffix`
508			`define VCD_SUFFIX ".vcd.gz"
509			`else
510			`define VCD_SUFFIX ".vcd"
511			`endif
512
513			`ifndef SIM_QUIET
514			$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
515			`endif
516			$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
517			`ifndef VCD_DEPTH
518			`define VCD_DEPTH 0
519			`endif
520			$dumpvars(`VCD_DEPTH);
521	411	julius
522			`end`
523			`endif // `ifdef VCD
524
525			`initial`
526			`begin`
527			`ifndef SIM_QUIET
528			`$display("\n* Starting simulation of design RTL.\n* Test: %s\n",`
529			`TEST_NAME_STRING );
530			`endif
531
532			`ifdef VCD
533			`vcd_go = 1;`
534	408	julius	`endif
535	411	julius
536			`end // initial begin`
537	408	julius
538			`ifdef END_TIME
539			`initial begin`
540			#(`END_TIME);
541			`ifndef SIM_QUIET
542			`$display("* Finish simulation due to END_TIME being set at %t", $time);`
543			`endif
544			`$finish;`
545			`end`
546			`endif
547
548			`ifdef END_INSNS
549			`initial begin`
550			`#10`
551			while (monitor.insns < `END_INSNS)
552			`@(posedge clk);`
553			`ifndef SIM_QUIET
554			`$display("* Finish simulation due to END_INSNS count (%d) reached at %t",`
555			`END_INSNS, $time);
556			`endif
557			`$finish;`
558			`end`
559			`endif
560
561			`ifdef UART0
562			`//`
563			`// UART0 decoder`
564			`//`
565			`uart_decoder`
566			`#(`
567			`.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS`
568			`)`
569			`uart0_decoder`
570			`(`
571			`.clk(clk),`
572			`.uart_tx(uart0_stx_pad_o)`
573			`);`
574
575			`// Loopback UART lines`
576			`assign uart0_srx_pad_i = uart0_stx_pad_o;`
577
578			`endif // `ifdef UART0
579
580			`ifdef USB0
581			`// USB testbench setup...`
582			`// All USB testbenches disabled for now`
583			`include "usbHostControl_h.v"
584			`include "wishBoneBus_h.v"
585			`include "usbHostSlave_h.v"
586			`include "usbSlaveControl_h.v"
587			`include "usbHostSlave_h.v"
588			`include "usbConstants_h.v"
589			`// The actual file with stimulus:`
590			`include "usb_hostslave_tb.v"
591
592			`endif
593
594			`endmodule // orpsoc_testbench`
595
596			`// Local Variables:`
597			`// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")`
598			`// verilog-library-files:()`
599			`// verilog-library-extensions:(".v" ".h")`
600			`// End:`
601