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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [arbiter/] [arbiter_bytebus.v] - Blame information for rev 544

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1 408 julius
//////////////////////////////////////////////////////////////////////
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///                                                               //// 
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/// Wishbone arbiter, byte-wide data path, no bursting            ////
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///                                                               ////
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/// Simple arbiter, single master, multiple slave, for byte-wide  ////
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/// peripherals                                                   ////
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///                                                               ////
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/// Julius Baxter, julius@opencores.org                           ////
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///                                                               ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
29
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
32
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
34
////                                                              ////
35
//////////////////////////////////////////////////////////////////////
36
 
37
//
38
// Things to update when changing slave config:
39
//
40
// 1. Port list
41
// 2. Port specification
42
// 3. Slave addr select parameter
43
// 4. Slave addr selects
44
// 5. Slave input mux logic
45
// 6. The four different master out mux logics (dat_o mux, and ack, rty & err)
46
//
47
`include "orpsoc-defines.v"
48
module arbiter_bytebus
49
  (
50
 
51
   // Master in   
52
   wbm0_adr_o,
53
   wbm0_dat_o,
54
   wbm0_sel_o,
55
   wbm0_we_o,
56
   wbm0_cyc_o,
57
   wbm0_stb_o,
58
   wbm0_cti_o,
59
   wbm0_bte_o,
60
   wbm0_dat_i,
61
   wbm0_ack_i,
62
   wbm0_err_i,
63
   wbm0_rty_i,
64
 
65
   // Slave one
66
   // Wishbone Slave interface
67
   wbs0_adr_i,
68
   wbs0_dat_i,
69
   wbs0_we_i,
70
   wbs0_cyc_i,
71
   wbs0_stb_i,
72
   wbs0_cti_i,
73
   wbs0_bte_i,
74
   wbs0_dat_o,
75
   wbs0_ack_o,
76
   wbs0_err_o,
77
   wbs0_rty_o,
78
 
79
   // Slave two
80
   // Wishbone Slave interface
81
   wbs1_adr_i,
82
   wbs1_dat_i,
83
   wbs1_we_i,
84
   wbs1_cyc_i,
85
   wbs1_stb_i,
86
   wbs1_cti_i,
87
   wbs1_bte_i,
88
   wbs1_dat_o,
89
   wbs1_ack_o,
90
   wbs1_err_o,
91
   wbs1_rty_o,
92
 
93
   // Slave three
94
   // Wishbone Slave interface
95
   wbs2_adr_i,
96
   wbs2_dat_i,
97
   wbs2_we_i,
98
   wbs2_cyc_i,
99
   wbs2_stb_i,
100
   wbs2_cti_i,
101
   wbs2_bte_i,
102
   wbs2_dat_o,
103
   wbs2_ack_o,
104
   wbs2_err_o,
105
   wbs2_rty_o,
106
 
107
   // Slave four
108
   // Wishbone Slave interface
109
   wbs3_adr_i,
110
   wbs3_dat_i,
111
   wbs3_we_i,
112
   wbs3_cyc_i,
113
   wbs3_stb_i,
114
   wbs3_cti_i,
115
   wbs3_bte_i,
116
   wbs3_dat_o,
117
   wbs3_ack_o,
118
   wbs3_err_o,
119
   wbs3_rty_o,
120
 
121
   // Slave five
122
   // Wishbone Slave interface
123
   wbs4_adr_i,
124
   wbs4_dat_i,
125
   wbs4_we_i,
126
   wbs4_cyc_i,
127
   wbs4_stb_i,
128
   wbs4_cti_i,
129
   wbs4_bte_i,
130
   wbs4_dat_o,
131
   wbs4_ack_o,
132
   wbs4_err_o,
133
   wbs4_rty_o,
134
 
135
   // Slave six
136
   // Wishbone Slave interface
137
   wbs5_adr_i,
138
   wbs5_dat_i,
139
   wbs5_we_i,
140
   wbs5_cyc_i,
141
   wbs5_stb_i,
142
   wbs5_cti_i,
143
   wbs5_bte_i,
144
   wbs5_dat_o,
145
   wbs5_ack_o,
146
   wbs5_err_o,
147
   wbs5_rty_o,
148
 
149
   // Slave seven
150
   // Wishbone Slave interface
151
   wbs6_adr_i,
152
   wbs6_dat_i,
153
   wbs6_we_i,
154
   wbs6_cyc_i,
155
   wbs6_stb_i,
156
   wbs6_cti_i,
157
   wbs6_bte_i,
158
   wbs6_dat_o,
159
   wbs6_ack_o,
160
   wbs6_err_o,
161
   wbs6_rty_o,
162
 
163
   // Slave eight
164
   // Wishbone Slave interface
165
   wbs7_adr_i,
166
   wbs7_dat_i,
167
   wbs7_we_i,
168
   wbs7_cyc_i,
169
   wbs7_stb_i,
170
   wbs7_cti_i,
171
   wbs7_bte_i,
172
   wbs7_dat_o,
173
   wbs7_ack_o,
174
   wbs7_err_o,
175
   wbs7_rty_o,
176
 
177
   // Slave nine
178
   // Wishbone Slave interface
179
   wbs8_adr_i,
180
   wbs8_dat_i,
181
   wbs8_we_i,
182
   wbs8_cyc_i,
183
   wbs8_stb_i,
184
   wbs8_cti_i,
185
   wbs8_bte_i,
186
   wbs8_dat_o,
187
   wbs8_ack_o,
188
   wbs8_err_o,
189
   wbs8_rty_o,
190
 
191
   // Slave ten
192
   // Wishbone Slave interface
193
   wbs9_adr_i,
194
   wbs9_dat_i,
195
   wbs9_we_i,
196
   wbs9_cyc_i,
197
   wbs9_stb_i,
198
   wbs9_cti_i,
199
   wbs9_bte_i,
200
   wbs9_dat_o,
201
   wbs9_ack_o,
202
   wbs9_err_o,
203
   wbs9_rty_o,
204
 
205
   // Slave eleven
206
   // Wishbone Slave interface
207
   wbs10_adr_i,
208
   wbs10_dat_i,
209
   wbs10_we_i,
210
   wbs10_cyc_i,
211
   wbs10_stb_i,
212
   wbs10_cti_i,
213
   wbs10_bte_i,
214
   wbs10_dat_o,
215
   wbs10_ack_o,
216
   wbs10_err_o,
217
   wbs10_rty_o,
218
 
219
   // Slave twelve
220
   // Wishbone Slave interface
221
   wbs11_adr_i,
222
   wbs11_dat_i,
223
   wbs11_we_i,
224
   wbs11_cyc_i,
225
   wbs11_stb_i,
226
   wbs11_cti_i,
227
   wbs11_bte_i,
228
   wbs11_dat_o,
229
   wbs11_ack_o,
230
   wbs11_err_o,
231
   wbs11_rty_o,
232
/*
233
   // Slave thirteen
234
   // Wishbone Slave interface
235
   wbs12_adr_i,
236
   wbs12_dat_i,
237
   wbs12_we_i,
238
   wbs12_cyc_i,
239
   wbs12_stb_i,
240
   wbs12_cti_i,
241
   wbs12_bte_i,
242
   wbs12_dat_o,
243
   wbs12_ack_o,
244
   wbs12_err_o,
245
   wbs12_rty_o,
246
 
247
    // Slave fourteen
248
    // Wishbone Slave interface
249
    wbs13_adr_i,
250
    wbs13_dat_i,
251
    wbs13_we_i,
252
    wbs13_cyc_i,
253
    wbs13_stb_i,
254
    wbs13_cti_i,
255
    wbs13_bte_i,
256
   wbs13_dat_o,
257
    wbs13_ack_o,
258
    wbs13_err_o,
259
    wbs13_rty_o,
260
 
261
    // Slave fifteen
262
    // Wishbone Slave interface
263
    wbs14_adr_i,
264
    wbs14_dat_i,
265
    wbs14_we_i,
266
    wbs14_cyc_i,
267
    wbs14_stb_i,
268
    wbs14_cti_i,
269
    wbs14_bte_i,
270
   wbs14_dat_o,
271
    wbs14_ack_o,
272
    wbs14_err_o,
273
    wbs14_rty_o,
274
 
275
    // Slave sixteen
276
    // Wishbone Slave interface
277
    wbs15_adr_i,
278
    wbs15_dat_i,
279
    wbs15_we_i,
280
    wbs15_cyc_i,
281
    wbs15_stb_i,
282
    wbs15_cti_i,
283
    wbs15_bte_i,
284
 
285
    wbs15_dat_o,
286
    wbs15_ack_o,
287
    wbs15_err_o,
288
    wbs15_rty_o,
289
 
290
    // Slave seventeen
291
    // Wishbone Slave interface
292
    wbs16_adr_i,
293
    wbs16_dat_i,
294
    wbs16_we_i,
295
    wbs16_cyc_i,
296
    wbs16_stb_i,
297
    wbs16_cti_i,
298
    wbs16_bte_i,
299
 
300
    wbs16_dat_o,
301
    wbs16_ack_o,
302
    wbs16_err_o,
303
    wbs16_rty_o,
304
 
305
 
306
    // Slave eighteen
307
    // Wishbone Slave interface
308
    wbs17_adr_i,
309
    wbs17_dat_i,
310
    wbs17_we_i,
311
    wbs17_cyc_i,
312
    wbs17_stb_i,
313
    wbs17_cti_i,
314
    wbs17_bte_i,
315
 
316
    wbs17_dat_o,
317
    wbs17_ack_o,
318
    wbs17_err_o,
319
    wbs17_rty_o,
320
 
321
    // Slave nineteen
322
    // Wishbone Slave interface
323
    wbs18_adr_i,
324
    wbs18_dat_i,
325
    wbs18_we_i,
326
    wbs18_cyc_i,
327
    wbs18_stb_i,
328
    wbs18_cti_i,
329
    wbs18_bte_i,
330
 
331
    wbs18_dat_o,
332
    wbs18_ack_o,
333
    wbs18_err_o,
334
    wbs18_rty_o,
335
 
336
    // Slave twenty
337
    // Wishbone Slave interface
338
    wbs19_adr_i,
339
    wbs19_dat_i,
340
    wbs19_we_i,
341
    wbs19_cyc_i,
342
    wbs19_stb_i,
343
    wbs19_cti_i,
344
    wbs19_bte_i,
345
 
346
    wbs19_dat_o,
347
    wbs19_ack_o,
348
    wbs19_err_o,
349
    wbs19_rty_o,
350
 
351
    */
352
 
353
   wb_clk, wb_rst
354
   );
355
 
356
 
357
   parameter wb_dat_width = 32;
358
   parameter wbs_dat_width = 8;
359
   parameter wb_adr_width = 32;
360
 
361
   parameter wb_addr_match_width = 8;
362
 
363
   parameter wb_num_slaves = 20; // Currently can handle up to 20
364
 
365
   // Slave addresses
366
 
367
   parameter slave0_adr =  8'h00;
368
   parameter slave1_adr =  8'h00;
369
   parameter slave2_adr =  8'h00;
370
   parameter slave3_adr =  8'h00;
371
   parameter slave4_adr =  8'h00;
372
   parameter slave5_adr =  8'h00;
373
   parameter slave6_adr =  8'h00;
374
   parameter slave7_adr =  8'h00;
375
   parameter slave8_adr =  8'h00;
376
   parameter slave9_adr =  8'h00;
377
   parameter slave10_adr = 8'h00;
378
   parameter slave11_adr = 8'h00;
379
   parameter slave12_adr = 8'h00;
380
   parameter slave13_adr = 8'h00;
381
   parameter slave14_adr = 8'h00;
382
   parameter slave15_adr = 8'h00;
383
   parameter slave16_adr = 8'h00;
384
   parameter slave17_adr = 8'h00;
385
   parameter slave18_adr = 8'h00;
386
   parameter slave19_adr = 8'h00;
387
 
388
 
389
`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
390
 
391
   input wb_clk;
392
   input wb_rst;
393
 
394
   // WB Master one
395
   input [wb_adr_width-1:0] wbm0_adr_o;
396
   input [wb_dat_width-1:0] wbm0_dat_o;
397
   input [3:0]               wbm0_sel_o;
398
   input                    wbm0_we_o;
399
   input                    wbm0_cyc_o;
400
   input                    wbm0_stb_o;
401
   input [2:0]               wbm0_cti_o;
402
   input [1:0]               wbm0_bte_o;
403
   output [wb_dat_width-1:0] wbm0_dat_i;
404
   output                    wbm0_ack_i;
405
   output                    wbm0_err_i;
406
   output                    wbm0_rty_i;
407
 
408
 
409
   // Slave one
410
   // Wishbone Slave interface
411
   output [wb_adr_width-1:0] wbs0_adr_i;
412
   output [wbs_dat_width-1:0] wbs0_dat_i;
413
   output                    wbs0_we_i;
414
   output                    wbs0_cyc_i;
415
   output                    wbs0_stb_i;
416
   output [2:0]       wbs0_cti_i;
417
   output [1:0]       wbs0_bte_i;
418
   input [wbs_dat_width-1:0]  wbs0_dat_o;
419
   input                     wbs0_ack_o;
420
   input                     wbs0_err_o;
421
   input                     wbs0_rty_o;
422
 
423
 
424
   // Wishbone Slave interface
425
   output [wb_adr_width-1:0] wbs1_adr_i;
426
   output [wbs_dat_width-1:0] wbs1_dat_i;
427
   output                    wbs1_we_i;
428
   output                    wbs1_cyc_i;
429
   output                    wbs1_stb_i;
430
   output [2:0]       wbs1_cti_i;
431
   output [1:0]       wbs1_bte_i;
432
   input [wbs_dat_width-1:0]  wbs1_dat_o;
433
   input                     wbs1_ack_o;
434
   input                     wbs1_err_o;
435
   input                     wbs1_rty_o;
436
 
437
 
438
   // Wishbone Slave interface
439
   output [wb_adr_width-1:0] wbs2_adr_i;
440
   output [wbs_dat_width-1:0] wbs2_dat_i;
441
   output                    wbs2_we_i;
442
   output                    wbs2_cyc_i;
443
   output                    wbs2_stb_i;
444
   output [2:0]       wbs2_cti_i;
445
   output [1:0]       wbs2_bte_i;
446
   input [wbs_dat_width-1:0]  wbs2_dat_o;
447
   input                     wbs2_ack_o;
448
   input                     wbs2_err_o;
449
   input                     wbs2_rty_o;
450
 
451
 
452
   // Wishbone Slave interface
453
   output [wb_adr_width-1:0] wbs3_adr_i;
454
   output [wbs_dat_width-1:0] wbs3_dat_i;
455
   output                    wbs3_we_i;
456
   output                    wbs3_cyc_i;
457
   output                    wbs3_stb_i;
458
   output [2:0]       wbs3_cti_i;
459
   output [1:0]       wbs3_bte_i;
460
   input [wbs_dat_width-1:0]  wbs3_dat_o;
461
   input                     wbs3_ack_o;
462
   input                     wbs3_err_o;
463
   input                     wbs3_rty_o;
464
 
465
 
466
   // Wishbone Slave interface
467
   output [wb_adr_width-1:0] wbs4_adr_i;
468
   output [wbs_dat_width-1:0] wbs4_dat_i;
469
   output                    wbs4_we_i;
470
   output                    wbs4_cyc_i;
471
   output                    wbs4_stb_i;
472
   output [2:0]       wbs4_cti_i;
473
   output [1:0]       wbs4_bte_i;
474
   input [wbs_dat_width-1:0]  wbs4_dat_o;
475
   input                     wbs4_ack_o;
476
   input                     wbs4_err_o;
477
   input                     wbs4_rty_o;
478
 
479
 
480
   // Wishbone Slave interface
481
   output [wb_adr_width-1:0] wbs5_adr_i;
482
   output [wbs_dat_width-1:0] wbs5_dat_i;
483
   output                    wbs5_we_i;
484
   output                    wbs5_cyc_i;
485
   output                    wbs5_stb_i;
486
   output [2:0]       wbs5_cti_i;
487
   output [1:0]       wbs5_bte_i;
488
   input [wbs_dat_width-1:0]  wbs5_dat_o;
489
   input                     wbs5_ack_o;
490
   input                     wbs5_err_o;
491
   input                     wbs5_rty_o;
492
 
493
 
494
   // Wishbone Slave interface
495
   output [wb_adr_width-1:0] wbs6_adr_i;
496
   output [wbs_dat_width-1:0] wbs6_dat_i;
497
   output                    wbs6_we_i;
498
   output                    wbs6_cyc_i;
499
   output                    wbs6_stb_i;
500
   output [2:0]       wbs6_cti_i;
501
   output [1:0]       wbs6_bte_i;
502
   input [wbs_dat_width-1:0]  wbs6_dat_o;
503
   input                     wbs6_ack_o;
504
   input                     wbs6_err_o;
505
   input                     wbs6_rty_o;
506
 
507
 
508
   // Wishbone Slave interface
509
   output [wb_adr_width-1:0] wbs7_adr_i;
510
   output [wbs_dat_width-1:0] wbs7_dat_i;
511
   output                    wbs7_we_i;
512
   output                    wbs7_cyc_i;
513
   output                    wbs7_stb_i;
514
   output [2:0]       wbs7_cti_i;
515
   output [1:0]       wbs7_bte_i;
516
   input [wbs_dat_width-1:0]  wbs7_dat_o;
517
   input                     wbs7_ack_o;
518
   input                     wbs7_err_o;
519
   input                     wbs7_rty_o;
520
 
521
 
522
   // Wishbone Slave interface
523
   output [wb_adr_width-1:0] wbs8_adr_i;
524
   output [wbs_dat_width-1:0] wbs8_dat_i;
525
   output                    wbs8_we_i;
526
   output                    wbs8_cyc_i;
527
   output                    wbs8_stb_i;
528
   output [2:0]       wbs8_cti_i;
529
   output [1:0]       wbs8_bte_i;
530
   input [wbs_dat_width-1:0]  wbs8_dat_o;
531
   input                     wbs8_ack_o;
532
   input                     wbs8_err_o;
533
   input                     wbs8_rty_o;
534
 
535
 
536
   // Wishbone Slave interface
537
   output [wb_adr_width-1:0] wbs9_adr_i;
538
   output [wbs_dat_width-1:0] wbs9_dat_i;
539
   output                    wbs9_we_i;
540
   output                    wbs9_cyc_i;
541
   output                    wbs9_stb_i;
542
   output [2:0]       wbs9_cti_i;
543
   output [1:0]       wbs9_bte_i;
544
   input [wbs_dat_width-1:0]  wbs9_dat_o;
545
   input                     wbs9_ack_o;
546
   input                     wbs9_err_o;
547
   input                     wbs9_rty_o;
548
 
549
 
550
   // Wishbone Slave interface
551
   output [wb_adr_width-1:0] wbs10_adr_i;
552
   output [wbs_dat_width-1:0] wbs10_dat_i;
553
   output                    wbs10_we_i;
554
   output                    wbs10_cyc_i;
555
   output                    wbs10_stb_i;
556
   output [2:0]       wbs10_cti_i;
557
   output [1:0]       wbs10_bte_i;
558
   input [wbs_dat_width-1:0]  wbs10_dat_o;
559
   input                     wbs10_ack_o;
560
   input                     wbs10_err_o;
561
   input                     wbs10_rty_o;
562
 
563
 
564
 // Wishbone Slave interface
565
   output [wb_adr_width-1:0] wbs11_adr_i;
566
   output [wbs_dat_width-1:0] wbs11_dat_i;
567
   output                    wbs11_we_i;
568
   output                    wbs11_cyc_i;
569
   output                    wbs11_stb_i;
570
   output [2:0]       wbs11_cti_i;
571
   output [1:0]       wbs11_bte_i;
572
   input [wbs_dat_width-1:0]  wbs11_dat_o;
573
   input                     wbs11_ack_o;
574
   input                     wbs11_err_o;
575
   input                     wbs11_rty_o;
576
/*
577
 
578
   // Wishbone Slave interface
579
   output [wb_adr_width-1:0] wbs12_adr_i;
580
   output [wbs_dat_width-1:0] wbs12_dat_i;
581
   output                     wbs12_we_i;
582
   output                     wbs12_cyc_i;
583
   output                     wbs12_stb_i;
584
   output [2:0]               wbs12_cti_i;
585
   output [1:0]               wbs12_bte_i;
586
   input [wbs_dat_width-1:0]  wbs12_dat_o;
587
   input                      wbs12_ack_o;
588
   input                      wbs12_err_o;
589
   input                      wbs12_rty_o;
590
 
591
   // Wishbone Slave interface
592
   output [wb_adr_width-1:0] wbs13_adr_i;
593
   output [wbs_dat_width-1:0] wbs13_dat_i;
594
   output                    wbs13_we_i;
595
   output                    wbs13_cyc_i;
596
   output                    wbs13_stb_i;
597
   output [2:0]              wbs13_cti_i;
598
   output [1:0]              wbs13_bte_i;
599
   input [wbs_dat_width-1:0]  wbs13_dat_o;
600
   input                     wbs13_ack_o;
601
   input                     wbs13_err_o;
602
   input                     wbs13_rty_o;
603
 
604
 
605
   // Wishbone Slave interface
606
   output [wb_adr_width-1:0] wbs14_adr_i;
607
   output [wbs_dat_width-1:0] wbs14_dat_i;
608
   output                    wbs14_we_i;
609
   output                    wbs14_cyc_i;
610
   output                    wbs14_stb_i;
611
   output [2:0]              wbs14_cti_i;
612
   output [1:0]              wbs14_bte_i;
613
   input [wbs_dat_width-1:0]  wbs14_dat_o;
614
   input                     wbs14_ack_o;
615
   input                     wbs14_err_o;
616
   input                     wbs14_rty_o;
617
 
618
 
619
   // Wishbone Slave interface
620
   output [wb_adr_width-1:0] wbs15_adr_i;
621
   output [wbs_dat_width-1:0] wbs15_dat_i;
622
   output                    wbs15_we_i;
623
   output                    wbs15_cyc_i;
624
   output                    wbs15_stb_i;
625
   output [2:0]              wbs15_cti_i;
626
   output [1:0]              wbs15_bte_i;
627
   input [wbs_dat_width-1:0]  wbs15_dat_o;
628
   input                     wbs15_ack_o;
629
   input                     wbs15_err_o;
630
   input                     wbs15_rty_o;
631
 
632
 
633
   // Wishbone Slave interface
634
   output [wb_adr_width-1:0] wbs16_adr_i;
635
   output [wbs_dat_width-1:0] wbs16_dat_i;
636
   output                    wbs16_we_i;
637
   output                    wbs16_cyc_i;
638
   output                    wbs16_stb_i;
639
   output [2:0]              wbs16_cti_i;
640
   output [1:0]              wbs16_bte_i;
641
   input [wbs_dat_width-1:0]  wbs16_dat_o;
642
   input                     wbs16_ack_o;
643
   input                     wbs16_err_o;
644
   input                     wbs16_rty_o;
645
 
646
 
647
   // Wishbone Slave interface
648
   output [wb_adr_width-1:0] wbs17_adr_i;
649
   output [wbs_dat_width-1:0] wbs17_dat_i;
650
   output                    wbs17_we_i;
651
   output                    wbs17_cyc_i;
652
   output                    wbs17_stb_i;
653
   output [2:0]              wbs17_cti_i;
654
   output [1:0]              wbs17_bte_i;
655
   input [wbs_dat_width-1:0]  wbs17_dat_o;
656
   input                     wbs17_ack_o;
657
   input                     wbs17_err_o;
658
   input                     wbs17_rty_o;
659
 
660
   // Wishbone Slave interface
661
   output [wb_adr_width-1:0] wbs18_adr_i;
662
   output [wbs_dat_width-1:0] wbs18_dat_i;
663
   output                    wbs18_we_i;
664
   output                    wbs18_cyc_i;
665
   output                    wbs18_stb_i;
666
   output [2:0]              wbs18_cti_i;
667
   output [1:0]              wbs18_bte_i;
668
   input [wbs_dat_width-1:0]  wbs18_dat_o;
669
   input                     wbs18_ack_o;
670
   input                     wbs18_err_o;
671
   input                     wbs18_rty_o;
672
 
673
   // Wishbone Slave interface
674
   output [wb_adr_width-1:0] wbs19_adr_i;
675
   output [wbs_dat_width-1:0] wbs19_dat_i;
676
   output                    wbs19_we_i;
677
   output                    wbs19_cyc_i;
678
   output                    wbs19_stb_i;
679
   output [2:0]              wbs19_cti_i;
680
   output [1:0]              wbs19_bte_i;
681
   input [wbs_dat_width-1:0]  wbs19_dat_o;
682
   input                     wbs19_ack_o;
683
   input                     wbs19_err_o;
684
   input                     wbs19_rty_o;
685
 */
686
 
687
   reg               watchdog_err;
688
 
689
   // Master input mux output wires
690
   wire [wb_adr_width-1:0]   wbm_adr_o;
691
   wire [wbs_dat_width-1:0]  wbm_dat_o;
692
   wire [3:0]                 wbm_sel_o;
693
   wire                      wbm_we_o;
694
   wire                      wbm_cyc_o;
695
   wire                      wbm_stb_o;
696
   wire [2:0]                 wbm_cti_o;
697
   wire [1:0]                 wbm_bte_o;
698
 
699
   wire [wbs_dat_width-1:0]   wbm_dat_byte_i;
700
   wire                      wbm_ack_i;
701
   wire                      wbm_err_i;
702
   wire                      wbm_rty_i;
703
 
704
 
705
   // Master input mux (not really used, only one master on this bus)
706
   assign wbm_adr_o = wbm0_adr_o;
707
 
708
   // Select the right byte and put it on the data out line
709
   // !BIG ENDIAN!
710
   assign wbm_dat_o = wbm0_sel_o[3] ? wbm0_dat_o[31:24] :
711
                      wbm0_sel_o[2] ? wbm0_dat_o[23:16] :
712
                      wbm0_sel_o[1] ? wbm0_dat_o[15:8] :
713
                      wbm0_dat_o[7:0];
714
 
715
   assign wbm_we_o = wbm0_we_o;
716
 
717
   assign wbm_cyc_o = wbm0_stb_o;
718
 
719
   assign wbm_stb_o = wbm0_stb_o;
720
 
721
   // Will we really need these for byte-peripherals
722
   assign wbm_cti_o = wbm0_cti_o;
723
 
724
   assign wbm_bte_o = wbm0_bte_o;
725
 
726
   // Signals back to the master
727
   assign wbm0_dat_i = (wbm0_sel_o[3]) ? {wbm_dat_byte_i, 24'd0} :
728
                       (wbm0_sel_o[2]) ? {8'd0, wbm_dat_byte_i, 16'd0} :
729
                       (wbm0_sel_o[1]) ? {16'd0, wbm_dat_byte_i, 8'd0} :
730
                       {24'd0, wbm_dat_byte_i};
731
 
732
   assign wbm0_ack_i = wbm_ack_i;
733
   assign wbm0_err_i = wbm_err_i;
734
   assign wbm0_rty_i = wbm_rty_i;
735
 
736
`ifdef ARBITER_BYTEBUS_WATCHDOG
737
   reg [`ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
738
   reg                       wbm_stb_r; // Register strobe
739
   wire                      wbm_stb_edge; // Detect its edge
740
 
741
   always @(posedge wb_clk)
742
     wbm_stb_r <= wbm_stb_o;
743
 
744
   assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
745
 
746
   // Counter logic
747
   always @(posedge wb_clk)
748
     if (wb_rst) watchdog_timer <= 0;
749
     else if (wbm_ack_i) // When we see an ack, turn off timer
750
       watchdog_timer <= 0;
751
     else if (wbm_stb_edge) // New access means start timer again
752
       watchdog_timer <= 1;
753
     else if (|watchdog_timer) // Continue counting if counter > 0
754
       watchdog_timer <= watchdog_timer + 1;
755
 
756
   always @(posedge wb_clk)
757
     watchdog_err <= (&watchdog_timer);
758
 
759
`else // !`ifdef ARBITER_BYTEBUS_WATCHDOG
760
   always @(posedge wb_clk)
761
     watchdog_err <= 0;
762
 
763
`endif // !`ifdef ARBITER_BYTEBUS_WATCHDOG
764
 
765
 
766
   // Wishbone slave mux out wires
767
   wire [wb_adr_width-1:0]   wbs_adr_i;
768
   wire [wbs_dat_width-1:0]  wbs_dat_i;
769
   wire                      wbs_we_i;
770
   wire                      wbs_cyc_i;
771
   wire                      wbs_stb_i;
772
   wire [2:0]                 wbs_cti_i;
773
   wire [1:0]                 wbs_bte_i;
774
   wire [wbs_dat_width-1:0]  wbs_dat_o;
775
   wire                      wbs_ack_o;
776
   wire                      wbs_err_o;
777
   wire                      wbs_rty_o;
778
 
779
 
780
   // Slave select wire
781
   wire [wb_num_slaves-1:0]  wb_slave_sel;
782
 
783
   // Slave out mux in wires   
784
   wire [wbs_dat_width-1:0]  wbs_dat_o_mux_i [0:wb_num_slaves-1];
785
   wire                      wbs_ack_o_mux_i [0:wb_num_slaves-1];
786
   wire                      wbs_err_o_mux_i [0:wb_num_slaves-1];
787
   wire                      wbs_rty_o_mux_i [0:wb_num_slaves-1];
788
 
789
   // Slave selects
790
   assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
791
   assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
792
   assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
793
   assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
794
   assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
795
   assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
796
   assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
797
   assign wb_slave_sel[7] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave7_adr;
798
   assign wb_slave_sel[8] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave8_adr;
799
   assign wb_slave_sel[9] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave9_adr;
800
   assign wb_slave_sel[10] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave10_adr;
801
   assign wb_slave_sel[11] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave11_adr;
802
      /*
803
   assign wb_slave_sel[12] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave12_adr;
804
   assign wb_slave_sel[13] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave13_adr;
805
   assign wb_slave_sel[14] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave14_adr;
806
   assign wb_slave_sel[15] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave15_adr;
807
   assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave16_adr;
808
   assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave17_adr;
809
   assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave18_adr;
810
   assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave19_adr;
811
   */
812
 
813
 
814
   // Assign master inputs to slaves and slave inputs for MUXing  back to master
815
 
816
   // Slave 0 inputs
817
   assign wbs0_adr_i = wbm_adr_o;
818
   assign wbs0_dat_i = wbm_dat_o;
819
   assign wbs0_cyc_i = wbm_cyc_o & wb_slave_sel[0];
820
   assign wbs0_stb_i = wbm_stb_o & wb_slave_sel[0];
821
   assign  wbs0_we_i =  wbm_we_o;
822
   assign wbs0_cti_i = wbm_cti_o;
823
   assign wbs0_bte_i = wbm_bte_o;
824
   assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
825
   assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0];
826
   assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
827
   assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];
828
 
829
 
830
   // Slave 1 inputs
831
   assign wbs1_adr_i = wbm_adr_o;
832
   assign wbs1_dat_i = wbm_dat_o;
833
   assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1];
834
   assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1];
835
   assign  wbs1_we_i =  wbm_we_o;
836
   assign wbs1_cti_i = wbm_cti_o;
837
   assign wbs1_bte_i = wbm_bte_o;
838
   assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
839
   assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1];
840
   assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
841
   assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];
842
 
843
 
844
   // Slave 2 inputs
845
   assign wbs2_adr_i = wbm_adr_o;
846
   assign wbs2_dat_i = wbm_dat_o;
847
   assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2];
848
   assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2];
849
   assign  wbs2_we_i =  wbm_we_o;
850
   assign wbs2_cti_i = wbm_cti_o;
851
   assign wbs2_bte_i = wbm_bte_o;
852
   assign wbs_dat_o_mux_i[2] = wbs2_dat_o;
853
   assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel[2];
854
   assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel[2];
855
   assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel[2];
856
 
857
 
858
   // Slave 3 inputs
859
   assign wbs3_adr_i = wbm_adr_o;
860
   assign wbs3_dat_i = wbm_dat_o;
861
   assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel[3];
862
   assign wbs3_stb_i = wbm_stb_o & wb_slave_sel[3];
863
   assign  wbs3_we_i =  wbm_we_o;
864
   assign wbs3_cti_i = wbm_cti_o;
865
   assign wbs3_bte_i = wbm_bte_o;
866
   assign wbs_dat_o_mux_i[3] = wbs3_dat_o;
867
   assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel[3];
868
   assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel[3];
869
   assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel[3];
870
 
871
 
872
   // Slave 4 inputs
873
   assign wbs4_adr_i = wbm_adr_o;
874
   assign wbs4_dat_i = wbm_dat_o;
875
   assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel[4];
876
   assign wbs4_stb_i = wbm_stb_o & wb_slave_sel[4];
877
   assign  wbs4_we_i =  wbm_we_o;
878
   assign wbs4_cti_i = wbm_cti_o;
879
   assign wbs4_bte_i = wbm_bte_o;
880
   assign wbs_dat_o_mux_i[4] = wbs4_dat_o;
881
   assign wbs_ack_o_mux_i[4] = wbs4_ack_o & wb_slave_sel[4];
882
   assign wbs_err_o_mux_i[4] = wbs4_err_o & wb_slave_sel[4];
883
   assign wbs_rty_o_mux_i[4] = wbs4_rty_o & wb_slave_sel[4];
884
 
885
 
886
   // Slave 5 inputs
887
   assign wbs5_adr_i = wbm_adr_o;
888
   assign wbs5_dat_i = wbm_dat_o;
889
   assign wbs5_cyc_i = wbm_cyc_o & wb_slave_sel[5];
890
   assign wbs5_stb_i = wbm_stb_o & wb_slave_sel[5];
891
   assign  wbs5_we_i =  wbm_we_o;
892
   assign wbs5_cti_i = wbm_cti_o;
893
   assign wbs5_bte_i = wbm_bte_o;
894
   assign wbs_dat_o_mux_i[5] = wbs5_dat_o;
895
   assign wbs_ack_o_mux_i[5] = wbs5_ack_o & wb_slave_sel[5];
896
   assign wbs_err_o_mux_i[5] = wbs5_err_o & wb_slave_sel[5];
897
   assign wbs_rty_o_mux_i[5] = wbs5_rty_o & wb_slave_sel[5];
898
 
899
 
900
   // Slave 6 inputs
901
   assign wbs6_adr_i = wbm_adr_o;
902
   assign wbs6_dat_i = wbm_dat_o;
903
   assign wbs6_cyc_i = wbm_cyc_o & wb_slave_sel[6];
904
   assign wbs6_stb_i = wbm_stb_o & wb_slave_sel[6];
905
   assign  wbs6_we_i =  wbm_we_o;
906
   assign wbs6_cti_i = wbm_cti_o;
907
   assign wbs6_bte_i = wbm_bte_o;
908
   assign wbs_dat_o_mux_i[6] = wbs6_dat_o;
909
   assign wbs_ack_o_mux_i[6] = wbs6_ack_o & wb_slave_sel[6];
910
   assign wbs_err_o_mux_i[6] = wbs6_err_o & wb_slave_sel[6];
911
   assign wbs_rty_o_mux_i[6] = wbs6_rty_o & wb_slave_sel[6];
912
 
913
 
914
   // Slave 7 inputs
915
   assign wbs7_adr_i = wbm_adr_o;
916
   assign wbs7_dat_i = wbm_dat_o;
917
   assign wbs7_cyc_i = wbm_cyc_o & wb_slave_sel[7];
918
   assign wbs7_stb_i = wbm_stb_o & wb_slave_sel[7];
919
   assign  wbs7_we_i =  wbm_we_o;
920
   assign wbs7_cti_i = wbm_cti_o;
921
   assign wbs7_bte_i = wbm_bte_o;
922
   assign wbs_dat_o_mux_i[7] = wbs7_dat_o;
923
   assign wbs_ack_o_mux_i[7] = wbs7_ack_o & wb_slave_sel[7];
924
   assign wbs_err_o_mux_i[7] = wbs7_err_o & wb_slave_sel[7];
925
   assign wbs_rty_o_mux_i[7] = wbs7_rty_o & wb_slave_sel[7];
926
 
927
 
928
   // Slave 8 inputs
929
   assign wbs8_adr_i = wbm_adr_o;
930
   assign wbs8_dat_i = wbm_dat_o;
931
   assign wbs8_cyc_i = wbm_cyc_o & wb_slave_sel[8];
932
   assign wbs8_stb_i = wbm_stb_o & wb_slave_sel[8];
933
   assign  wbs8_we_i =  wbm_we_o;
934
   assign wbs8_cti_i = wbm_cti_o;
935
   assign wbs8_bte_i = wbm_bte_o;
936
   assign wbs_dat_o_mux_i[8] = wbs8_dat_o;
937
   assign wbs_ack_o_mux_i[8] = wbs8_ack_o & wb_slave_sel[8];
938
   assign wbs_err_o_mux_i[8] = wbs8_err_o & wb_slave_sel[8];
939
   assign wbs_rty_o_mux_i[8] = wbs8_rty_o & wb_slave_sel[8];
940
 
941
 
942
   // Slave 9 inputs
943
   assign wbs9_adr_i = wbm_adr_o;
944
   assign wbs9_dat_i = wbm_dat_o;
945
   assign wbs9_cyc_i = wbm_cyc_o & wb_slave_sel[9];
946
   assign wbs9_stb_i = wbm_stb_o & wb_slave_sel[9];
947
   assign  wbs9_we_i =  wbm_we_o;
948
   assign wbs9_cti_i = wbm_cti_o;
949
   assign wbs9_bte_i = wbm_bte_o;
950
   assign wbs_dat_o_mux_i[9] = wbs9_dat_o;
951
   assign wbs_ack_o_mux_i[9] = wbs9_ack_o & wb_slave_sel[9];
952
   assign wbs_err_o_mux_i[9] = wbs9_err_o & wb_slave_sel[9];
953
   assign wbs_rty_o_mux_i[9] = wbs9_rty_o & wb_slave_sel[9];
954
 
955
 
956
   // Slave 10 inputs
957
   assign wbs10_adr_i = wbm_adr_o;
958
   assign wbs10_dat_i = wbm_dat_o;
959
   assign wbs10_cyc_i = wbm_cyc_o & wb_slave_sel[10];
960
   assign wbs10_stb_i = wbm_stb_o & wb_slave_sel[10];
961
   assign  wbs10_we_i =  wbm_we_o;
962
   assign wbs10_cti_i = wbm_cti_o;
963
   assign wbs10_bte_i = wbm_bte_o;
964
   assign wbs_dat_o_mux_i[10] = wbs10_dat_o;
965
   assign wbs_ack_o_mux_i[10] = wbs10_ack_o & wb_slave_sel[10];
966
   assign wbs_err_o_mux_i[10] = wbs10_err_o & wb_slave_sel[10];
967
   assign wbs_rty_o_mux_i[10] = wbs10_rty_o & wb_slave_sel[10];
968
 
969
 
970
   // Slave 11 inputs
971
   assign wbs11_adr_i = wbm_adr_o;
972
   assign wbs11_dat_i = wbm_dat_o;
973
   assign wbs11_cyc_i = wbm_cyc_o & wb_slave_sel[11];
974
   assign wbs11_stb_i = wbm_stb_o & wb_slave_sel[11];
975
   assign  wbs11_we_i =  wbm_we_o;
976
   assign wbs11_cti_i = wbm_cti_o;
977
   assign wbs11_bte_i = wbm_bte_o;
978
   assign wbs_dat_o_mux_i[11] = wbs11_dat_o;
979
   assign wbs_ack_o_mux_i[11] = wbs11_ack_o & wb_slave_sel[11];
980
   assign wbs_err_o_mux_i[11] = wbs11_err_o & wb_slave_sel[11];
981
   assign wbs_rty_o_mux_i[11] = wbs11_rty_o & wb_slave_sel[11];
982
   /*
983
   // Slave 12 inputs
984
   assign wbs12_adr_i = wbm_adr_o;
985
   assign wbs12_dat_i = wbm_dat_o;
986
   assign wbs12_cyc_i = wbm_cyc_o & wb_slave_sel[12];
987
   assign wbs12_stb_i = wbm_stb_o & wb_slave_sel[12];
988
   assign  wbs12_we_i =  wbm_we_o;
989
   assign wbs12_cti_i = wbm_cti_o;
990
   assign wbs12_bte_i = wbm_bte_o;
991
   assign wbs_dat_o_mux_i[12] = wbs12_dat_o;
992
   assign wbs_ack_o_mux_i[12] = wbs12_ack_o & wb_slave_sel[12];
993
   assign wbs_err_o_mux_i[12] = wbs12_err_o & wb_slave_sel[12];
994
   assign wbs_rty_o_mux_i[12] = wbs12_rty_o & wb_slave_sel[12];
995
 
996
 
997
   // Slave 13 inputs
998
   assign wbs13_adr_i = wbm_adr_o;
999
   assign wbs13_dat_i = wbm_dat_o;
1000
   assign wbs13_cyc_i = wbm_cyc_o & wb_slave_sel[13];
1001
   assign wbs13_stb_i = wbm_stb_o & wb_slave_sel[13];
1002
   assign  wbs13_we_i =  wbm_we_o;
1003
   assign wbs13_cti_i = wbm_cti_o;
1004
   assign wbs13_bte_i = wbm_bte_o;
1005
   assign wbs_dat_o_mux_i[13] = wbs13_dat_o;
1006
   assign wbs_ack_o_mux_i[13] = wbs13_ack_o & wb_slave_sel[13];
1007
   assign wbs_err_o_mux_i[13] = wbs13_err_o & wb_slave_sel[13];
1008
   assign wbs_rty_o_mux_i[13] = wbs13_rty_o & wb_slave_sel[13];
1009
 
1010
 
1011
   // Slave 14 inputs
1012
   assign wbs14_adr_i = wbm_adr_o;
1013
   assign wbs14_dat_i = wbm_dat_o;
1014
   assign wbs14_cyc_i = wbm_cyc_o & wb_slave_sel[14];
1015
   assign wbs14_stb_i = wbm_stb_o & wb_slave_sel[14];
1016
   assign  wbs14_we_i =  wbm_we_o;
1017
   assign wbs14_cti_i = wbm_cti_o;
1018
   assign wbs14_bte_i = wbm_bte_o;
1019
   assign wbs_dat_o_mux_i[14] = wbs14_dat_o;
1020
   assign wbs_ack_o_mux_i[14] = wbs14_ack_o & wb_slave_sel[14];
1021
   assign wbs_err_o_mux_i[14] = wbs14_err_o & wb_slave_sel[14];
1022
   assign wbs_rty_o_mux_i[14] = wbs14_rty_o & wb_slave_sel[14];
1023
 
1024
 
1025
   // Slave 15 inputs
1026
   assign wbs15_adr_i = wbm_adr_o;
1027
   assign wbs15_dat_i = wbm_dat_o;
1028
   assign wbs15_cyc_i = wbm_cyc_o & wb_slave_sel[15];
1029
   assign wbs15_stb_i = wbm_stb_o & wb_slave_sel[15];
1030
   assign  wbs15_we_i =  wbm_we_o;
1031
   assign wbs15_cti_i = wbm_cti_o;
1032
   assign wbs15_bte_i = wbm_bte_o;
1033
   assign wbs_dat_o_mux_i[15] = wbs15_dat_o;
1034
   assign wbs_ack_o_mux_i[15] = wbs15_ack_o & wb_slave_sel[15];
1035
   assign wbs_err_o_mux_i[15] = wbs15_err_o & wb_slave_sel[15];
1036
   assign wbs_rty_o_mux_i[15] = wbs15_rty_o & wb_slave_sel[15];
1037
 
1038
 
1039
   // Slave 16 inputs
1040
   assign wbs16_adr_i = wbm_adr_o;
1041
   assign wbs16_dat_i = wbm_dat_o;
1042
   assign wbs16_cyc_i = wbm_cyc_o & wb_slave_sel[16];
1043
   assign wbs16_stb_i = wbm_stb_o & wb_slave_sel[16];
1044
   assign  wbs16_we_i =  wbm_we_o;
1045
   assign wbs16_cti_i = wbm_cti_o;
1046
   assign wbs16_bte_i = wbm_bte_o;
1047
   assign wbs_dat_o_mux_i[16] = wbs16_dat_o;
1048
   assign wbs_ack_o_mux_i[16] = wbs16_ack_o & wb_slave_sel[16];
1049
   assign wbs_err_o_mux_i[16] = wbs16_err_o & wb_slave_sel[16];
1050
   assign wbs_rty_o_mux_i[16] = wbs16_rty_o & wb_slave_sel[16];
1051
 
1052
 
1053
   // Slave 17 inputs
1054
   assign wbs17_adr_i = wbm_adr_o;
1055
   assign wbs17_dat_i = wbm_dat_o;
1056
   assign wbs17_cyc_i = wbm_cyc_o & wb_slave_sel[17];
1057
   assign wbs17_stb_i = wbm_stb_o & wb_slave_sel[17];
1058
   assign  wbs17_we_i =  wbm_we_o;
1059
   assign wbs17_cti_i = wbm_cti_o;
1060
   assign wbs17_bte_i = wbm_bte_o;
1061
   assign wbs_dat_o_mux_i[17] = wbs17_dat_o;
1062
   assign wbs_ack_o_mux_i[17] = wbs17_ack_o & wb_slave_sel[17];
1063
   assign wbs_err_o_mux_i[17] = wbs17_err_o & wb_slave_sel[17];
1064
   assign wbs_rty_o_mux_i[17] = wbs17_rty_o & wb_slave_sel[17];
1065
 
1066
   // Slave 18 inputs
1067
   assign wbs18_adr_i = wbm_adr_o;
1068
   assign wbs18_dat_i = wbm_dat_o;
1069
   assign wbs18_cyc_i = wbm_cyc_o & wb_slave_sel[18];
1070
   assign wbs18_stb_i = wbm_stb_o & wb_slave_sel[18];
1071
   assign  wbs18_we_i =  wbm_we_o;
1072
   assign wbs18_cti_i = wbm_cti_o;
1073
   assign wbs18_bte_i = wbm_bte_o;
1074
   assign wbs_dat_o_mux_i[18] = wbs18_dat_o;
1075
   assign wbs_ack_o_mux_i[18] = wbs18_ack_o & wb_slave_sel[18];
1076
   assign wbs_err_o_mux_i[18] = wbs18_err_o & wb_slave_sel[18];
1077
   assign wbs_rty_o_mux_i[18] = wbs18_rty_o & wb_slave_sel[18];
1078
 
1079
   // Slave 19 inputs
1080
   assign wbs19_adr_i = wbm_adr_o;
1081
   assign wbs19_dat_i = wbm_dat_o;
1082
   assign wbs19_cyc_i = wbm_cyc_o & wb_slave_sel[19];
1083
   assign wbs19_stb_i = wbm_stb_o & wb_slave_sel[19];
1084
   assign  wbs19_we_i =  wbm_we_o;
1085
   assign wbs19_cti_i = wbm_cti_o;
1086
   assign wbs19_bte_i = wbm_bte_o;
1087
   assign wbs_dat_o_mux_i[19] = wbs19_dat_o;
1088
   assign wbs_ack_o_mux_i[19] = wbs19_ack_o & wb_slave_sel[19];
1089
   assign wbs_err_o_mux_i[19] = wbs19_err_o & wb_slave_sel[19];
1090
   assign wbs_rty_o_mux_i[19] = wbs19_rty_o & wb_slave_sel[19];
1091
 
1092
*/
1093
 
1094
 
1095
 
1096
   // Master out mux from slave in data
1097
   assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
1098
                      wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
1099
                      wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
1100
                      wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
1101
                      wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :
1102
                      wb_slave_sel[5] ? wbs_dat_o_mux_i[5] :
1103
                      wb_slave_sel[6] ? wbs_dat_o_mux_i[6] :
1104
                      wb_slave_sel[7] ? wbs_dat_o_mux_i[7] :
1105
                      wb_slave_sel[8] ? wbs_dat_o_mux_i[8] :
1106
                      wb_slave_sel[9] ? wbs_dat_o_mux_i[9] :
1107
                      wb_slave_sel[10] ? wbs_dat_o_mux_i[10] :
1108
                      wb_slave_sel[11] ? wbs_dat_o_mux_i[11] :
1109
                           /*
1110
                      wb_slave_sel[12] ? wbs_dat_o_mux_i[12] :
1111
                      wb_slave_sel[13] ? wbs_dat_o_mux_i[13] :
1112
                      wb_slave_sel[14] ? wbs_dat_o_mux_i[14] :
1113
                      wb_slave_sel[15] ? wbs_dat_o_mux_i[15] :
1114
                      wb_slave_sel[16] ? wbs_dat_o_mux_i[16] :
1115
                      wb_slave_sel[17] ? wbs_dat_o_mux_i[17] :
1116
                      wb_slave_sel[18] ? wbs_dat_o_mux_i[18] :
1117
                      wb_slave_sel[19] ? wbs_dat_o_mux_i[19] :
1118
*/
1119
                      wbs_dat_o_mux_i[0];
1120
   // Master out acks, or together
1121
   assign wbm_ack_i = wbs_ack_o_mux_i[0]  |
1122
                      wbs_ack_o_mux_i[1]  |
1123
                      wbs_ack_o_mux_i[2]  |
1124
                      wbs_ack_o_mux_i[3]  |
1125
                      wbs_ack_o_mux_i[4]  |
1126
                      wbs_ack_o_mux_i[5]  |
1127
                      wbs_ack_o_mux_i[6]  |
1128
                      wbs_ack_o_mux_i[7]  |
1129
                      wbs_ack_o_mux_i[8]  |
1130
                      wbs_ack_o_mux_i[9]  |
1131
                      wbs_ack_o_mux_i[10] |
1132
                      wbs_ack_o_mux_i[11] /* |
1133
                      wbs_ack_o_mux_i[12] |
1134
                      wbs_ack_o_mux_i[13] |
1135
                      wbs_ack_o_mux_i[14] |
1136
                      wbs_ack_o_mux_i[15] |
1137
                      wbs_ack_o_mux_i[16] |
1138
                      wbs_ack_o_mux_i[17] |
1139
                      wbs_ack_o_mux_i[18] |
1140
                      wbs_ack_o_mux_i[19]
1141
                      */
1142
                      ;
1143
 
1144
 
1145
   assign wbm_err_i = wbs_err_o_mux_i[0] |
1146
                      wbs_err_o_mux_i[1] |
1147
                      wbs_err_o_mux_i[2] |
1148
                      wbs_err_o_mux_i[3] |
1149
                      wbs_err_o_mux_i[4] |
1150
                      wbs_err_o_mux_i[5] |
1151
                      wbs_err_o_mux_i[6] |
1152
                      wbs_err_o_mux_i[7] |
1153
                      wbs_err_o_mux_i[8] |
1154
                      wbs_err_o_mux_i[9] |
1155
                      wbs_err_o_mux_i[10] |
1156
                      wbs_err_o_mux_i[11] |/*
1157
                      wbs_err_o_mux_i[12] |
1158
                      wbs_err_o_mux_i[13] |
1159
                      wbs_err_o_mux_i[14] |
1160
                      wbs_err_o_mux_i[15] |
1161
                      wbs_err_o_mux_i[16] |
1162
                      wbs_err_o_mux_i[17] |
1163
                      wbs_err_o_mux_i[18] |
1164
                      wbs_err_o_mux_i[19] |
1165
                                       */
1166
                      watchdog_err  ;
1167
 
1168
 
1169
   assign wbm_rty_i = wbs_rty_o_mux_i[0]  |
1170
                      wbs_rty_o_mux_i[1]  |
1171
                      wbs_rty_o_mux_i[2]  |
1172
                      wbs_rty_o_mux_i[3]  |
1173
                      wbs_rty_o_mux_i[4]  |
1174
                      wbs_rty_o_mux_i[5]  |
1175
                      wbs_rty_o_mux_i[6]  |
1176
                      wbs_rty_o_mux_i[7]  |
1177
                      wbs_rty_o_mux_i[8]  |
1178
                      wbs_rty_o_mux_i[9]  |
1179
                      wbs_rty_o_mux_i[10] |
1180
                      wbs_rty_o_mux_i[11] /*|
1181
                      wbs_rty_o_mux_i[12] |
1182
                      wbs_rty_o_mux_i[13] |
1183
                      wbs_rty_o_mux_i[14] |
1184
                      wbs_rty_o_mux_i[15] |
1185
                      wbs_rty_o_mux_i[16] |
1186
                      wbs_rty_o_mux_i[17] |
1187
                      wbs_rty_o_mux_i[18] |
1188
                      wbs_rty_o_mux_i[19]
1189
                       */
1190
                      ;
1191
 
1192
endmodule // arbiter_bytebus

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