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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [arbiter/] [arbiter_ibus.v] - Blame information for rev 485

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1 408 julius
//////////////////////////////////////////////////////////////////////
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///                                                               //// 
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/// Wishbone arbiter, burst-compatible                            ////
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///                                                               ////
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/// Simple arbiter, single master, dual slave, primarily for      ////
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/// processor instruction bus, providing access to one main       ////
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/// memory server and one ROM                                     ////
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///                                                               ////
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/// Julius Baxter, julius@opencores.org                           ////
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///                                                               ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "orpsoc-defines.v"
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// One master, 2 slaves.
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module arbiter_ibus
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  (
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   // instruction bus in
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   // Wishbone Master interface
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   wbm_adr_o,
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   wbm_dat_o,
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   wbm_sel_o,
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   wbm_we_o,
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   wbm_cyc_o,
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   wbm_stb_o,
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   wbm_cti_o,
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   wbm_bte_o,
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   wbm_dat_i,
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   wbm_ack_i,
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   wbm_err_i,
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   wbm_rty_i,
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   // Slave one
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   // Wishbone Slave interface
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   wbs0_adr_i,
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   wbs0_dat_i,
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   wbs0_sel_i,
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   wbs0_we_i,
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   wbs0_cyc_i,
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   wbs0_stb_i,
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   wbs0_cti_i,
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   wbs0_bte_i,
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   wbs0_dat_o,
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   wbs0_ack_o,
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   wbs0_err_o,
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   wbs0_rty_o,
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   // Slave two
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   // Wishbone Slave interface
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   wbs1_adr_i,
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   wbs1_dat_i,
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   wbs1_sel_i,
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   wbs1_we_i,
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   wbs1_cyc_i,
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   wbs1_stb_i,
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   wbs1_cti_i,
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   wbs1_bte_i,
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   wbs1_dat_o,
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   wbs1_ack_o,
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   wbs1_err_o,
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   wbs1_rty_o,
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90
   wb_clk,
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   wb_rst
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   );
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94
 
95
   parameter wb_dat_width = 32;
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   parameter wb_adr_width = 32;
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98
   parameter wb_addr_match_width = 8;
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100
   parameter slave0_adr = 8'hf0; // FLASH ROM
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   parameter slave1_adr = 8'h00; // Main memory (SDRAM/FPGA SRAM)
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`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
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105
   input wb_clk;
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   input wb_rst;
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108
 
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   // WB Master
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   input [wb_adr_width-1:0] wbm_adr_o;
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   input [wb_dat_width-1:0] wbm_dat_o;
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   input [3:0]               wbm_sel_o;
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   input                    wbm_we_o;
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   input                    wbm_cyc_o;
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   input                    wbm_stb_o;
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   input [2:0]               wbm_cti_o;
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   input [1:0]               wbm_bte_o;
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   output [wb_dat_width-1:0] wbm_dat_i;
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   output                    wbm_ack_i;
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   output                    wbm_err_i;
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   output                    wbm_rty_i;
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   // WB Slave 0
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   output [wb_adr_width-1:0] wbs0_adr_i;
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   output [wb_dat_width-1:0] wbs0_dat_i;
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   output [3:0]       wbs0_sel_i;
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   output                    wbs0_we_i;
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   output                    wbs0_cyc_i;
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   output                    wbs0_stb_i;
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   output [2:0]       wbs0_cti_i;
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   output [1:0]       wbs0_bte_i;
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   input [wb_dat_width-1:0]  wbs0_dat_o;
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   input                     wbs0_ack_o;
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   input                     wbs0_err_o;
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   input                     wbs0_rty_o;
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137
   // WB Slave 1
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   output [wb_adr_width-1:0] wbs1_adr_i;
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   output [wb_dat_width-1:0] wbs1_dat_i;
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   output [3:0]       wbs1_sel_i;
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   output                    wbs1_we_i;
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   output                    wbs1_cyc_i;
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   output                    wbs1_stb_i;
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   output [2:0]       wbs1_cti_i;
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   output [1:0]       wbs1_bte_i;
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   input [wb_dat_width-1:0]  wbs1_dat_o;
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   input                     wbs1_ack_o;
148
   input                     wbs1_err_o;
149
   input                     wbs1_rty_o;
150
 
151
   wire [1:0]                 slave_sel; // One bit per slave
152
 
153
   reg                       watchdog_err;
154
 
155
`ifdef ARBITER_IBUS_WATCHDOG
156
   reg [`ARBITER_IBUS_WATCHDOG_TIMER_WIDTH:0]  watchdog_timer;
157
   reg                       wbm_stb_r; // Register strobe
158
   wire                      wbm_stb_edge; // Detect its edge
159
   reg                       wbm_stb_edge_r, wbm_ack_i_r; // Reg these, better timing
160
 
161
   always @(posedge wb_clk)
162
     wbm_stb_r <= wbm_stb_o;
163
 
164
   assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
165
 
166
   always @(posedge wb_clk)
167
     wbm_stb_edge_r <= wbm_stb_edge;
168
 
169
   always @(posedge wb_clk)
170
     wbm_ack_i_r <= wbm_ack_i;
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172
 
173
   // Counter logic
174
   always @(posedge wb_clk)
175
     if (wb_rst) watchdog_timer <= 0;
176
     else if (wbm_ack_i_r) // When we see an ack, turn off timer
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       watchdog_timer <= 0;
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     else if (wbm_stb_edge_r) // New access means start timer again
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       watchdog_timer <= 1;
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     else if (|watchdog_timer) // Continue counting if counter > 0
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       watchdog_timer <= watchdog_timer + 1;
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183
   always @(posedge wb_clk)
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     watchdog_err <= (&watchdog_timer);
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186
`else // !`ifdef ARBITER_IBUS_WATCHDOG
187
 
188
   always @(posedge wb_clk)
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     watchdog_err <= 0;
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191
`endif // !`ifdef ARBITER_IBUS_WATCHDOG
192
 
193
 
194
 
195
`ifdef ARBITER_IBUS_REGISTERING
196
 
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   // Master input registers
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   reg [wb_adr_width-1:0]    wbm_adr_o_r;
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   reg [wb_dat_width-1:0]    wbm_dat_o_r;
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   reg [3:0]                  wbm_sel_o_r;
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   reg                       wbm_we_o_r;
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   reg                       wbm_cyc_o_r;
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   reg                       wbm_stb_o_r;
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   reg [2:0]                  wbm_cti_o_r;
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   reg [1:0]                  wbm_bte_o_r;
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   // Slave output registers
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   reg [wb_dat_width-1:0]    wbs0_dat_o_r;
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   reg                       wbs0_ack_o_r;
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   reg                       wbs0_err_o_r;
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   reg                       wbs0_rty_o_r;
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   reg [wb_dat_width-1:0]    wbs1_dat_o_r;
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   reg                       wbs1_ack_o_r;
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   reg                       wbs1_err_o_r;
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   reg                       wbs1_rty_o_r;
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   wire                      wbm_ack_i_pre_reg;
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220
   // Register master input signals
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   always @(posedge wb_clk)
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     begin
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        wbm_adr_o_r <= wbm_adr_o;
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        wbm_dat_o_r <= wbm_dat_o;
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        wbm_sel_o_r <= wbm_sel_o;
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        wbm_we_o_r <= wbm_we_o;
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        wbm_cyc_o_r <= wbm_cyc_o;
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        wbm_stb_o_r <= wbm_stb_o & !wbm_ack_i_pre_reg & !wbm_ack_i;//classic
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        wbm_cti_o_r <= wbm_cti_o;
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        wbm_bte_o_r <= wbm_bte_o;
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        // Slave signals
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        wbs0_dat_o_r <= wbs0_dat_o;
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        wbs0_ack_o_r <= wbs0_ack_o;
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        wbs0_err_o_r <= wbs0_err_o;
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        wbs0_rty_o_r <= wbs0_rty_o;
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        wbs1_dat_o_r <= wbs1_dat_o;
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        wbs1_ack_o_r <= wbs1_ack_o;
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        wbs1_err_o_r <= wbs1_err_o;
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        wbs1_rty_o_r <= wbs1_rty_o;
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     end // always @ (posedge wb_clk)
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   // Slave select
245
   assign slave_sel[0] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
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                         slave0_adr;
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   assign slave_sel[1] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
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                         slave1_adr;
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   // Slave out assigns
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   assign wbs0_adr_i = wbm_adr_o_r;
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   assign wbs0_dat_i = wbm_dat_o_r;
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   assign wbs0_we_i = wbm_dat_o_r;
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   assign wbs0_sel_i = wbm_sel_o_r;
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   assign wbs0_cti_i = wbm_cti_o_r;
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   assign wbs0_bte_i = wbm_bte_o_r;
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   assign wbs0_cyc_i = wbm_cyc_o_r & slave_sel[0];
259
   assign wbs0_stb_i = wbm_stb_o_r & slave_sel[0];
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   assign wbs1_adr_i = wbm_adr_o_r;
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   assign wbs1_dat_i = wbm_dat_o_r;
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   assign wbs1_we_i = wbm_dat_o_r;
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   assign wbs1_sel_i = wbm_sel_o_r;
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   assign wbs1_cti_i = wbm_cti_o_r;
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   assign wbs1_bte_i = wbm_bte_o_r;
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   assign wbs1_cyc_i = wbm_cyc_o_r & slave_sel[1];
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   assign wbs1_stb_i = wbm_stb_o_r & slave_sel[1];
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270
   // Master out assigns
271
   // Don't care about none selected...
272
   assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o_r :
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                      wbs0_dat_o_r ;
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275
   assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o_r) |
276
                      (slave_sel[1] & wbs1_ack_o_r)
277
     ;
278
 
279
   assign wbm_err_i = (slave_sel[0] & wbs0_err_o_r) |
280
                      (slave_sel[1] & wbs1_err_o_r) |
281
                      watchdog_err;
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283
   assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o_r) |
284
                      (slave_sel[1] & wbs1_rty_o_r);
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286
   // Non-registered ack
287
   assign wbm_ack_i_pre_reg = (slave_sel[0] & wbs0_ack_o) |
288
                              (slave_sel[1] & wbs1_ack_o);
289
 
290
`else // !`ifdef ARBITER_IBUS_REGISTERING
291
 
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   // Slave select
293
   assign slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
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                         slave0_adr;
295
 
296
   assign slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
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                         slave1_adr;
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   // Slave out assigns
300
   assign wbs0_adr_i = wbm_adr_o;
301
   assign wbs0_dat_i = wbm_dat_o;
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   assign wbs0_we_i  = wbm_we_o;
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   assign wbs0_sel_i = wbm_sel_o;
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   assign wbs0_cti_i = wbm_cti_o;
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   assign wbs0_bte_i = wbm_bte_o;
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   assign wbs0_cyc_i = wbm_cyc_o & slave_sel[0];
307
   assign wbs0_stb_i = wbm_stb_o & slave_sel[0];
308
 
309
   assign wbs1_adr_i = wbm_adr_o;
310
   assign wbs1_dat_i = wbm_dat_o;
311
   assign wbs1_we_i  = wbm_we_o;
312
   assign wbs1_sel_i = wbm_sel_o;
313
   assign wbs1_cti_i = wbm_cti_o;
314
   assign wbs1_bte_i = wbm_bte_o;
315
   assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1];
316
   assign wbs1_stb_i = wbm_stb_o & slave_sel[1];
317
 
318
   // Master out assigns
319
   // Don't care about none selected...
320
   assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o :
321
                      wbs0_dat_o ;
322
 
323
   assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) |
324
                      (slave_sel[1] & wbs1_ack_o);
325
 
326
 
327
   assign wbm_err_i = (slave_sel[0] & wbs0_err_o) |
328
                      (slave_sel[1] & wbs1_err_o) |
329
                      watchdog_err;
330
 
331
   assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) |
332
                      (slave_sel[1] & wbs1_rty_o);
333
 
334
 
335
`endif
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endmodule // arbiter_ibus
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