URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [clkgen/] [clkgen.v] - Blame information for rev 485

Go to most recent revision | Details | Compare with Previous | View Log


/*
 *
 * Clock, reset generation unit
 *
 * Implements clock generation according to design defines
 *
 */
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "orpsoc-defines.v"
`include "synthesis-defines.v"
 
module clkgen
  (
   // Main clocks in, depending on board
   sys_clk_pad_i,
 
   // Wishbone clock and reset out  
   wb_clk_o,
   wb_rst_o,
 
   // JTAG clock
`ifdef JTAG_DEBUG
   tck_pad_i,
   dbg_tck_o,
`endif
   // Main memory clocks
`ifdef VERSATILE_SDRAM
   sdram_clk_o,
   sdram_rst_o,
`endif
   // Peripheral clocks
`ifdef ETH_CLK
   eth_clk_pad_i,
   eth_clk_o,
   eth_rst_o,
 `endif
 
`ifdef USB_CLK
   usb_clk_o,
`endif
 
   // Asynchronous, active low reset in
   rst_n_pad_i
 
   );
 
   input sys_clk_pad_i;
 
   output wb_rst_o;
   output wb_clk_o;
 
`ifdef JTAG_DEBUG
   input  tck_pad_i;
   output dbg_tck_o;
`endif
 
`ifdef VERSATILE_SDRAM
   output sdram_clk_o;
   output sdram_rst_o;
`endif
 
`ifdef ETH_CLK
   input  eth_clk_pad_i;
   output eth_clk_o;
   output eth_rst_o;
`endif
 
`ifdef USB_CLK
   output usb_clk_o;
`endif
 
   // Asynchronous, active low reset (pushbutton, typically)
   input  rst_n_pad_i;
 
   // First, deal with the asychronous reset
   wire   async_rst;
   wire   async_rst_n;
 
   reset_buffer reset_gbuf
     (
      .GL(async_rst_n),
      .CLK(rst_n_pad_i)
      );
 
   // Everyone likes active-high reset signals...
   assign async_rst = ~async_rst_n;
 
 
`ifdef JTAG_DEBUG
   gbuf dbg_tck_gbuf
     (
      .CLK(tck_pad_i),
      .GL(dbg_tck_o)
      );
`endif
 
   //
   // Declare synchronous reset wires here
   //
 
   // An active-low synchronous reset signal (usually a PLL lock signal)
   wire   sync_rst_n;
 
   // An active-low synchronous reset from ethernet PLL
   wire   sync_eth_rst_n;
 
 
`ifdef ACTEL_PLL
 `ifdef SYNTHESIS
   wire   pll_lock;
   wire   eth_pll_lock;
 
  `ifdef PLL_XTAL64_WB36
   pll_xtal64_wb36
  `endif
  `ifdef PLL_XTAL64_WB32
   pll_xtal64_wb32
  `endif
  `ifdef PLL_XTAL64_WB30
   pll_xtal64_wb30
  `endif
  `ifdef PLL_XTAL64_WB24
   pll_xtal64_wb24
  `endif
  `ifdef PLL_XTAL64_WB20
   pll_xtal64_wb20
  `endif
  `ifdef PLL_XTAL64_WB18
   pll_xtal64_wb18
  `endif
  `ifdef PLL_XTAL64_WB16
   pll_xtal64_wb16
  `endif
  `ifdef PLL_XTAL25_WB24
   pll_xtal25_wb24
  `endif
  `ifdef PLL_XTAL25_WB20
   pll_xtal25_wb20
  `endif
 
     pll0
     (
      .POWERDOWN(1'b1),
      .CLKA(sys_clk_pad_i),
      .LOCK(pll_lock),
 
  `ifdef VERSATILE_SDRAM
      .GLA(sdram_clk_o),
  `else
      .GLA(),
  `endif
 
      .GLB(wb_clk_o),
 
  `ifdef USB_CLK
      .GLC(usb_clk_o)
  `else
      .GLC()
  `endif
      );
 
   assign sync_rst_n = pll_lock;
 
  `ifdef ETH_CLK
   `ifdef ETH_CLK_PLL
 
   eth_pll eth_pll0
     (
      .POWERDOWN(1'b1),
      .CLKA(eth_clk_pad_i),
      .LOCK(eth_pll_lock),
      .GLA(eth_clk_o)
      );
   `else
   // Just instantiate global buffer for incoming ethernet clock
   gbuf eth_clk_gbuf
     (
      .CLK(eth_clk_pad_i),
      .GL(eth_clk_o)
      );
   assign eth_pll_lock = 1'b1;
   `endif // !`ifdef ETH_CLK_PLL
  `endif
 
   assign sync_eth_rst_n = eth_pll_lock;
 
 `else // !`ifdef SYNTHESIS
   // Buggy looking Actel PLL simulation model  (it was drifting when 
   // generating certain frequencies) so we will generate our own during 
   // simulation.
 
   reg    wb_clk_gen = 0;
   reg    usb_clk_gen = 0;
 
   // Delay on Actel PLLs for SDRAM clock (GLA) is 0.200ns
   parameter Tskew_actel_pll_gla = 0.200;
   assign #Tskew_actel_pll_gla sdram_clk_o  = sys_clk_pad_i;
 
   always
     #((`ACTEL_PLL_CLKB_PERIOD)/2) wb_clk_gen <=  async_rst ? 0 : ~wb_clk_gen;
 
   always
     #((`ACTEL_PLL_CLKC_PERIOD)/2) usb_clk_gen <=  async_rst ? 0 : ~usb_clk_gen;
 
   assign wb_clk_o = wb_clk_gen;
 
  `ifdef USB_CLK
   assign usb_clk_o = usb_clk_gen;
  `endif
 
  `ifdef ETH_CLK
   `ifdef ETH_CLK_PLL
   // Ethernet clock is 125MHz on ORSoC dev board 
   // PLL set to -0.06ns delay model this here
 
   wire   eth_clk, eth_clk_dly1, eth_clk_dly2;
   assign #3.5 eth_clk_dly1 = eth_clk_pad_i;
   assign #3.5 eth_clk_dly2 = eth_clk_dly1;
   assign #(1 - 0.06)eth_clk = eth_clk_dly2;
   assign eth_clk_o = eth_clk;
   `else
 
   assign eth_clk_o = eth_clk_pad_i;
 
   `endif // !`ifdef ETH_CLK_PLL
  `endif //  `ifdef ETH_CLK
 
 
 
   reg    pll_lock = 0;
   reg    eth_pll_lock = 1;
 
   always @(async_rst)
     if (async_rst)
       pll_lock = 0;
     else
       #300 pll_lock = 1;
 
   // Assign synchronous resets
   assign sync_rst_n = pll_lock;
   assign sync_eth_rst_n = eth_pll_lock;
 
 
 `endif // !`ifdef SYNTHESIS
`endif //  `ifdef ACTEL_PLL
 
   //
   // Reset generation
   //
   //
 
 
   // Reset generation for wishbone
   reg [15:0]       wb_rst_shr;
   always @(posedge wb_clk_o or posedge async_rst)
     if (async_rst)
       wb_rst_shr <= 16'hffff;
     else
       wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
 
   assign wb_rst_o = wb_rst_shr[15];
 
 
 
`ifdef VERSATILE_SDRAM
   // Reset generation for SDRAM controller
   reg [15:0]       sdram_rst_shr;
   always @(posedge sdram_clk_o or posedge async_rst)
     if (async_rst)
       sdram_rst_shr <= 16'hffff;
     else
       sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};
 
   assign sdram_rst_o = sdram_rst_shr[15];
`endif //  `ifdef VERSATILE_SDRAM
 
`ifdef ETH_CLK
   // Reset generation for ethernet SMII
   reg [15:0]       eth_rst_shr;
   always @(posedge eth_clk_o or posedge async_rst)
     if (async_rst)
       eth_rst_shr <= 16'hffff;
     else
       eth_rst_shr <= {eth_rst_shr[14:0], ~(sync_eth_rst_n)};
 
   assign eth_rst_o = eth_rst_shr[15];
`endif //  `ifdef ETH_CLK
 
endmodule // clkgen

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [clkgen/] [clkgen.v] - Blame information for rev 485

Line No.	Rev	Author	Line
1	408	julius	`/*`
2			`*`
3			`* Clock, reset generation unit`
4			`*`
5			`* Implements clock generation according to design defines`
6			`*`
7			`*/`
8			`//////////////////////////////////////////////////////////////////////`
9			`//// ////`
10			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
11			`//// ////`
12			`//// This source file may be used and distributed without ////`
13			`//// restriction provided that this copyright statement is not ////`
14			`//// removed from the file and that any derivative work contains ////`
15			`//// the original copyright notice and the associated disclaimer. ////`
16			`//// ////`
17			`//// This source file is free software; you can redistribute it ////`
18			`//// and/or modify it under the terms of the GNU Lesser General ////`
19			`//// Public License as published by the Free Software Foundation; ////`
20			`//// either version 2.1 of the License, or (at your option) any ////`
21			`//// later version. ////`
22			`//// ////`
23			`//// This source is distributed in the hope that it will be ////`
24			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
25			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
26			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
27			`//// details. ////`
28			`//// ////`
29			`//// You should have received a copy of the GNU Lesser General ////`
30			`//// Public License along with this source; if not, download it ////`
31			`//// from http://www.opencores.org/lgpl.shtml ////`
32			`//// ////`
33			`//////////////////////////////////////////////////////////////////////`
34
35			`include "timescale.v"
36			`include "orpsoc-defines.v"
37			`include "synthesis-defines.v"
38
39			`module clkgen`
40			`(`
41			`// Main clocks in, depending on board`
42			`sys_clk_pad_i,`
43
44			`// Wishbone clock and reset out`
45			`wb_clk_o,`
46			`wb_rst_o,`
47
48			`// JTAG clock`
49			`ifdef JTAG_DEBUG
50			`tck_pad_i,`
51			`dbg_tck_o,`
52			`endif
53			`// Main memory clocks`
54			`ifdef VERSATILE_SDRAM
55			`sdram_clk_o,`
56			`sdram_rst_o,`
57			`endif
58			`// Peripheral clocks`
59			`ifdef ETH_CLK
60			`eth_clk_pad_i,`
61			`eth_clk_o,`
62			`eth_rst_o,`
63			`endif
64
65			`ifdef USB_CLK
66			`usb_clk_o,`
67			`endif
68
69			`// Asynchronous, active low reset in`
70			`rst_n_pad_i`
71
72			`);`
73
74			`input sys_clk_pad_i;`
75
76			`output wb_rst_o;`
77			`output wb_clk_o;`
78
79			`ifdef JTAG_DEBUG
80			`input tck_pad_i;`
81			`output dbg_tck_o;`
82			`endif
83
84			`ifdef VERSATILE_SDRAM
85			`output sdram_clk_o;`
86			`output sdram_rst_o;`
87			`endif
88
89			`ifdef ETH_CLK
90			`input eth_clk_pad_i;`
91			`output eth_clk_o;`
92			`output eth_rst_o;`
93			`endif
94
95			`ifdef USB_CLK
96			`output usb_clk_o;`
97			`endif
98
99			`// Asynchronous, active low reset (pushbutton, typically)`
100			`input rst_n_pad_i;`
101
102			`// First, deal with the asychronous reset`
103			`wire async_rst;`
104			`wire async_rst_n;`
105
106			`reset_buffer reset_gbuf`
107			`(`
108			`.GL(async_rst_n),`
109			`.CLK(rst_n_pad_i)`
110			`);`
111
112			`// Everyone likes active-high reset signals...`
113			`assign async_rst = ~async_rst_n;`
114
115
116			`ifdef JTAG_DEBUG
117			`gbuf dbg_tck_gbuf`
118			`(`
119			`.CLK(tck_pad_i),`
120			`.GL(dbg_tck_o)`
121			`);`
122			`endif
123
124			`//`
125			`// Declare synchronous reset wires here`
126			`//`
127
128			`// An active-low synchronous reset signal (usually a PLL lock signal)`
129			`wire sync_rst_n;`
130
131			`// An active-low synchronous reset from ethernet PLL`
132			`wire sync_eth_rst_n;`
133
134
135			`ifdef ACTEL_PLL
136			`ifdef SYNTHESIS
137			`wire pll_lock;`
138			`wire eth_pll_lock;`
139
140			`ifdef PLL_XTAL64_WB36
141			`pll_xtal64_wb36`
142			`endif
143			`ifdef PLL_XTAL64_WB32
144			`pll_xtal64_wb32`
145			`endif
146			`ifdef PLL_XTAL64_WB30
147			`pll_xtal64_wb30`
148			`endif
149			`ifdef PLL_XTAL64_WB24
150			`pll_xtal64_wb24`
151			`endif
152			`ifdef PLL_XTAL64_WB20
153			`pll_xtal64_wb20`
154			`endif
155			`ifdef PLL_XTAL64_WB18
156			`pll_xtal64_wb18`
157			`endif
158			`ifdef PLL_XTAL64_WB16
159			`pll_xtal64_wb16`
160			`endif
161			`ifdef PLL_XTAL25_WB24
162			`pll_xtal25_wb24`
163			`endif
164			`ifdef PLL_XTAL25_WB20
165			`pll_xtal25_wb20`
166			`endif
167
168			`pll0`
169			`(`
170			`.POWERDOWN(1'b1),`
171			`.CLKA(sys_clk_pad_i),`
172			`.LOCK(pll_lock),`
173
174			`ifdef VERSATILE_SDRAM
175			`.GLA(sdram_clk_o),`
176			`else
177			`.GLA(),`
178			`endif
179
180			`.GLB(wb_clk_o),`
181
182			`ifdef USB_CLK
183			`.GLC(usb_clk_o)`
184			`else
185			`.GLC()`
186			`endif
187			`);`
188
189			`assign sync_rst_n = pll_lock;`
190
191			`ifdef ETH_CLK
192			`ifdef ETH_CLK_PLL
193
194			`eth_pll eth_pll0`
195			`(`
196			`.POWERDOWN(1'b1),`
197			`.CLKA(eth_clk_pad_i),`
198			`.LOCK(eth_pll_lock),`
199			`.GLA(eth_clk_o)`
200			`);`
201			`else
202			`// Just instantiate global buffer for incoming ethernet clock`
203			`gbuf eth_clk_gbuf`
204			`(`
205			`.CLK(eth_clk_pad_i),`
206			`.GL(eth_clk_o)`
207			`);`
208			`assign eth_pll_lock = 1'b1;`
209			`endif // !`ifdef ETH_CLK_PLL
210			`endif
211
212			`assign sync_eth_rst_n = eth_pll_lock;`
213
214			`else // !`ifdef SYNTHESIS
215			`// Buggy looking Actel PLL simulation model (it was drifting when`
216			`// generating certain frequencies) so we will generate our own during`
217			`// simulation.`
218
219			`reg wb_clk_gen = 0;`
220			`reg usb_clk_gen = 0;`
221
222			`// Delay on Actel PLLs for SDRAM clock (GLA) is 0.200ns`
223			`parameter Tskew_actel_pll_gla = 0.200;`
224			`assign #Tskew_actel_pll_gla sdram_clk_o = sys_clk_pad_i;`
225
226			`always`
227			#((`ACTEL_PLL_CLKB_PERIOD)/2) wb_clk_gen <= async_rst ? 0 : ~wb_clk_gen;
228
229			`always`
230			#((`ACTEL_PLL_CLKC_PERIOD)/2) usb_clk_gen <= async_rst ? 0 : ~usb_clk_gen;
231
232			`assign wb_clk_o = wb_clk_gen;`
233
234			`ifdef USB_CLK
235			`assign usb_clk_o = usb_clk_gen;`
236			`endif
237
238			`ifdef ETH_CLK
239			`ifdef ETH_CLK_PLL
240			`// Ethernet clock is 125MHz on ORSoC dev board`
241			`// PLL set to -0.06ns delay model this here`
242
243			`wire eth_clk, eth_clk_dly1, eth_clk_dly2;`
244			`assign #3.5 eth_clk_dly1 = eth_clk_pad_i;`
245			`assign #3.5 eth_clk_dly2 = eth_clk_dly1;`
246			`assign #(1 - 0.06)eth_clk = eth_clk_dly2;`
247			`assign eth_clk_o = eth_clk;`
248			`else
249
250			`assign eth_clk_o = eth_clk_pad_i;`
251
252			`endif // !`ifdef ETH_CLK_PLL
253			`endif // `ifdef ETH_CLK
254
255
256
257			`reg pll_lock = 0;`
258			`reg eth_pll_lock = 1;`
259
260			`always @(async_rst)`
261			`if (async_rst)`
262			`pll_lock = 0;`
263			`else`
264			`#300 pll_lock = 1;`
265
266			`// Assign synchronous resets`
267			`assign sync_rst_n = pll_lock;`
268			`assign sync_eth_rst_n = eth_pll_lock;`
269
270
271			`endif // !`ifdef SYNTHESIS
272			`endif // `ifdef ACTEL_PLL
273
274			`//`
275			`// Reset generation`
276			`//`
277			`//`
278
279
280			`// Reset generation for wishbone`
281			`reg [15:0] wb_rst_shr;`
282			`always @(posedge wb_clk_o or posedge async_rst)`
283			`if (async_rst)`
284			`wb_rst_shr <= 16'hffff;`
285			`else`
286			`wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};`
287
288			`assign wb_rst_o = wb_rst_shr[15];`
289
290
291
292			`ifdef VERSATILE_SDRAM
293			`// Reset generation for SDRAM controller`
294			`reg [15:0] sdram_rst_shr;`
295			`always @(posedge sdram_clk_o or posedge async_rst)`
296			`if (async_rst)`
297			`sdram_rst_shr <= 16'hffff;`
298			`else`
299			`sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};`
300
301			`assign sdram_rst_o = sdram_rst_shr[15];`
302			`endif // `ifdef VERSATILE_SDRAM
303
304			`ifdef ETH_CLK
305			`// Reset generation for ethernet SMII`
306			`reg [15:0] eth_rst_shr;`
307			`always @(posedge eth_clk_o or posedge async_rst)`
308			`if (async_rst)`
309			`eth_rst_shr <= 16'hffff;`
310			`else`
311			`eth_rst_shr <= {eth_rst_shr[14:0], ~(sync_eth_rst_n)};`
312
313			`assign eth_rst_o = eth_rst_shr[15];`
314			`endif // `ifdef ETH_CLK
315
316			`endmodule // clkgen`