URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [clkgen/] [clkgen.v] - Blame information for rev 544

Details | Compare with Previous | View Log


/*
 *
 * Clock, reset generation unit
 *
 * Implements clock generation according to design defines
 *
 */
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "orpsoc-defines.v"
`include "synthesis-defines.v"
 
module clkgen
  (
   // Main clocks in, depending on board
   sys_clk_pad_i,
 
   // Wishbone clock and reset out  
   wb_clk_o,
   wb_rst_o,
 
   // JTAG clock
`ifdef JTAG_DEBUG
   tck_pad_i,
   dbg_tck_o,
`endif
   // Main memory clocks
`ifdef VERSATILE_SDRAM
   sdram_clk_o,
   sdram_rst_o,
`endif
   // Peripheral clocks
`ifdef ETH_CLK
   eth_clk_pad_i,
   eth_clk_o,
   eth_rst_o,
 `endif
 
`ifdef USB_CLK
   usb_clk_o,
`endif
 
   // Asynchronous, active low reset in
   rst_n_pad_i
 
   );
 
   input sys_clk_pad_i;
 
   output wb_rst_o;
   output wb_clk_o;
 
`ifdef JTAG_DEBUG
   input  tck_pad_i;
   output dbg_tck_o;
`endif
 
`ifdef VERSATILE_SDRAM
   output sdram_clk_o;
   output sdram_rst_o;
`endif
 
`ifdef ETH_CLK
   input  eth_clk_pad_i;
   output eth_clk_o;
   output eth_rst_o;
`endif
 
`ifdef USB_CLK
   output usb_clk_o;
`endif
 
   // Asynchronous, active low reset (pushbutton, typically)
   input  rst_n_pad_i;
 
   // First, deal with the asychronous reset
   wire   async_rst;
   wire   async_rst_n;
 
   assign async_rst_n  = rst_n_pad_i;
 
   // Everyone likes active-high reset signals...
   assign async_rst = ~async_rst_n;
 
 
`ifdef JTAG_DEBUG
   assign  dbg_tck_o = tck_pad_i;
`endif
 
   //
   // Declare synchronous reset wires here
   //
 
   // An active-low synchronous reset signal (usually a PLL lock signal)
   wire   sync_rst_n;
 
   // An active-low synchronous reset from ethernet PLL
   wire   sync_eth_rst_n;
 
 
`ifdef ACTEL_PLL
 `ifdef SYNTHESIS
   wire   pll_lock;
   wire   eth_pll_lock;
 
  `ifdef PLL_XTAL64_WB36
   pll_xtal64_wb36
  `endif
  `ifdef PLL_XTAL64_WB32
   pll_xtal64_wb32
  `endif
  `ifdef PLL_XTAL64_WB30
   pll_xtal64_wb30
  `endif
  `ifdef PLL_XTAL64_WB24
   pll_xtal64_wb24
  `endif
  `ifdef PLL_XTAL64_WB20
   pll_xtal64_wb20
  `endif
  `ifdef PLL_XTAL64_WB18
   pll_xtal64_wb18
  `endif
  `ifdef PLL_XTAL64_WB16
   pll_xtal64_wb16
  `endif
  `ifdef PLL_XTAL25_WB24
   pll_xtal25_wb24
  `endif
  `ifdef PLL_XTAL25_WB20
   pll_xtal25_wb20
  `endif
 
     pll0
     (
      .POWERDOWN(1'b1),
      .CLKA(sys_clk_pad_i),
      .LOCK(pll_lock),
 
  `ifdef VERSATILE_SDRAM
      .GLA(sdram_clk_o),
  `else
      .GLA(),
  `endif
 
      .GLB(wb_clk_o),
 
  `ifdef USB_CLK
      .GLC(usb_clk_o)
  `else
      .GLC()
  `endif
      );
 
   assign sync_rst_n = pll_lock;
 
  `ifdef ETH_CLK
   `ifdef ETH_CLK_PLL
 
   eth_pll eth_pll0
     (
      .POWERDOWN(1'b1),
      .CLKA(eth_clk_pad_i),
      .LOCK(eth_pll_lock),
      .GLA(eth_clk_o)
      );
   `else
   // Just instantiate global buffer for incoming ethernet clock
   gbuf eth_clk_gbuf
     (
      .CLK(eth_clk_pad_i),
      .GL(eth_clk_o)
      );
   assign eth_pll_lock = 1'b1;
   `endif // !`ifdef ETH_CLK_PLL
  `endif
 
   assign sync_eth_rst_n = eth_pll_lock;
 
 `else // !`ifdef SYNTHESIS
   // Buggy looking Actel PLL simulation model  (it was drifting when 
   // generating certain frequencies) so we will generate our own during 
   // simulation.
 
   reg    wb_clk_gen = 0;
   reg    usb_clk_gen = 0;
 
   // Delay on Actel PLLs for SDRAM clock (GLA) is 0.200ns
   parameter Tskew_actel_pll_gla = 0.200;
   assign #Tskew_actel_pll_gla sdram_clk_o  = sys_clk_pad_i;
 
   always
     #((`ACTEL_PLL_CLKB_PERIOD)/2) wb_clk_gen <=  async_rst ? 0 : ~wb_clk_gen;
 
   always
     #((`ACTEL_PLL_CLKC_PERIOD)/2) usb_clk_gen <=  async_rst ? 0 : ~usb_clk_gen;
 
   assign wb_clk_o = wb_clk_gen;
 
  `ifdef USB_CLK
   assign usb_clk_o = usb_clk_gen;
  `endif
 
  `ifdef ETH_CLK
   `ifdef ETH_CLK_PLL
   // Ethernet clock is 125MHz on ORSoC dev board 
   // PLL set to -0.06ns delay model this here
 
   wire   eth_clk, eth_clk_dly1, eth_clk_dly2;
   assign #3.5 eth_clk_dly1 = eth_clk_pad_i;
   assign #3.5 eth_clk_dly2 = eth_clk_dly1;
   assign #(1 - 0.06)eth_clk = eth_clk_dly2;
   assign eth_clk_o = eth_clk;
   `else
 
   assign eth_clk_o = eth_clk_pad_i;
 
   `endif // !`ifdef ETH_CLK_PLL
  `endif //  `ifdef ETH_CLK
 
 
 
   reg    pll_lock = 0;
   reg    eth_pll_lock = 1;
 
   always @(async_rst)
     if (async_rst)
       pll_lock = 0;
     else
       #300 pll_lock = 1;
 
   // Assign synchronous resets
   assign sync_rst_n = pll_lock;
   assign sync_eth_rst_n = eth_pll_lock;
 
 
 `endif // !`ifdef SYNTHESIS
`endif //  `ifdef ACTEL_PLL
 
   //
   // Reset generation
   //
   //
 
 
   // Reset generation for wishbone
   reg [15:0]       wb_rst_shr;
   always @(posedge wb_clk_o or posedge async_rst)
     if (async_rst)
       wb_rst_shr <= 16'hffff;
     else
       wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
 
   assign wb_rst_o = wb_rst_shr[15];
 
 
 
`ifdef VERSATILE_SDRAM
   // Reset generation for SDRAM controller
   reg [15:0]       sdram_rst_shr;
   always @(posedge sdram_clk_o or posedge async_rst)
     if (async_rst)
       sdram_rst_shr <= 16'hffff;
     else
       sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};
 
   assign sdram_rst_o = sdram_rst_shr[15];
`endif //  `ifdef VERSATILE_SDRAM
 
`ifdef ETH_CLK
   // Reset generation for ethernet SMII
   reg [15:0]       eth_rst_shr;
   always @(posedge eth_clk_o or posedge async_rst)
     if (async_rst)
       eth_rst_shr <= 16'hffff;
     else
       eth_rst_shr <= {eth_rst_shr[14:0], ~(sync_eth_rst_n)};
 
   assign eth_rst_o = eth_rst_shr[15];
`endif //  `ifdef ETH_CLK
 
endmodule // clkgen

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [clkgen/] [clkgen.v] - Blame information for rev 544

Line No.	Rev	Author	Line
1	408	julius	`/*`
2			`*`
3			`* Clock, reset generation unit`
4			`*`
5			`* Implements clock generation according to design defines`
6			`*`
7			`*/`
8			`//////////////////////////////////////////////////////////////////////`
9			`//// ////`
10			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
11			`//// ////`
12			`//// This source file may be used and distributed without ////`
13			`//// restriction provided that this copyright statement is not ////`
14			`//// removed from the file and that any derivative work contains ////`
15			`//// the original copyright notice and the associated disclaimer. ////`
16			`//// ////`
17			`//// This source file is free software; you can redistribute it ////`
18			`//// and/or modify it under the terms of the GNU Lesser General ////`
19			`//// Public License as published by the Free Software Foundation; ////`
20			`//// either version 2.1 of the License, or (at your option) any ////`
21			`//// later version. ////`
22			`//// ////`
23			`//// This source is distributed in the hope that it will be ////`
24			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
25			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
26			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
27			`//// details. ////`
28			`//// ////`
29			`//// You should have received a copy of the GNU Lesser General ////`
30			`//// Public License along with this source; if not, download it ////`
31			`//// from http://www.opencores.org/lgpl.shtml ////`
32			`//// ////`
33			`//////////////////////////////////////////////////////////////////////`
34
35			`include "timescale.v"
36			`include "orpsoc-defines.v"
37			`include "synthesis-defines.v"
38
39			`module clkgen`
40			`(`
41			`// Main clocks in, depending on board`
42			`sys_clk_pad_i,`
43
44			`// Wishbone clock and reset out`
45			`wb_clk_o,`
46			`wb_rst_o,`
47
48			`// JTAG clock`
49			`ifdef JTAG_DEBUG
50			`tck_pad_i,`
51			`dbg_tck_o,`
52			`endif
53			`// Main memory clocks`
54			`ifdef VERSATILE_SDRAM
55			`sdram_clk_o,`
56			`sdram_rst_o,`
57			`endif
58			`// Peripheral clocks`
59			`ifdef ETH_CLK
60			`eth_clk_pad_i,`
61			`eth_clk_o,`
62			`eth_rst_o,`
63			`endif
64
65			`ifdef USB_CLK
66			`usb_clk_o,`
67			`endif
68
69			`// Asynchronous, active low reset in`
70			`rst_n_pad_i`
71
72			`);`
73
74			`input sys_clk_pad_i;`
75
76			`output wb_rst_o;`
77			`output wb_clk_o;`
78
79			`ifdef JTAG_DEBUG
80			`input tck_pad_i;`
81			`output dbg_tck_o;`
82			`endif
83
84			`ifdef VERSATILE_SDRAM
85			`output sdram_clk_o;`
86			`output sdram_rst_o;`
87			`endif
88
89			`ifdef ETH_CLK
90			`input eth_clk_pad_i;`
91			`output eth_clk_o;`
92			`output eth_rst_o;`
93			`endif
94
95			`ifdef USB_CLK
96			`output usb_clk_o;`
97			`endif
98
99			`// Asynchronous, active low reset (pushbutton, typically)`
100			`input rst_n_pad_i;`
101
102			`// First, deal with the asychronous reset`
103			`wire async_rst;`
104			`wire async_rst_n;`
105
106	544	julius	`assign async_rst_n = rst_n_pad_i;`
107	408	julius
108			`// Everyone likes active-high reset signals...`
109			`assign async_rst = ~async_rst_n;`
110
111
112	544	julius	`ifdef JTAG_DEBUG
113			`assign dbg_tck_o = tck_pad_i;`
114	408	julius	`endif
115
116			`//`
117			`// Declare synchronous reset wires here`
118			`//`
119
120			`// An active-low synchronous reset signal (usually a PLL lock signal)`
121			`wire sync_rst_n;`
122
123			`// An active-low synchronous reset from ethernet PLL`
124			`wire sync_eth_rst_n;`
125
126
127			`ifdef ACTEL_PLL
128			`ifdef SYNTHESIS
129			`wire pll_lock;`
130			`wire eth_pll_lock;`
131
132			`ifdef PLL_XTAL64_WB36
133			`pll_xtal64_wb36`
134			`endif
135			`ifdef PLL_XTAL64_WB32
136			`pll_xtal64_wb32`
137			`endif
138			`ifdef PLL_XTAL64_WB30
139			`pll_xtal64_wb30`
140			`endif
141			`ifdef PLL_XTAL64_WB24
142			`pll_xtal64_wb24`
143			`endif
144			`ifdef PLL_XTAL64_WB20
145			`pll_xtal64_wb20`
146			`endif
147			`ifdef PLL_XTAL64_WB18
148			`pll_xtal64_wb18`
149			`endif
150			`ifdef PLL_XTAL64_WB16
151			`pll_xtal64_wb16`
152			`endif
153			`ifdef PLL_XTAL25_WB24
154			`pll_xtal25_wb24`
155			`endif
156			`ifdef PLL_XTAL25_WB20
157			`pll_xtal25_wb20`
158			`endif
159
160			`pll0`
161			`(`
162			`.POWERDOWN(1'b1),`
163			`.CLKA(sys_clk_pad_i),`
164			`.LOCK(pll_lock),`
165
166			`ifdef VERSATILE_SDRAM
167			`.GLA(sdram_clk_o),`
168			`else
169			`.GLA(),`
170			`endif
171
172			`.GLB(wb_clk_o),`
173
174			`ifdef USB_CLK
175			`.GLC(usb_clk_o)`
176			`else
177			`.GLC()`
178			`endif
179			`);`
180
181			`assign sync_rst_n = pll_lock;`
182
183			`ifdef ETH_CLK
184			`ifdef ETH_CLK_PLL
185
186			`eth_pll eth_pll0`
187			`(`
188			`.POWERDOWN(1'b1),`
189			`.CLKA(eth_clk_pad_i),`
190			`.LOCK(eth_pll_lock),`
191			`.GLA(eth_clk_o)`
192			`);`
193			`else
194			`// Just instantiate global buffer for incoming ethernet clock`
195			`gbuf eth_clk_gbuf`
196			`(`
197			`.CLK(eth_clk_pad_i),`
198			`.GL(eth_clk_o)`
199			`);`
200			`assign eth_pll_lock = 1'b1;`
201			`endif // !`ifdef ETH_CLK_PLL
202			`endif
203
204			`assign sync_eth_rst_n = eth_pll_lock;`
205
206			`else // !`ifdef SYNTHESIS
207			`// Buggy looking Actel PLL simulation model (it was drifting when`
208			`// generating certain frequencies) so we will generate our own during`
209			`// simulation.`
210
211			`reg wb_clk_gen = 0;`
212			`reg usb_clk_gen = 0;`
213
214			`// Delay on Actel PLLs for SDRAM clock (GLA) is 0.200ns`
215			`parameter Tskew_actel_pll_gla = 0.200;`
216			`assign #Tskew_actel_pll_gla sdram_clk_o = sys_clk_pad_i;`
217
218			`always`
219			#((`ACTEL_PLL_CLKB_PERIOD)/2) wb_clk_gen <= async_rst ? 0 : ~wb_clk_gen;
220
221			`always`
222			#((`ACTEL_PLL_CLKC_PERIOD)/2) usb_clk_gen <= async_rst ? 0 : ~usb_clk_gen;
223
224			`assign wb_clk_o = wb_clk_gen;`
225
226			`ifdef USB_CLK
227			`assign usb_clk_o = usb_clk_gen;`
228			`endif
229
230			`ifdef ETH_CLK
231			`ifdef ETH_CLK_PLL
232			`// Ethernet clock is 125MHz on ORSoC dev board`
233			`// PLL set to -0.06ns delay model this here`
234
235			`wire eth_clk, eth_clk_dly1, eth_clk_dly2;`
236			`assign #3.5 eth_clk_dly1 = eth_clk_pad_i;`
237			`assign #3.5 eth_clk_dly2 = eth_clk_dly1;`
238			`assign #(1 - 0.06)eth_clk = eth_clk_dly2;`
239			`assign eth_clk_o = eth_clk;`
240			`else
241
242			`assign eth_clk_o = eth_clk_pad_i;`
243
244			`endif // !`ifdef ETH_CLK_PLL
245			`endif // `ifdef ETH_CLK
246
247
248
249			`reg pll_lock = 0;`
250			`reg eth_pll_lock = 1;`
251
252			`always @(async_rst)`
253			`if (async_rst)`
254			`pll_lock = 0;`
255			`else`
256			`#300 pll_lock = 1;`
257
258			`// Assign synchronous resets`
259			`assign sync_rst_n = pll_lock;`
260			`assign sync_eth_rst_n = eth_pll_lock;`
261
262
263			`endif // !`ifdef SYNTHESIS
264			`endif // `ifdef ACTEL_PLL
265
266			`//`
267			`// Reset generation`
268			`//`
269			`//`
270
271
272			`// Reset generation for wishbone`
273			`reg [15:0] wb_rst_shr;`
274			`always @(posedge wb_clk_o or posedge async_rst)`
275			`if (async_rst)`
276			`wb_rst_shr <= 16'hffff;`
277			`else`
278			`wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};`
279
280			`assign wb_rst_o = wb_rst_shr[15];`
281
282
283
284			`ifdef VERSATILE_SDRAM
285			`// Reset generation for SDRAM controller`
286			`reg [15:0] sdram_rst_shr;`
287			`always @(posedge sdram_clk_o or posedge async_rst)`
288			`if (async_rst)`
289			`sdram_rst_shr <= 16'hffff;`
290			`else`
291			`sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};`
292
293			`assign sdram_rst_o = sdram_rst_shr[15];`
294			`endif // `ifdef VERSATILE_SDRAM
295
296			`ifdef ETH_CLK
297			`// Reset generation for ethernet SMII`
298			`reg [15:0] eth_rst_shr;`
299			`always @(posedge eth_clk_o or posedge async_rst)`
300			`if (async_rst)`
301			`eth_rst_shr <= 16'hffff;`
302			`else`
303			`eth_rst_shr <= {eth_rst_shr[14:0], ~(sync_eth_rst_n)};`
304
305			`assign eth_rst_o = eth_rst_shr[15];`
306			`endif // `ifdef ETH_CLK
307
308			`endmodule // clkgen`