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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [flashrom/] [flashrom.v] - Blame information for rev 502

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Line No. Rev Author Line
1 408 julius
// Wrapper for Actel flash ROM
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// 2 cycles from request to ACK
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module flashrom(
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                wb_clk,
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                wb_rst,
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                wb_adr_i,
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                wb_cyc_i,
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                wb_stb_i,
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                wb_ack_o,
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                wb_dat_o,
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                wb_err_o,
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                wb_rty_o);
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   input wb_clk;
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   input wb_rst;
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   input [6:0] wb_adr_i;
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   input       wb_cyc_i;
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   input       wb_stb_i;
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   output      wb_ack_o;
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   output reg [7:0] wb_dat_o;
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   output           wb_err_o;
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   output           wb_rty_o;
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   reg [3:0]         ack_shr;
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   reg [6:0]         addr;
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   wire [7:0]        dat;
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   reg [7:0]         dat_r;
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   wire             wb_access;
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   assign wb_access = wb_cyc_i & wb_stb_i;
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   always @(posedge wb_clk)
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     if (wb_rst)
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       ack_shr <= 0;
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     else if (wb_access & !(|ack_shr))
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       ack_shr[0] <= 1'b1;
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     else
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       ack_shr <= {ack_shr[2:0],1'b0};
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   assign wb_ack_o = ack_shr[3];
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   always @(posedge wb_clk)
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     if (wb_access & !(|ack_shr))
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       addr <= wb_adr_i;
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   orpsoc_flashROM orpsoc_flashROM0
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     (
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      .CLK(wb_clk),
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      .ADDR(addr),
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      .DOUT(dat)
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      );
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   always @(posedge wb_clk)
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     dat_r <= dat;
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   always @(posedge wb_clk)
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     wb_dat_o <= dat_r;
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   assign wb_err_o = 0;
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   assign wb_rty_o = 0;
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endmodule // flashrom

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