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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] [ethmac_defines.v] - Blame information for rev 425

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_defines.v                                               ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://opencores.org/project,ethmac                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  Modified by:                                                ////
////      - Julius Baxter (julius@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
 
//`define ETH_BIST                    // Bist for usage with Virtual Silicon RAMS
 
`define ETH_MBIST_CTRL_WIDTH 3        // width of MBIST control bus
 
// Generic FIFO implementation - hopefully synthesizable with Synplify
`define ETH_FIFO_GENERIC
// Ethernet implemented in Xilinx Chips (uncomment following lines)
// `define ETH_FIFO_XILINX             // Use Xilinx distributed ram for tx and rx fifo
// `define ETH_XILINX_RAMB4            // Selection of the used memory for Buffer descriptors
                                      // Core is going to be implemented in Virtex FPGA and contains Virtex 
                                      // specific elements. 
 
// Ethernet implemented in Altera Chips (uncomment following lines)
//`define ETH_ALTERA_ALTSYNCRAM
 
// Ethernet implemented in ASIC with Virtual Silicon RAMs
// `define ETH_VIRTUAL_SILICON_RAM     // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
 
// Ethernet implemented in ASIC with Artisan RAMs
// `define ETH_ARTISAN_RAM             // Artisan RAMS used storing buffer decriptors (ASIC implementation)
 
// Uncomment when Avalon bus is used
//`define ETH_AVALON_BUS
 
`define ETH_MODER_ADR         8'h0    // 0x0 
`define ETH_INT_SOURCE_ADR    8'h1    // 0x4 
`define ETH_INT_MASK_ADR      8'h2    // 0x8 
`define ETH_IPGT_ADR          8'h3    // 0xC 
`define ETH_IPGR1_ADR         8'h4    // 0x10
`define ETH_IPGR2_ADR         8'h5    // 0x14
`define ETH_PACKETLEN_ADR     8'h6    // 0x18
`define ETH_COLLCONF_ADR      8'h7    // 0x1C
`define ETH_TX_BD_NUM_ADR     8'h8    // 0x20
`define ETH_CTRLMODER_ADR     8'h9    // 0x24
`define ETH_MIIMODER_ADR      8'hA    // 0x28
`define ETH_MIICOMMAND_ADR    8'hB    // 0x2C
`define ETH_MIIADDRESS_ADR    8'hC    // 0x30
`define ETH_MIITX_DATA_ADR    8'hD    // 0x34
`define ETH_MIIRX_DATA_ADR    8'hE    // 0x38
`define ETH_MIISTATUS_ADR     8'hF    // 0x3C
`define ETH_MAC_ADDR0_ADR     8'h10   // 0x40
`define ETH_MAC_ADDR1_ADR     8'h11   // 0x44
`define ETH_HASH0_ADR         8'h12   // 0x48
`define ETH_HASH1_ADR         8'h13   // 0x4C
`define ETH_TX_CTRL_ADR       8'h14   // 0x50
`define ETH_RX_CTRL_ADR       8'h15   // 0x54
`define ETH_DBG_ADR           8'h16   // 0x58
 
 
`define ETH_MODER_DEF_0         8'h00
`define ETH_MODER_DEF_1         8'hA0
`define ETH_MODER_DEF_2         1'h0
`define ETH_INT_MASK_DEF_0      7'h0
`define ETH_IPGT_DEF_0          7'h12
`define ETH_IPGR1_DEF_0         7'h0C
`define ETH_IPGR2_DEF_0         7'h12
`define ETH_PACKETLEN_DEF_0     8'h00
`define ETH_PACKETLEN_DEF_1     8'h06
`define ETH_PACKETLEN_DEF_2     8'h40
`define ETH_PACKETLEN_DEF_3     8'h00
`define ETH_COLLCONF_DEF_0      6'h3f
`define ETH_COLLCONF_DEF_2      4'hF
`define ETH_TX_BD_NUM_DEF_0     8'h40
`define ETH_CTRLMODER_DEF_0     3'h0
`define ETH_MIIMODER_DEF_0      8'h64
`define ETH_MIIMODER_DEF_1      1'h0
`define ETH_MIIADDRESS_DEF_0    5'h00
`define ETH_MIIADDRESS_DEF_1    5'h00
`define ETH_MIITX_DATA_DEF_0    8'h00
`define ETH_MIITX_DATA_DEF_1    8'h00
`define ETH_MIIRX_DATA_DEF     16'h0000 // not written from WB
`define ETH_MAC_ADDR0_DEF_0     8'h00
`define ETH_MAC_ADDR0_DEF_1     8'h00
`define ETH_MAC_ADDR0_DEF_2     8'h00
`define ETH_MAC_ADDR0_DEF_3     8'h00
`define ETH_MAC_ADDR1_DEF_0     8'h00
`define ETH_MAC_ADDR1_DEF_1     8'h00
`define ETH_HASH0_DEF_0         8'h00
`define ETH_HASH0_DEF_1         8'h00
`define ETH_HASH0_DEF_2         8'h00
`define ETH_HASH0_DEF_3         8'h00
`define ETH_HASH1_DEF_0         8'h00
`define ETH_HASH1_DEF_1         8'h00
`define ETH_HASH1_DEF_2         8'h00
`define ETH_HASH1_DEF_3         8'h00
`define ETH_TX_CTRL_DEF_0       8'h00 //
`define ETH_TX_CTRL_DEF_1       8'h00 //
`define ETH_TX_CTRL_DEF_2       1'h0  //
`define ETH_RX_CTRL_DEF_0       8'h00
`define ETH_RX_CTRL_DEF_1       8'h00
 
 
`define ETH_MODER_WIDTH_0       8
`define ETH_MODER_WIDTH_1       8
`define ETH_MODER_WIDTH_2       1
`define ETH_INT_SOURCE_WIDTH_0  7
`define ETH_INT_MASK_WIDTH_0    7
`define ETH_IPGT_WIDTH_0        7
`define ETH_IPGR1_WIDTH_0       7
`define ETH_IPGR2_WIDTH_0       7
`define ETH_PACKETLEN_WIDTH_0   8
`define ETH_PACKETLEN_WIDTH_1   8
`define ETH_PACKETLEN_WIDTH_2   8
`define ETH_PACKETLEN_WIDTH_3   8
`define ETH_COLLCONF_WIDTH_0    6
`define ETH_COLLCONF_WIDTH_2    4
`define ETH_TX_BD_NUM_WIDTH_0   8
`define ETH_CTRLMODER_WIDTH_0   3
`define ETH_MIIMODER_WIDTH_0    8
`define ETH_MIIMODER_WIDTH_1    1
`define ETH_MIICOMMAND_WIDTH_0  3
`define ETH_MIIADDRESS_WIDTH_0  5
`define ETH_MIIADDRESS_WIDTH_1  5
`define ETH_MIITX_DATA_WIDTH_0  8
`define ETH_MIITX_DATA_WIDTH_1  8
`define ETH_MIIRX_DATA_WIDTH    16 // not written from WB
`define ETH_MIISTATUS_WIDTH     3 // not written from WB
`define ETH_MAC_ADDR0_WIDTH_0   8
`define ETH_MAC_ADDR0_WIDTH_1   8
`define ETH_MAC_ADDR0_WIDTH_2   8
`define ETH_MAC_ADDR0_WIDTH_3   8
`define ETH_MAC_ADDR1_WIDTH_0   8
`define ETH_MAC_ADDR1_WIDTH_1   8
`define ETH_HASH0_WIDTH_0       8
`define ETH_HASH0_WIDTH_1       8
`define ETH_HASH0_WIDTH_2       8
`define ETH_HASH0_WIDTH_3       8
`define ETH_HASH1_WIDTH_0       8
`define ETH_HASH1_WIDTH_1       8
`define ETH_HASH1_WIDTH_2       8
`define ETH_HASH1_WIDTH_3       8
`define ETH_TX_CTRL_WIDTH_0     8
`define ETH_TX_CTRL_WIDTH_1     8
`define ETH_TX_CTRL_WIDTH_2     1
`define ETH_RX_CTRL_WIDTH_0     8
`define ETH_RX_CTRL_WIDTH_1     8
 
 
// Outputs are registered (uncomment when needed)
`define ETH_REGISTERED_OUTPUTS
 
// Settings for TX FIFO
`define ETH_TX_FIFO_DATA_WIDTH 32
 
// Defines for ethernet TX fifo size - impacts FPGA resource usage
//`define ETH_TX_FULL_PACKET_FIFO  // Full 1500 byte TX buffer - uncomment this
//`define ETH_TX_256BYTE_FIFO  // 256 byte TX buffer - uncomment this
//`define ETH_TX_512BYTE_FIFO  // 512 byte TX buffer - uncomment this
`define ETH_TX_1KBYTE_FIFO     // 1024 byte TX buffer - uncomment this
 
`ifdef  ETH_TX_FULL_PACKET_FIFO
 `define ETH_TX_FIFO_CNT_WIDTH  11
 `define ETH_TX_FIFO_DEPTH      375
`else
 `ifdef ETH_TX_1KBYTE_FIFO
  `define ETH_TX_FIFO_CNT_WIDTH  9
  `define ETH_TX_FIFO_DEPTH      256
 `else
  `ifdef ETH_TX_512BYTE_FIFO
   `define ETH_TX_FIFO_CNT_WIDTH  8
   `define ETH_TX_FIFO_DEPTH      128
  `else
   `ifdef ETH_TX_256BYTE_FIFO
    `define ETH_TX_FIFO_CNT_WIDTH  7
    `define ETH_TX_FIFO_DEPTH      64
   `else
// Default is 64 bytes
    `define ETH_TX_FIFO_CNT_WIDTH  5
    `define ETH_TX_FIFO_DEPTH      16
   `endif
  `endif
 `endif // !`ifdef ETH_TX_512BYTE_FIFO
`endif // !`ifdef ETH_TX_FULL_PACKET_FIFO
 
 
 
// Settings for RX FIFO
`define ETH_RX_FIFO_CNT_WIDTH  9
`define ETH_RX_FIFO_DEPTH      256
//`define ETH_RX_FIFO_CNT_WIDTH  8
//`define ETH_RX_FIFO_DEPTH      128
//`define ETH_RX_FIFO_CNT_WIDTH  7
//`define ETH_RX_FIFO_DEPTH      64
//`define ETH_RX_FIFO_CNT_WIDTH  6
//`define ETH_RX_FIFO_DEPTH      32
//`define ETH_RX_FIFO_CNT_WIDTH  5
//`define ETH_RX_FIFO_DEPTH      16
 
`define ETH_RX_FIFO_DATA_WIDTH 32
 
// Burst length
`define BURST_4BEAT
`ifdef BURST_4BEAT
 `define ETH_BURST_LENGTH       4    // Change also ETH_BURST_CNT_WIDTH
 `define ETH_BURST_CNT_WIDTH    3    // The counter must be width enough to count to ETH_BURST_LENGTH
`endif
 
//`define ETH_BURST_LENGTH      32    // Change also ETH_BURST_CNT_WIDTH
//`define ETH_BURST_CNT_WIDTH    7    // The counter must be width enough to count to ETH_BURST_LENGTH
 
// Undefine this to enable bursting for RX (writing to memory)
`define ETH_RX_BURST_EN
 
 
// WISHBONE interface is Revision B3 compliant (uncomment when needed)
`define ETH_WISHBONE_B3
 
// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on
//`define TXBD_POLL
 
// Define this to allow reading of the Wishbone control state machine on reg
// address 0x58
`define WISHBONE_DEBUG

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] [ethmac_defines.v] - Blame information for rev 425

Line No.	Rev	Author	Line
1	408	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_defines.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://opencores.org/project,ethmac ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// Modified by: ////`
12			`//// - Julius Baxter (julius@opencores.org) ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40
41
42
43			//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
44
45			`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
46
47			`// Generic FIFO implementation - hopefully synthesizable with Synplify`
48			`define ETH_FIFO_GENERIC
49			`// Ethernet implemented in Xilinx Chips (uncomment following lines)`
50			// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
51			// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
52			`// Core is going to be implemented in Virtex FPGA and contains Virtex`
53			`// specific elements.`
54
55			`// Ethernet implemented in Altera Chips (uncomment following lines)`
56			//`define ETH_ALTERA_ALTSYNCRAM
57
58			`// Ethernet implemented in ASIC with Virtual Silicon RAMs`
59			// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
60
61			`// Ethernet implemented in ASIC with Artisan RAMs`
62			// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
63
64			`// Uncomment when Avalon bus is used`
65			//`define ETH_AVALON_BUS
66
67			`define ETH_MODER_ADR 8'h0 // 0x0
68			`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
69			`define ETH_INT_MASK_ADR 8'h2 // 0x8
70			`define ETH_IPGT_ADR 8'h3 // 0xC
71			`define ETH_IPGR1_ADR 8'h4 // 0x10
72			`define ETH_IPGR2_ADR 8'h5 // 0x14
73			`define ETH_PACKETLEN_ADR 8'h6 // 0x18
74			`define ETH_COLLCONF_ADR 8'h7 // 0x1C
75			`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
76			`define ETH_CTRLMODER_ADR 8'h9 // 0x24
77			`define ETH_MIIMODER_ADR 8'hA // 0x28
78			`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
79			`define ETH_MIIADDRESS_ADR 8'hC // 0x30
80			`define ETH_MIITX_DATA_ADR 8'hD // 0x34
81			`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
82			`define ETH_MIISTATUS_ADR 8'hF // 0x3C
83			`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
84			`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
85			`define ETH_HASH0_ADR 8'h12 // 0x48
86			`define ETH_HASH1_ADR 8'h13 // 0x4C
87			`define ETH_TX_CTRL_ADR 8'h14 // 0x50
88			`define ETH_RX_CTRL_ADR 8'h15 // 0x54
89			`define ETH_DBG_ADR 8'h16 // 0x58
90
91
92			`define ETH_MODER_DEF_0 8'h00
93			`define ETH_MODER_DEF_1 8'hA0
94			`define ETH_MODER_DEF_2 1'h0
95			`define ETH_INT_MASK_DEF_0 7'h0
96			`define ETH_IPGT_DEF_0 7'h12
97			`define ETH_IPGR1_DEF_0 7'h0C
98			`define ETH_IPGR2_DEF_0 7'h12
99			`define ETH_PACKETLEN_DEF_0 8'h00
100			`define ETH_PACKETLEN_DEF_1 8'h06
101			`define ETH_PACKETLEN_DEF_2 8'h40
102			`define ETH_PACKETLEN_DEF_3 8'h00
103			`define ETH_COLLCONF_DEF_0 6'h3f
104			`define ETH_COLLCONF_DEF_2 4'hF
105			`define ETH_TX_BD_NUM_DEF_0 8'h40
106			`define ETH_CTRLMODER_DEF_0 3'h0
107			`define ETH_MIIMODER_DEF_0 8'h64
108			`define ETH_MIIMODER_DEF_1 1'h0
109			`define ETH_MIIADDRESS_DEF_0 5'h00
110			`define ETH_MIIADDRESS_DEF_1 5'h00
111			`define ETH_MIITX_DATA_DEF_0 8'h00
112			`define ETH_MIITX_DATA_DEF_1 8'h00
113			`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB
114			`define ETH_MAC_ADDR0_DEF_0 8'h00
115			`define ETH_MAC_ADDR0_DEF_1 8'h00
116			`define ETH_MAC_ADDR0_DEF_2 8'h00
117			`define ETH_MAC_ADDR0_DEF_3 8'h00
118			`define ETH_MAC_ADDR1_DEF_0 8'h00
119			`define ETH_MAC_ADDR1_DEF_1 8'h00
120			`define ETH_HASH0_DEF_0 8'h00
121			`define ETH_HASH0_DEF_1 8'h00
122			`define ETH_HASH0_DEF_2 8'h00
123			`define ETH_HASH0_DEF_3 8'h00
124			`define ETH_HASH1_DEF_0 8'h00
125			`define ETH_HASH1_DEF_1 8'h00
126			`define ETH_HASH1_DEF_2 8'h00
127			`define ETH_HASH1_DEF_3 8'h00
128			`define ETH_TX_CTRL_DEF_0 8'h00 //
129			`define ETH_TX_CTRL_DEF_1 8'h00 //
130			`define ETH_TX_CTRL_DEF_2 1'h0 //
131			`define ETH_RX_CTRL_DEF_0 8'h00
132			`define ETH_RX_CTRL_DEF_1 8'h00
133
134
135			`define ETH_MODER_WIDTH_0 8
136			`define ETH_MODER_WIDTH_1 8
137			`define ETH_MODER_WIDTH_2 1
138			`define ETH_INT_SOURCE_WIDTH_0 7
139			`define ETH_INT_MASK_WIDTH_0 7
140			`define ETH_IPGT_WIDTH_0 7
141			`define ETH_IPGR1_WIDTH_0 7
142			`define ETH_IPGR2_WIDTH_0 7
143			`define ETH_PACKETLEN_WIDTH_0 8
144			`define ETH_PACKETLEN_WIDTH_1 8
145			`define ETH_PACKETLEN_WIDTH_2 8
146			`define ETH_PACKETLEN_WIDTH_3 8
147			`define ETH_COLLCONF_WIDTH_0 6
148			`define ETH_COLLCONF_WIDTH_2 4
149			`define ETH_TX_BD_NUM_WIDTH_0 8
150			`define ETH_CTRLMODER_WIDTH_0 3
151			`define ETH_MIIMODER_WIDTH_0 8
152			`define ETH_MIIMODER_WIDTH_1 1
153			`define ETH_MIICOMMAND_WIDTH_0 3
154			`define ETH_MIIADDRESS_WIDTH_0 5
155			`define ETH_MIIADDRESS_WIDTH_1 5
156			`define ETH_MIITX_DATA_WIDTH_0 8
157			`define ETH_MIITX_DATA_WIDTH_1 8
158			`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB
159			`define ETH_MIISTATUS_WIDTH 3 // not written from WB
160			`define ETH_MAC_ADDR0_WIDTH_0 8
161			`define ETH_MAC_ADDR0_WIDTH_1 8
162			`define ETH_MAC_ADDR0_WIDTH_2 8
163			`define ETH_MAC_ADDR0_WIDTH_3 8
164			`define ETH_MAC_ADDR1_WIDTH_0 8
165			`define ETH_MAC_ADDR1_WIDTH_1 8
166			`define ETH_HASH0_WIDTH_0 8
167			`define ETH_HASH0_WIDTH_1 8
168			`define ETH_HASH0_WIDTH_2 8
169			`define ETH_HASH0_WIDTH_3 8
170			`define ETH_HASH1_WIDTH_0 8
171			`define ETH_HASH1_WIDTH_1 8
172			`define ETH_HASH1_WIDTH_2 8
173			`define ETH_HASH1_WIDTH_3 8
174			`define ETH_TX_CTRL_WIDTH_0 8
175			`define ETH_TX_CTRL_WIDTH_1 8
176			`define ETH_TX_CTRL_WIDTH_2 1
177			`define ETH_RX_CTRL_WIDTH_0 8
178			`define ETH_RX_CTRL_WIDTH_1 8
179
180
181			`// Outputs are registered (uncomment when needed)`
182			`define ETH_REGISTERED_OUTPUTS
183
184			`// Settings for TX FIFO`
185			`define ETH_TX_FIFO_DATA_WIDTH 32
186
187			`// Defines for ethernet TX fifo size - impacts FPGA resource usage`
188			//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this
189			//`define ETH_TX_256BYTE_FIFO // 256 byte TX buffer - uncomment this
190			//`define ETH_TX_512BYTE_FIFO // 512 byte TX buffer - uncomment this
191			`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
192
193			`ifdef ETH_TX_FULL_PACKET_FIFO
194			`define ETH_TX_FIFO_CNT_WIDTH 11
195			`define ETH_TX_FIFO_DEPTH 375
196			`else
197			`ifdef ETH_TX_1KBYTE_FIFO
198			`define ETH_TX_FIFO_CNT_WIDTH 9
199			`define ETH_TX_FIFO_DEPTH 256
200			`else
201			`ifdef ETH_TX_512BYTE_FIFO
202			`define ETH_TX_FIFO_CNT_WIDTH 8
203			`define ETH_TX_FIFO_DEPTH 128
204			`else
205			`ifdef ETH_TX_256BYTE_FIFO
206			`define ETH_TX_FIFO_CNT_WIDTH 7
207			`define ETH_TX_FIFO_DEPTH 64
208			`else
209			`// Default is 64 bytes`
210			`define ETH_TX_FIFO_CNT_WIDTH 5
211			`define ETH_TX_FIFO_DEPTH 16
212			`endif
213			`endif
214			`endif // !`ifdef ETH_TX_512BYTE_FIFO
215			`endif // !`ifdef ETH_TX_FULL_PACKET_FIFO
216
217
218
219			`// Settings for RX FIFO`
220			`define ETH_RX_FIFO_CNT_WIDTH 9
221			`define ETH_RX_FIFO_DEPTH 256
222			//`define ETH_RX_FIFO_CNT_WIDTH 8
223			//`define ETH_RX_FIFO_DEPTH 128
224			//`define ETH_RX_FIFO_CNT_WIDTH 7
225			//`define ETH_RX_FIFO_DEPTH 64
226			//`define ETH_RX_FIFO_CNT_WIDTH 6
227			//`define ETH_RX_FIFO_DEPTH 32
228			//`define ETH_RX_FIFO_CNT_WIDTH 5
229			//`define ETH_RX_FIFO_DEPTH 16
230
231			`define ETH_RX_FIFO_DATA_WIDTH 32
232
233			`// Burst length`
234			`define BURST_4BEAT
235			`ifdef BURST_4BEAT
236			`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH
237			`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH
238			`endif
239
240			//`define ETH_BURST_LENGTH 32 // Change also ETH_BURST_CNT_WIDTH
241			//`define ETH_BURST_CNT_WIDTH 7 // The counter must be width enough to count to ETH_BURST_LENGTH
242
243			`// Undefine this to enable bursting for RX (writing to memory)`
244			`define ETH_RX_BURST_EN
245
246
247			`// WISHBONE interface is Revision B3 compliant (uncomment when needed)`
248			`define ETH_WISHBONE_B3
249
250			`// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on`
251			//`define TXBD_POLL
252
253			`// Define this to allow reading of the Wishbone control state machine on reg`
254			`// address 0x58`
255			`define WISHBONE_DEBUG