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1 408 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's definitions                                        ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://opencores.org/project,or1k                           ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Defines for the OR1200 core                                 ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add parameters that are missing                          ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// $Log: or1200_defines.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Defines added, bugs fixed. 
48
 
49
//
50
// Dump VCD
51
//
52
//`define OR1200_VCD_DUMP
53
 
54
//
55
// Generate debug messages during simulation
56
//
57
//`define OR1200_VERBOSE
58
 
59
//  `define OR1200_ASIC
60
////////////////////////////////////////////////////////
61
//
62
// Typical configuration for an ASIC
63
//
64
`ifdef OR1200_ASIC
65
 
66
//
67
// Target ASIC memories
68
//
69
//`define OR1200_ARTISAN_SSP
70
//`define OR1200_ARTISAN_SDP
71
//`define OR1200_ARTISAN_STP
72
`define OR1200_VIRTUALSILICON_SSP
73
//`define OR1200_VIRTUALSILICON_STP_T1
74
//`define OR1200_VIRTUALSILICON_STP_T2
75
 
76
//
77
// Do not implement Data cache
78
//
79
//`define OR1200_NO_DC
80
 
81
//
82
// Do not implement Insn cache
83
//
84
//`define OR1200_NO_IC
85
 
86
//
87
// Do not implement Data MMU
88
//
89
//`define OR1200_NO_DMMU
90
 
91
//
92
// Do not implement Insn MMU
93
//
94
//`define OR1200_NO_IMMU
95
 
96
//
97
// Select between ASIC optimized and generic multiplier
98
//
99
//`define OR1200_ASIC_MULTP2_32X32
100
`define OR1200_GENERIC_MULTP2_32X32
101
 
102
//
103
// Size/type of insn/data cache if implemented
104
//
105
// `define OR1200_IC_1W_512B
106
// `define OR1200_IC_1W_4KB
107
`define OR1200_IC_1W_8KB
108
// `define OR1200_DC_1W_4KB
109
`define OR1200_DC_1W_8KB
110
 
111
`else
112
 
113
 
114
/////////////////////////////////////////////////////////
115
//
116
// Typical configuration for an FPGA
117
//
118
 
119
//
120
// Target FPGA memories
121
//
122
//`define OR1200_ALTERA_LPM
123
//`define OR1200_XILINX_RAMB16
124
//`define OR1200_XILINX_RAMB4
125
//`define OR1200_XILINX_RAM32X1D
126
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
127
// Generic models should infer RAM blocks at synthesis time (not only effects 
128
// single port ram.)
129
`define OR1200_GENERIC
130
 
131
//
132
// Do not implement Data cache
133
//
134
//`define OR1200_NO_DC
135
 
136
//
137
// Do not implement Insn cache
138
//
139
//`define OR1200_NO_IC
140
 
141
//
142
// Do not implement Data MMU
143
//
144
//`define OR1200_NO_DMMU
145
 
146
//
147
// Do not implement Insn MMU
148
//
149
//`define OR1200_NO_IMMU
150
 
151
//
152
// Select between ASIC and generic multiplier
153
//
154
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
155
//
156
//`define OR1200_ASIC_MULTP2_32X32
157
`define OR1200_GENERIC_MULTP2_32X32
158
 
159
//
160
// Size/type of insn/data cache if implemented
161
// (consider available FPGA memory resources)
162
//
163
//`define OR1200_IC_1W_512B
164
//`define OR1200_IC_1W_4KB
165
`define OR1200_IC_1W_8KB
166
`define OR1200_DC_1W_4KB
167
//`define OR1200_DC_1W_8KB
168
 
169
`endif
170
 
171
 
172
//////////////////////////////////////////////////////////
173
//
174
// Do not change below unless you know what you are doing
175
//
176
 
177
//
178
// Reset active low
179
//
180
//`define OR1200_RST_ACT_LOW
181
 
182
//
183
// Enable RAM BIST
184
//
185
// At the moment this only works for Virtual Silicon
186
// single port RAMs. For other RAMs it has not effect.
187
// Special wrapper for VS RAMs needs to be provided
188
// with scan flops to facilitate bist scan.
189
//
190
//`define OR1200_BIST
191
 
192
//
193
// Register OR1200 WISHBONE outputs
194
// (must be defined/enabled)
195
//
196
`define OR1200_REGISTERED_OUTPUTS
197
 
198
//
199
// Register OR1200 WISHBONE inputs
200
//
201
// (must be undefined/disabled)
202
//
203
//`define OR1200_REGISTERED_INPUTS
204
 
205
//
206
// Disable bursts if they are not supported by the
207
// memory subsystem (only affect cache line fill)
208
//
209
//`define OR1200_NO_BURSTS
210
//
211
 
212
//
213
// WISHBONE retry counter range
214
//
215
// 2^value range for retry counter. Retry counter
216
// is activated whenever *wb_rty_i is asserted and
217
// until retry counter expires, corresponding
218
// WISHBONE interface is deactivated.
219
//
220
// To disable retry counters and *wb_rty_i all together,
221
// undefine this macro.
222
//
223
//`define OR1200_WB_RETRY 7
224
 
225
//
226
// WISHBONE Consecutive Address Burst
227
//
228
// This was used prior to WISHBONE B3 specification
229
// to identify bursts. It is no longer needed but
230
// remains enabled for compatibility with old designs.
231
//
232
// To remove *wb_cab_o ports undefine this macro.
233
//
234
//`define OR1200_WB_CAB
235
 
236
//
237
// WISHBONE B3 compatible interface
238
//
239
// This follows the WISHBONE B3 specification.
240
// It is not enabled by default because most
241
// designs still don't use WB b3.
242
//
243
// To enable *wb_cti_o/*wb_bte_o ports,
244
// define this macro.
245
//
246
`define OR1200_WB_B3
247
 
248
//
249
// LOG all WISHBONE accesses
250
//
251
`define OR1200_LOG_WB_ACCESS
252
 
253
//
254
// Enable additional synthesis directives if using
255
// _Synopsys_ synthesis tool
256
//
257
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
258
 
259
//
260
// Enables default statement in some case blocks
261
// and disables Synopsys synthesis directive full_case
262
//
263
// By default it is enabled. When disabled it
264
// can increase clock frequency.
265
//
266
`define OR1200_CASE_DEFAULT
267
 
268
//
269
// Operand width / register file address width
270
//
271
// (DO NOT CHANGE)
272
//
273
`define OR1200_OPERAND_WIDTH            32
274
`define OR1200_REGFILE_ADDR_WIDTH       5
275
 
276
//
277
// l.add/l.addi/l.and and optional l.addc/l.addic
278
// also set (compare) flag when result of their
279
// operation equals zero
280
//
281
// At the time of writing this, default or32
282
// C/C++ compiler doesn't generate code that
283
// would benefit from this optimization.
284
//
285
// By default this optimization is disabled to
286
// save area.
287
//
288
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
289
 
290
//
291
// Implement l.addc/l.addic instructions
292
//
293
// By default implementation of l.addc/l.addic
294
// instructions is enabled in case you need them.
295
// If you don't use them, then disable implementation
296
// to save area.
297
//
298
//`define OR1200_IMPL_ADDC
299
 
300
//
301
// Implement l.sub instruction
302
//
303
// By default implementation of l.sub instructions
304
// is enabled to be compliant with the simulator.
305
// If you don't use carry bit, then disable
306
// implementation to save area.
307
//
308
`define OR1200_IMPL_SUB
309
 
310
//
311
// Implement carry bit SR[CY]
312
//
313
//
314
// By default implementation of SR[CY] is enabled
315
// to be compliant with the simulator. However SR[CY]
316
// is explicitly only used by l.addc/l.addic/l.sub
317
// instructions and if these three insns are not
318
// implemented there is not much point having SR[CY].
319
//
320
//`define OR1200_IMPL_CY
321
 
322
//
323
// Implement rotate in the ALU
324
//
325
// At the time of writing this, or32
326
// C/C++ compiler doesn't generate rotate
327
// instructions. However or32 assembler
328
// can assemble code that uses rotate insn.
329
// This means that rotate instructions
330
// must be used manually inserted.
331
//
332
// By default implementation of rotate
333
// is disabled to save area and increase
334
// clock frequency.
335
//
336
//`define OR1200_IMPL_ALU_ROTATE
337
 
338
//
339
// Type of ALU compare to implement
340
//
341
// Try either one to find what yields
342
// higher clock frequencyin your case.
343
//
344
//`define OR1200_IMPL_ALU_COMP1
345
`define OR1200_IMPL_ALU_COMP2
346
 
347
//
348
// Implement Find First/Last '1'
349
//
350
`define OR1200_IMPL_ALU_FFL1
351
 
352
//
353
// Implement multiplier
354
//
355
// By default multiplier is implemented
356
//
357
`define OR1200_MULT_IMPLEMENTED
358
 
359
//
360
// Implement multiply-and-accumulate
361
//
362
// By default MAC is implemented. To
363 435 julius
// implement MAC, multiplier (non-serial) needs to be
364 408 julius
// implemented.
365
//
366 435 julius
//`define OR1200_MAC_IMPLEMENTED
367 408 julius
 
368
//
369
// Implement optional l.div/l.divu instructions
370
//
371
// By default divide instructions are not implemented
372 435 julius
// to save area.
373 408 julius
//
374
//
375
`define OR1200_DIV_IMPLEMENTED
376
 
377
//
378 435 julius
// Serial multiplier.
379 408 julius
//
380 435 julius
`define OR1200_MULT_SERIAL
381
 
382 408 julius
//
383 435 julius
// Serial divider.
384
// Uncomment to use a serial divider, otherwise will
385
// be a generic parallel implementation.
386
//
387
`define OR1200_DIV_SERIAL
388 408 julius
 
389
//
390
// Implement HW Single Precision FPU
391
//
392
//`define OR1200_FPU_IMPLEMENTED
393
//
394
 
395
//
396
// Clock ratio RISC clock versus WB clock
397
//
398
// If you plan to run WB:RISC clock fixed to 1:1, disable
399
// both defines
400
//
401
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
402
// and use clmode to set ratio
403
//
404
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
405
// clmode to set ratio
406
//
407
//`define OR1200_CLKDIV_2_SUPPORTED
408
//`define OR1200_CLKDIV_4_SUPPORTED
409
 
410
//
411
// Type of register file RAM
412
//
413
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
414
//`define OR1200_RFRAM_TWOPORT
415
//
416
// Memory macro dual port (see or1200_dpram.v)
417
`define OR1200_RFRAM_DUALPORT
418
 
419
//
420
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
421
//`define OR1200_RFRAM_GENERIC
422
//  Generic register file supports - 16 registers 
423
`ifdef OR1200_RFRAM_GENERIC
424
//    `define OR1200_RFRAM_16REG
425
`endif
426
 
427
//
428
// Type of mem2reg aligner to implement.
429
//
430
// Once OR1200_IMPL_MEM2REG2 yielded faster
431
// circuit, however with today tools it will
432
// most probably give you slower circuit.
433
//
434
`define OR1200_IMPL_MEM2REG1
435
//`define OR1200_IMPL_MEM2REG2
436
 
437
//
438
// Reset value and event
439
//
440
`ifdef OR1200_RST_ACT_LOW
441
  `define OR1200_RST_VALUE      (1'b0)
442
  `define OR1200_RST_EVENT      negedge
443
`else
444
  `define OR1200_RST_VALUE      (1'b1)
445
  `define OR1200_RST_EVENT      posedge
446
`endif
447
 
448
//
449
// ALUOPs
450
//
451
`define OR1200_ALUOP_WIDTH      4
452
`define OR1200_ALUOP_NOP        4'd4
453
/* Order defined by arith insns that have two source operands both in regs
454
   (see binutils/include/opcode/or32.h) */
455
`define OR1200_ALUOP_ADD        4'd0
456
`define OR1200_ALUOP_ADDC       4'd1
457
`define OR1200_ALUOP_SUB        4'd2
458
`define OR1200_ALUOP_AND        4'd3
459
`define OR1200_ALUOP_OR         4'd4
460
`define OR1200_ALUOP_XOR        4'd5
461
`define OR1200_ALUOP_MUL        4'd6
462
`define OR1200_ALUOP_CUST5      4'd7
463
`define OR1200_ALUOP_SHROT      4'd8
464
`define OR1200_ALUOP_DIV        4'd9
465
`define OR1200_ALUOP_DIVU       4'd10
466 435 julius
`define OR1200_ALUOP_MULU       4'd11
467
/* Values sent to ALU from decode unit - not strictly defined by ISA */
468 408 julius
`define OR1200_ALUOP_MOVHI      4'd12
469
`define OR1200_ALUOP_COMP       4'd13
470
`define OR1200_ALUOP_MTSR       4'd14
471
`define OR1200_ALUOP_MFSR       4'd15
472
`define OR1200_ALUOP_CMOV       4'd14
473
`define OR1200_ALUOP_FFL1       4'd15
474
 
475
 
476
// ALU instructions second opcode field (previously multicycle field in 
477
// machine word)
478
`define OR1200_ALUOP2_POS               9:8
479
`define OR1200_ALUOP2_WIDTH     2
480
 
481
 
482
//
483
// MACOPs
484
//
485
`define OR1200_MACOP_WIDTH      3
486
`define OR1200_MACOP_NOP        3'b000
487
`define OR1200_MACOP_MAC        3'b001
488
`define OR1200_MACOP_MSB        3'b010
489
 
490
//
491
// Shift/rotate ops
492
//
493
`define OR1200_SHROTOP_WIDTH    2
494
`define OR1200_SHROTOP_NOP      2'd0
495
`define OR1200_SHROTOP_SLL      2'd0
496
`define OR1200_SHROTOP_SRL      2'd1
497
`define OR1200_SHROTOP_SRA      2'd2
498
`define OR1200_SHROTOP_ROR      2'd3
499
 
500
// Execution cycles per instruction
501
`define OR1200_MULTICYCLE_WIDTH 3
502
`define OR1200_ONE_CYCLE                3'd0
503
`define OR1200_TWO_CYCLES               3'd1
504
 
505
// Execution control which will "wait on" a module to finish
506
`define OR1200_WAIT_ON_WIDTH 2
507
`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd1
508
`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd2
509
 
510
// Operand MUX selects
511
`define OR1200_SEL_WIDTH                2
512
`define OR1200_SEL_RF                   2'd0
513
`define OR1200_SEL_IMM                  2'd1
514
`define OR1200_SEL_EX_FORW              2'd2
515
`define OR1200_SEL_WB_FORW              2'd3
516
 
517
//
518
// BRANCHOPs
519
//
520
`define OR1200_BRANCHOP_WIDTH           3
521
`define OR1200_BRANCHOP_NOP             3'd0
522
`define OR1200_BRANCHOP_J               3'd1
523
`define OR1200_BRANCHOP_JR              3'd2
524
`define OR1200_BRANCHOP_BAL             3'd3
525
`define OR1200_BRANCHOP_BF              3'd4
526
`define OR1200_BRANCHOP_BNF             3'd5
527
`define OR1200_BRANCHOP_RFE             3'd6
528
 
529
//
530
// LSUOPs
531
//
532
// Bit 0: sign extend
533
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
534
// Bit 3: 0 load, 1 store
535
`define OR1200_LSUOP_WIDTH              4
536
`define OR1200_LSUOP_NOP                4'b0000
537
`define OR1200_LSUOP_LBZ                4'b0010
538
`define OR1200_LSUOP_LBS                4'b0011
539
`define OR1200_LSUOP_LHZ                4'b0100
540
`define OR1200_LSUOP_LHS                4'b0101
541
`define OR1200_LSUOP_LWZ                4'b0110
542
`define OR1200_LSUOP_LWS                4'b0111
543
`define OR1200_LSUOP_LD                 4'b0001
544
`define OR1200_LSUOP_SD                 4'b1000
545
`define OR1200_LSUOP_SB                 4'b1010
546
`define OR1200_LSUOP_SH                 4'b1100
547
`define OR1200_LSUOP_SW                 4'b1110
548
 
549
// Number of bits of load/store EA precalculated in ID stage
550
// for balancing ID and EX stages.
551
//
552
// Valid range: 2,3,...,30,31
553
`define OR1200_LSUEA_PRECALC            2
554
 
555
// FETCHOPs
556
`define OR1200_FETCHOP_WIDTH            1
557
`define OR1200_FETCHOP_NOP              1'b0
558
`define OR1200_FETCHOP_LW               1'b1
559
 
560
//
561
// Register File Write-Back OPs
562
//
563
// Bit 0: register file write enable
564
// Bits 3-1: write-back mux selects
565
//
566
`define OR1200_RFWBOP_WIDTH             4
567
`define OR1200_RFWBOP_NOP               4'b0000
568
`define OR1200_RFWBOP_ALU               3'b000
569
`define OR1200_RFWBOP_LSU               3'b001
570
`define OR1200_RFWBOP_SPRS              3'b010
571
`define OR1200_RFWBOP_LR                3'b011
572
`define OR1200_RFWBOP_FPU               3'b100
573
 
574
// Compare instructions
575
`define OR1200_COP_SFEQ       3'b000
576
`define OR1200_COP_SFNE       3'b001
577
`define OR1200_COP_SFGT       3'b010
578
`define OR1200_COP_SFGE       3'b011
579
`define OR1200_COP_SFLT       3'b100
580
`define OR1200_COP_SFLE       3'b101
581
`define OR1200_COP_X          3'b111
582
`define OR1200_SIGNED_COMPARE 'd3
583
`define OR1200_COMPOP_WIDTH     4
584
 
585
//
586
// FP OPs
587
//
588
// MSbit indicates FPU operation valid
589
//
590
`define OR1200_FPUOP_WIDTH      8
591
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
592
`define OR1200_FPUOP_CYCLES 3'd4
593
// FP instruction is double precision if bit 4 is set. We're a 32-bit 
594
// implementation thus do not support double precision FP 
595
`define OR1200_FPUOP_DOUBLE_BIT 4
596
`define OR1200_FPUOP_ADD  8'b0000_0000
597
`define OR1200_FPUOP_SUB  8'b0000_0001
598
`define OR1200_FPUOP_MUL  8'b0000_0010
599
`define OR1200_FPUOP_DIV  8'b0000_0011
600
`define OR1200_FPUOP_ITOF 8'b0000_0100
601
`define OR1200_FPUOP_FTOI 8'b0000_0101
602
`define OR1200_FPUOP_REM  8'b0000_0110
603
`define OR1200_FPUOP_RESERVED  8'b0000_0111
604
// FP Compare instructions
605
`define OR1200_FPCOP_SFEQ 8'b0000_1000
606
`define OR1200_FPCOP_SFNE 8'b0000_1001
607
`define OR1200_FPCOP_SFGT 8'b0000_1010
608
`define OR1200_FPCOP_SFGE 8'b0000_1011
609
`define OR1200_FPCOP_SFLT 8'b0000_1100
610
`define OR1200_FPCOP_SFLE 8'b0000_1101
611
 
612
//
613
// TAGs for instruction bus
614
//
615
`define OR1200_ITAG_IDLE        4'h0    // idle bus
616
`define OR1200_ITAG_NI          4'h1    // normal insn
617
`define OR1200_ITAG_BE          4'hb    // Bus error exception
618
`define OR1200_ITAG_PE          4'hc    // Page fault exception
619
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
620
 
621
//
622
// TAGs for data bus
623
//
624
`define OR1200_DTAG_IDLE        4'h0    // idle bus
625
`define OR1200_DTAG_ND          4'h1    // normal data
626
`define OR1200_DTAG_AE          4'ha    // Alignment exception
627
`define OR1200_DTAG_BE          4'hb    // Bus error exception
628
`define OR1200_DTAG_PE          4'hc    // Page fault exception
629
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
630
 
631
 
632
//////////////////////////////////////////////
633
//
634
// ORBIS32 ISA specifics
635
//
636
 
637
// SHROT_OP position in machine word
638
`define OR1200_SHROTOP_POS              7:6
639
 
640
//
641
// Instruction opcode groups (basic)
642
//
643
`define OR1200_OR32_J                 6'b000000
644
`define OR1200_OR32_JAL               6'b000001
645
`define OR1200_OR32_BNF               6'b000011
646
`define OR1200_OR32_BF                6'b000100
647
`define OR1200_OR32_NOP               6'b000101
648
`define OR1200_OR32_MOVHI             6'b000110
649
`define OR1200_OR32_XSYNC             6'b001000
650
`define OR1200_OR32_RFE               6'b001001
651
/* */
652
`define OR1200_OR32_JR                6'b010001
653
`define OR1200_OR32_JALR              6'b010010
654
`define OR1200_OR32_MACI              6'b010011
655
/* */
656
`define OR1200_OR32_LWZ               6'b100001
657
`define OR1200_OR32_LBZ               6'b100011
658
`define OR1200_OR32_LBS               6'b100100
659
`define OR1200_OR32_LHZ               6'b100101
660
`define OR1200_OR32_LHS               6'b100110
661
`define OR1200_OR32_ADDI              6'b100111
662
`define OR1200_OR32_ADDIC             6'b101000
663
`define OR1200_OR32_ANDI              6'b101001
664
`define OR1200_OR32_ORI               6'b101010
665
`define OR1200_OR32_XORI              6'b101011
666
`define OR1200_OR32_MULI              6'b101100
667
`define OR1200_OR32_MFSPR             6'b101101
668
`define OR1200_OR32_SH_ROTI           6'b101110
669
`define OR1200_OR32_SFXXI             6'b101111
670
/* */
671
`define OR1200_OR32_MTSPR             6'b110000
672
`define OR1200_OR32_MACMSB            6'b110001
673
`define OR1200_OR32_FLOAT             6'b110010
674
/* */
675
`define OR1200_OR32_SW                6'b110101
676
`define OR1200_OR32_SB                6'b110110
677
`define OR1200_OR32_SH                6'b110111
678
`define OR1200_OR32_ALU               6'b111000
679
`define OR1200_OR32_SFXX              6'b111001
680
//`define OR1200_OR32_CUST5             6'b111100
681
 
682
 
683
/////////////////////////////////////////////////////
684
//
685
// Exceptions
686
//
687
 
688
//
689
// Exception vectors per OR1K architecture:
690
// 0xPPPPP100 - reset
691
// 0xPPPPP200 - bus error
692
// ... etc
693
// where P represents exception prefix.
694
//
695
// Exception vectors can be customized as per
696
// the following formula:
697
// 0xPPPPPNVV - exception N
698
//
699
// P represents exception prefix
700
// N represents exception N
701
// VV represents length of the individual vector space,
702
//   usually it is 8 bits wide and starts with all bits zero
703
//
704
 
705
//
706
// PPPPP and VV parts
707
//
708
// Sum of these two defines needs to be 28
709
//
710
`define OR1200_EXCEPT_EPH0_P    20'h00000
711
`define OR1200_EXCEPT_EPH1_P    20'hF0000
712
`define OR1200_EXCEPT_V             8'h00
713
 
714
//
715
// N part width
716
//
717
`define OR1200_EXCEPT_WIDTH 4
718
 
719
//
720
// Definition of exception vectors
721
//
722
// To avoid implementation of a certain exception,
723
// simply comment out corresponding line
724
//
725
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
726
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
727
`define OR1200_EXCEPT_FLOAT             `OR1200_EXCEPT_WIDTH'hd
728
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
729
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
730
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
731
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
732
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
733
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
734
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
735
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
736
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
737
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
738
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
739
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
740
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
741
 
742
 
743
/////////////////////////////////////////////////////
744
//
745
// SPR groups
746
//
747
 
748
// Bits that define the group
749
`define OR1200_SPR_GROUP_BITS   15:11
750
 
751
// Width of the group bits
752
`define OR1200_SPR_GROUP_WIDTH  5
753
 
754
// Bits that define offset inside the group
755
`define OR1200_SPR_OFS_BITS 10:0
756
 
757
// List of groups
758
`define OR1200_SPR_GROUP_SYS    5'd00
759
`define OR1200_SPR_GROUP_DMMU   5'd01
760
`define OR1200_SPR_GROUP_IMMU   5'd02
761
`define OR1200_SPR_GROUP_DC     5'd03
762
`define OR1200_SPR_GROUP_IC     5'd04
763
`define OR1200_SPR_GROUP_MAC    5'd05
764
`define OR1200_SPR_GROUP_DU     5'd06
765
`define OR1200_SPR_GROUP_PM     5'd08
766
`define OR1200_SPR_GROUP_PIC    5'd09
767
`define OR1200_SPR_GROUP_TT     5'd10
768
`define OR1200_SPR_GROUP_FPU    5'd11
769
 
770
/////////////////////////////////////////////////////
771
//
772
// System group
773
//
774
 
775
//
776
// System registers
777
//
778
`define OR1200_SPR_CFGR         7'd0
779
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
780
`define OR1200_SPR_NPC          11'd16
781
`define OR1200_SPR_SR           11'd17
782
`define OR1200_SPR_PPC          11'd18
783
`define OR1200_SPR_FPCSR        11'd20
784
`define OR1200_SPR_EPCR         11'd32
785
`define OR1200_SPR_EEAR         11'd48
786
`define OR1200_SPR_ESR          11'd64
787
 
788
//
789
// SR bits
790
//
791
`define OR1200_SR_WIDTH 17
792
`define OR1200_SR_SM   0
793
`define OR1200_SR_TEE  1
794
`define OR1200_SR_IEE  2
795
`define OR1200_SR_DCE  3
796
`define OR1200_SR_ICE  4
797
`define OR1200_SR_DME  5
798
`define OR1200_SR_IME  6
799
`define OR1200_SR_LEE  7
800
`define OR1200_SR_CE   8
801
`define OR1200_SR_F    9
802
`define OR1200_SR_CY   10       // Unused
803
`define OR1200_SR_OV   11       // Unused
804
`define OR1200_SR_OVE  12       // Unused
805
`define OR1200_SR_DSX  13       // Unused
806
`define OR1200_SR_EPH  14
807
`define OR1200_SR_FO   15
808
`define OR1200_SR_TED  16
809
`define OR1200_SR_CID  31:28    // Unimplemented
810
 
811
//
812
// Bits that define offset inside the group
813
//
814
`define OR1200_SPROFS_BITS 10:0
815
 
816
//
817
// Default Exception Prefix
818
//
819
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
820
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
821
//
822
`define OR1200_SR_EPH_DEF       1'b0
823
 
824
 
825
//
826
// FPCSR bits
827
//
828
`define OR1200_FPCSR_WIDTH 12
829
`define OR1200_FPCSR_FPEE  0
830
`define OR1200_FPCSR_RM    2:1
831
`define OR1200_FPCSR_OVF   3
832
`define OR1200_FPCSR_UNF   4
833
`define OR1200_FPCSR_SNF   5
834
`define OR1200_FPCSR_QNF   6
835
`define OR1200_FPCSR_ZF    7
836
`define OR1200_FPCSR_IXF   8
837
`define OR1200_FPCSR_IVF   9
838
`define OR1200_FPCSR_INF   10
839
`define OR1200_FPCSR_DZF   11
840
`define OR1200_FPCSR_RES   31:12
841
 
842
/////////////////////////////////////////////////////
843
//
844
// Power Management (PM)
845
//
846
 
847
// Define it if you want PM implemented
848
//`define OR1200_PM_IMPLEMENTED
849
 
850
// Bit positions inside PMR (don't change)
851
`define OR1200_PM_PMR_SDF 3:0
852
`define OR1200_PM_PMR_DME 4
853
`define OR1200_PM_PMR_SME 5
854
`define OR1200_PM_PMR_DCGE 6
855
`define OR1200_PM_PMR_UNUSED 31:7
856
 
857
// PMR offset inside PM group of registers
858
`define OR1200_PM_OFS_PMR 11'b0
859
 
860
// PM group
861
`define OR1200_SPRGRP_PM 5'd8
862
 
863
// Define if PMR can be read/written at any address inside PM group
864
`define OR1200_PM_PARTIAL_DECODING
865
 
866
// Define if reading PMR is allowed
867
`define OR1200_PM_READREGS
868
 
869
// Define if unused PMR bits should be zero
870
`define OR1200_PM_UNUSED_ZERO
871
 
872
 
873
/////////////////////////////////////////////////////
874
//
875
// Debug Unit (DU)
876
//
877
 
878
// Define it if you want DU implemented
879
`define OR1200_DU_IMPLEMENTED
880
 
881
//
882
// Define if you want HW Breakpoints
883
// (if HW breakpoints are not implemented
884
// only default software trapping is
885
// possible with l.trap insn - this is
886
// however already enough for use
887
// with or32 gdb)
888
//
889
//`define OR1200_DU_HWBKPTS
890
 
891
// Number of DVR/DCR pairs if HW breakpoints enabled
892
//      Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
893
//      DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
894
`define OR1200_DU_DVRDCR_PAIRS 8
895
 
896
// Define if you want trace buffer
897
//      (for now only available for Xilinx Virtex FPGAs)
898
//`define OR1200_DU_TB_IMPLEMENTED
899
 
900
 
901
//
902
// Address offsets of DU registers inside DU group
903
//
904
// To not implement a register, doq not define its address
905
//
906
`ifdef OR1200_DU_HWBKPTS
907
`define OR1200_DU_DVR0          11'd0
908
`define OR1200_DU_DVR1          11'd1
909
`define OR1200_DU_DVR2          11'd2
910
`define OR1200_DU_DVR3          11'd3
911
`define OR1200_DU_DVR4          11'd4
912
`define OR1200_DU_DVR5          11'd5
913
`define OR1200_DU_DVR6          11'd6
914
`define OR1200_DU_DVR7          11'd7
915
`define OR1200_DU_DCR0          11'd8
916
`define OR1200_DU_DCR1          11'd9
917
`define OR1200_DU_DCR2          11'd10
918
`define OR1200_DU_DCR3          11'd11
919
`define OR1200_DU_DCR4          11'd12
920
`define OR1200_DU_DCR5          11'd13
921
`define OR1200_DU_DCR6          11'd14
922
`define OR1200_DU_DCR7          11'd15
923
`endif
924
`define OR1200_DU_DMR1          11'd16
925
`ifdef OR1200_DU_HWBKPTS
926
`define OR1200_DU_DMR2          11'd17
927
`define OR1200_DU_DWCR0         11'd18
928
`define OR1200_DU_DWCR1         11'd19
929
`endif
930
`define OR1200_DU_DSR           11'd20
931
`define OR1200_DU_DRR           11'd21
932
`ifdef OR1200_DU_TB_IMPLEMENTED
933
`define OR1200_DU_TBADR         11'h0ff
934
`define OR1200_DU_TBIA          11'h1??
935
`define OR1200_DU_TBIM          11'h2??
936
`define OR1200_DU_TBAR          11'h3??
937
`define OR1200_DU_TBTS          11'h4??
938
`endif
939
 
940
// Position of offset bits inside SPR address
941
`define OR1200_DUOFS_BITS       10:0
942
 
943
// DCR bits
944
`define OR1200_DU_DCR_DP        0
945
`define OR1200_DU_DCR_CC        3:1
946
`define OR1200_DU_DCR_SC        4
947
`define OR1200_DU_DCR_CT        7:5
948
 
949
// DMR1 bits
950
`define OR1200_DU_DMR1_CW0      1:0
951
`define OR1200_DU_DMR1_CW1      3:2
952
`define OR1200_DU_DMR1_CW2      5:4
953
`define OR1200_DU_DMR1_CW3      7:6
954
`define OR1200_DU_DMR1_CW4      9:8
955
`define OR1200_DU_DMR1_CW5      11:10
956
`define OR1200_DU_DMR1_CW6      13:12
957
`define OR1200_DU_DMR1_CW7      15:14
958
`define OR1200_DU_DMR1_CW8      17:16
959
`define OR1200_DU_DMR1_CW9      19:18
960
`define OR1200_DU_DMR1_CW10     21:20
961
`define OR1200_DU_DMR1_ST       22
962
`define OR1200_DU_DMR1_BT       23
963
`define OR1200_DU_DMR1_DXFW     24
964
`define OR1200_DU_DMR1_ETE      25
965
 
966
// DMR2 bits
967
`define OR1200_DU_DMR2_WCE0     0
968
`define OR1200_DU_DMR2_WCE1     1
969
`define OR1200_DU_DMR2_AWTC     12:2
970
`define OR1200_DU_DMR2_WGB      23:13
971
 
972
// DWCR bits
973
`define OR1200_DU_DWCR_COUNT    15:0
974
`define OR1200_DU_DWCR_MATCH    31:16
975
 
976
// DSR bits
977
`define OR1200_DU_DSR_WIDTH     14
978
`define OR1200_DU_DSR_RSTE      0
979
`define OR1200_DU_DSR_BUSEE     1
980
`define OR1200_DU_DSR_DPFE      2
981
`define OR1200_DU_DSR_IPFE      3
982
`define OR1200_DU_DSR_TTE       4
983
`define OR1200_DU_DSR_AE        5
984
`define OR1200_DU_DSR_IIE       6
985
`define OR1200_DU_DSR_IE        7
986
`define OR1200_DU_DSR_DME       8
987
`define OR1200_DU_DSR_IME       9
988
`define OR1200_DU_DSR_RE        10
989
`define OR1200_DU_DSR_SCE       11
990
`define OR1200_DU_DSR_FPE       12
991
`define OR1200_DU_DSR_TE        13
992
 
993
// DRR bits
994
`define OR1200_DU_DRR_RSTE      0
995
`define OR1200_DU_DRR_BUSEE     1
996
`define OR1200_DU_DRR_DPFE      2
997
`define OR1200_DU_DRR_IPFE      3
998
`define OR1200_DU_DRR_TTE       4
999
`define OR1200_DU_DRR_AE        5
1000
`define OR1200_DU_DRR_IIE       6
1001
`define OR1200_DU_DRR_IE        7
1002
`define OR1200_DU_DRR_DME       8
1003
`define OR1200_DU_DRR_IME       9
1004
`define OR1200_DU_DRR_RE        10
1005
`define OR1200_DU_DRR_SCE       11
1006
`define OR1200_DU_DRR_FPE       12
1007
`define OR1200_DU_DRR_TE        13
1008
 
1009
// Define if reading DU regs is allowed
1010
`define OR1200_DU_READREGS
1011
 
1012
// Define if unused DU registers bits should be zero
1013
`define OR1200_DU_UNUSED_ZERO
1014
 
1015
// Define if IF/LSU status is not needed by devel i/f
1016
`define OR1200_DU_STATUS_UNIMPLEMENTED
1017
 
1018
/////////////////////////////////////////////////////
1019
//
1020
// Programmable Interrupt Controller (PIC)
1021
//
1022
 
1023
// Define it if you want PIC implemented
1024
`define OR1200_PIC_IMPLEMENTED
1025
 
1026
// Define number of interrupt inputs (2-31)
1027
`define OR1200_PIC_INTS 31
1028
 
1029
// Address offsets of PIC registers inside PIC group
1030
`define OR1200_PIC_OFS_PICMR 2'd0
1031
`define OR1200_PIC_OFS_PICSR 2'd2
1032
 
1033
// Position of offset bits inside SPR address
1034
`define OR1200_PICOFS_BITS 1:0
1035
 
1036
// Define if you want these PIC registers to be implemented
1037
`define OR1200_PIC_PICMR
1038
`define OR1200_PIC_PICSR
1039
 
1040
// Define if reading PIC registers is allowed
1041
`define OR1200_PIC_READREGS
1042
 
1043
// Define if unused PIC register bits should be zero
1044
`define OR1200_PIC_UNUSED_ZERO
1045
 
1046
 
1047
/////////////////////////////////////////////////////
1048
//
1049
// Tick Timer (TT)
1050
//
1051
 
1052
// Define it if you want TT implemented
1053
`define OR1200_TT_IMPLEMENTED
1054
 
1055
// Address offsets of TT registers inside TT group
1056
`define OR1200_TT_OFS_TTMR 1'd0
1057
`define OR1200_TT_OFS_TTCR 1'd1
1058
 
1059
// Position of offset bits inside SPR group
1060
`define OR1200_TTOFS_BITS 0
1061
 
1062
// Define if you want these TT registers to be implemented
1063
`define OR1200_TT_TTMR
1064
`define OR1200_TT_TTCR
1065
 
1066
// TTMR bits
1067
`define OR1200_TT_TTMR_TP 27:0
1068
`define OR1200_TT_TTMR_IP 28
1069
`define OR1200_TT_TTMR_IE 29
1070
`define OR1200_TT_TTMR_M 31:30
1071
 
1072
// Define if reading TT registers is allowed
1073
`define OR1200_TT_READREGS
1074
 
1075
 
1076
//////////////////////////////////////////////
1077
//
1078
// MAC
1079
//
1080
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1081
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1082
 
1083
//
1084
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1085
//
1086
// According to architecture manual there is no shift, so default value is 0.
1087
// However the implementation has deviated in this from the arch manual and had
1088
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
1089
// (if using libmad fixed point library). Shifts are no longer default setup, 
1090
// but if you need to remain backward compatible, define your shift bits, which
1091
// were normally
1092
// dest_GPR = {MACHI,MACLO}[59:28]
1093
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1094
 
1095
 
1096
//////////////////////////////////////////////
1097
//
1098
// Data MMU (DMMU)
1099
//
1100
 
1101
//
1102
// Address that selects between TLB TR and MR
1103
//
1104
`define OR1200_DTLB_TM_ADDR     7
1105
 
1106
//
1107
// DTLBMR fields
1108
//
1109
`define OR1200_DTLBMR_V_BITS    0
1110
`define OR1200_DTLBMR_CID_BITS  4:1
1111
`define OR1200_DTLBMR_RES_BITS  11:5
1112
`define OR1200_DTLBMR_VPN_BITS  31:13
1113
 
1114
//
1115
// DTLBTR fields
1116
//
1117
`define OR1200_DTLBTR_CC_BITS   0
1118
`define OR1200_DTLBTR_CI_BITS   1
1119
`define OR1200_DTLBTR_WBC_BITS  2
1120
`define OR1200_DTLBTR_WOM_BITS  3
1121
`define OR1200_DTLBTR_A_BITS    4
1122
`define OR1200_DTLBTR_D_BITS    5
1123
`define OR1200_DTLBTR_URE_BITS  6
1124
`define OR1200_DTLBTR_UWE_BITS  7
1125
`define OR1200_DTLBTR_SRE_BITS  8
1126
`define OR1200_DTLBTR_SWE_BITS  9
1127
`define OR1200_DTLBTR_RES_BITS  11:10
1128
`define OR1200_DTLBTR_PPN_BITS  31:13
1129
 
1130
//
1131
// DTLB configuration
1132
//
1133
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1134
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1135
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1136
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1137
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1138
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1139
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1140
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1141
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1142
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1143
 
1144
//
1145
// Cache inhibit while DMMU is not enabled/implemented
1146
//
1147
// cache inhibited 0GB-4GB              1'b1
1148
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1149
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1150
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1151
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1152
// cached 0GB-4GB                       1'b0
1153
//
1154
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1155
 
1156
 
1157
//////////////////////////////////////////////
1158
//
1159
// Insn MMU (IMMU)
1160
//
1161
 
1162
//
1163
// Address that selects between TLB TR and MR
1164
//
1165
`define OR1200_ITLB_TM_ADDR     7
1166
 
1167
//
1168
// ITLBMR fields
1169
//
1170
`define OR1200_ITLBMR_V_BITS    0
1171
`define OR1200_ITLBMR_CID_BITS  4:1
1172
`define OR1200_ITLBMR_RES_BITS  11:5
1173
`define OR1200_ITLBMR_VPN_BITS  31:13
1174
 
1175
//
1176
// ITLBTR fields
1177
//
1178
`define OR1200_ITLBTR_CC_BITS   0
1179
`define OR1200_ITLBTR_CI_BITS   1
1180
`define OR1200_ITLBTR_WBC_BITS  2
1181
`define OR1200_ITLBTR_WOM_BITS  3
1182
`define OR1200_ITLBTR_A_BITS    4
1183
`define OR1200_ITLBTR_D_BITS    5
1184
`define OR1200_ITLBTR_SXE_BITS  6
1185
`define OR1200_ITLBTR_UXE_BITS  7
1186
`define OR1200_ITLBTR_RES_BITS  11:8
1187
`define OR1200_ITLBTR_PPN_BITS  31:13
1188
 
1189
//
1190
// ITLB configuration
1191
//
1192
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1193
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1194
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1195
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1196
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1197
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1198
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1199
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1200
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1201
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1202
 
1203
//
1204
// Cache inhibit while IMMU is not enabled/implemented
1205
// Note: all combinations that use icpu_adr_i cause async loop
1206
//
1207
// cache inhibited 0GB-4GB              1'b1
1208
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1209
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1210
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1211
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1212
// cached 0GB-4GB                       1'b0
1213
//
1214
`define OR1200_IMMU_CI                  1'b0
1215
 
1216
 
1217
/////////////////////////////////////////////////
1218
//
1219
// Insn cache (IC)
1220
//
1221
 
1222
// 3 for 8 bytes, 4 for 16 bytes etc
1223
`define OR1200_ICLS             4
1224
 
1225
//
1226
// IC configurations
1227
//
1228
`ifdef OR1200_IC_1W_512B
1229
`define OR1200_ICSIZE   9     // 512
1230
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1231
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1232
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1233
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1234
`define OR1200_ICTAG_W  24
1235
`endif
1236
`ifdef OR1200_IC_1W_4KB
1237
`define OR1200_ICSIZE                   12                      // 4096
1238
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1239
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1240
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1241
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1242
`define OR1200_ICTAG_W                  21
1243
`endif
1244
`ifdef OR1200_IC_1W_8KB
1245
`define OR1200_ICSIZE                   13                      // 8192
1246
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1247
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1248
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1249
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1250
`define OR1200_ICTAG_W                  20
1251
`endif
1252
 
1253
 
1254
/////////////////////////////////////////////////
1255
//
1256
// Data cache (DC)
1257
//
1258
 
1259
// 3 for 8 bytes, 4 for 16 bytes etc
1260
`define OR1200_DCLS             4
1261
 
1262
// Define to enable default behavior of cache as write through
1263
// Turning this off enables write back strategy
1264
//
1265
`define OR1200_DC_WRITETHROUGH
1266
 
1267
// Define to enable stores from the stack not doing writethrough.
1268
// EXPERIMENTAL
1269
//`define OR1200_DC_NOSTACKWRITETHROUGH
1270
 
1271
// Data cache SPR definitions
1272
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
1273
// Data cache group SPR addresses
1274
`define OR1200_SPRGRP_DC_DCCR           3'd0 // Not implemented
1275
`define OR1200_SPRGRP_DC_DCBPR          3'd1 // Not implemented
1276
`define OR1200_SPRGRP_DC_DCBFR          3'd2
1277
`define OR1200_SPRGRP_DC_DCBIR          3'd3
1278
`define OR1200_SPRGRP_DC_DCBWR          3'd4 // Not implemented
1279
`define OR1200_SPRGRP_DC_DCBLR          3'd5 // Not implemented
1280
 
1281
//
1282
// DC configurations
1283
//
1284
`ifdef OR1200_DC_1W_4KB
1285
`define OR1200_DCSIZE                   12                      // 4096
1286
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1287
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1288
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1289
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1290
`define OR1200_DCTAG_W                  21
1291
`endif
1292
`ifdef OR1200_DC_1W_8KB
1293
`define OR1200_DCSIZE                   13                      // 8192
1294
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1295
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1296
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1297
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1298
`define OR1200_DCTAG_W                  20
1299
`endif
1300
 
1301
 
1302
/////////////////////////////////////////////////
1303
//
1304
// Store buffer (SB)
1305
//
1306
 
1307
//
1308
// Store buffer
1309
//
1310
// It will improve performance by "caching" CPU stores
1311
// using store buffer. This is most important for function
1312
// prologues because DC can only work in write though mode
1313
// and all stores would have to complete external WB writes
1314
// to memory.
1315
// Store buffer is between DC and data BIU.
1316
// All stores will be stored into store buffer and immediately
1317
// completed by the CPU, even though actual external writes
1318
// will be performed later. As a consequence store buffer masks
1319
// all data bus errors related to stores (data bus errors
1320
// related to loads are delivered normally).
1321
// All pending CPU loads will wait until store buffer is empty to
1322
// ensure strict memory model. Right now this is necessary because
1323
// we don't make destinction between cached and cache inhibited
1324
// address space, so we simply empty store buffer until loads
1325
// can begin.
1326
//
1327
// It makes design a bit bigger, depending what is the number of
1328
// entries in SB FIFO. Number of entries can be changed further
1329
// down.
1330
//
1331
//`define OR1200_SB_IMPLEMENTED
1332
 
1333
//
1334
// Number of store buffer entries
1335
//
1336
// Verified number of entries are 4 and 8 entries
1337
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1338
// always match 2**OR1200_SB_LOG.
1339
// To disable store buffer, undefine
1340
// OR1200_SB_IMPLEMENTED.
1341
//
1342
`define OR1200_SB_LOG           2       // 2 or 3
1343
`define OR1200_SB_ENTRIES       4       // 4 or 8
1344
 
1345
 
1346
/////////////////////////////////////////////////
1347
//
1348
// Quick Embedded Memory (QMEM)
1349
//
1350
 
1351
//
1352
// Quick Embedded Memory
1353
//
1354
// Instantiation of dedicated insn/data memory (RAM or ROM).
1355
// Insn fetch has effective throughput 1insn / clock cycle.
1356
// Data load takes two clock cycles / access, data store
1357
// takes 1 clock cycle / access (if there is no insn fetch)).
1358
// Memory instantiation is shared between insn and data,
1359
// meaning if insn fetch are performed, data load/store
1360
// performance will be lower.
1361
//
1362
// Main reason for QMEM is to put some time critical functions
1363
// into this memory and to have predictable and fast access
1364
// to these functions. (soft fpu, context switch, exception
1365
// handlers, stack, etc)
1366
//
1367
// It makes design a bit bigger and slower. QMEM sits behind
1368
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1369
// used with QMEM and QMEM is seen by the CPU just like any other
1370
// memory in the system). IC/DC are sitting behind QMEM so the
1371
// whole design timing might be worse with QMEM implemented.
1372
//
1373
//`define OR1200_QMEM_IMPLEMENTED
1374
 
1375
//
1376
// Base address and mask of QMEM
1377
//
1378
// Base address defines first address of QMEM. Mask defines
1379
// QMEM range in address space. Actual size of QMEM is however
1380
// determined with instantiated RAM/ROM. However bigger
1381
// mask will reserve more address space for QMEM, but also
1382
// make design faster, while more tight mask will take
1383
// less address space but also make design slower. If
1384
// instantiated RAM/ROM is smaller than space reserved with
1385
// the mask, instatiated RAM/ROM will also be shadowed
1386
// at higher addresses in reserved space.
1387
//
1388
`define OR1200_QMEM_IADDR       32'h0080_0000
1389
`define OR1200_QMEM_IMASK       32'hfff0_0000 // Max QMEM size 1MB
1390
`define OR1200_QMEM_DADDR       32'h0080_0000
1391
`define OR1200_QMEM_DMASK       32'hfff0_0000 // Max QMEM size 1MB
1392
 
1393
//
1394
// QMEM interface byte-select capability
1395
//
1396
// To enable qmem_sel* ports, define this macro.
1397
//
1398
//`define OR1200_QMEM_BSEL
1399
 
1400
//
1401
// QMEM interface acknowledge
1402
//
1403
// To enable qmem_ack port, define this macro.
1404
//
1405
//`define OR1200_QMEM_ACK
1406
 
1407
/////////////////////////////////////////////////////
1408
//
1409
// VR, UPR and Configuration Registers
1410
//
1411
//
1412
// VR, UPR and configuration registers are optional. If 
1413
// implemented, operating system can automatically figure
1414
// out how to use the processor because it knows 
1415
// what units are available in the processor and how they
1416
// are configured.
1417
//
1418
// This section must be last in or1200_defines.v file so
1419
// that all units are already configured and thus
1420
// configuration registers are properly set.
1421
// 
1422
 
1423
// Define if you want configuration registers implemented
1424
`define OR1200_CFGR_IMPLEMENTED
1425
 
1426
// Define if you want full address decode inside SYS group
1427
`define OR1200_SYS_FULL_DECODE
1428
 
1429
// Offsets of VR, UPR and CFGR registers
1430
`define OR1200_SPRGRP_SYS_VR            4'h0
1431
`define OR1200_SPRGRP_SYS_UPR           4'h1
1432
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1433
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1434
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1435
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1436
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1437
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1438
 
1439
// VR fields
1440
`define OR1200_VR_REV_BITS              5:0
1441
`define OR1200_VR_RES1_BITS             15:6
1442
`define OR1200_VR_CFG_BITS              23:16
1443
`define OR1200_VR_VER_BITS              31:24
1444
 
1445
// VR values
1446
`define OR1200_VR_REV                   6'h08
1447
`define OR1200_VR_RES1                  10'h000
1448
`define OR1200_VR_CFG                   8'h00
1449
`define OR1200_VR_VER                   8'h12
1450
 
1451
// UPR fields
1452
`define OR1200_UPR_UP_BITS              0
1453
`define OR1200_UPR_DCP_BITS             1
1454
`define OR1200_UPR_ICP_BITS             2
1455
`define OR1200_UPR_DMP_BITS             3
1456
`define OR1200_UPR_IMP_BITS             4
1457
`define OR1200_UPR_MP_BITS              5
1458
`define OR1200_UPR_DUP_BITS             6
1459
`define OR1200_UPR_PCUP_BITS            7
1460
`define OR1200_UPR_PMP_BITS             8
1461
`define OR1200_UPR_PICP_BITS            9
1462
`define OR1200_UPR_TTP_BITS             10
1463
`define OR1200_UPR_FPP_BITS             11
1464
`define OR1200_UPR_RES1_BITS            23:12
1465
`define OR1200_UPR_CUP_BITS             31:24
1466
 
1467
// UPR values
1468
`define OR1200_UPR_UP                   1'b1
1469
`ifdef OR1200_NO_DC
1470
`define OR1200_UPR_DCP                  1'b0
1471
`else
1472
`define OR1200_UPR_DCP                  1'b1
1473
`endif
1474
`ifdef OR1200_NO_IC
1475
`define OR1200_UPR_ICP                  1'b0
1476
`else
1477
`define OR1200_UPR_ICP                  1'b1
1478
`endif
1479
`ifdef OR1200_NO_DMMU
1480
`define OR1200_UPR_DMP                  1'b0
1481
`else
1482
`define OR1200_UPR_DMP                  1'b1
1483
`endif
1484
`ifdef OR1200_NO_IMMU
1485
`define OR1200_UPR_IMP                  1'b0
1486
`else
1487
`define OR1200_UPR_IMP                  1'b1
1488
`endif
1489
`ifdef OR1200_MAC_IMPLEMENTED
1490
`define OR1200_UPR_MP                   1'b1
1491
`else
1492
`define OR1200_UPR_MP                   1'b0
1493
`endif
1494
`ifdef OR1200_DU_IMPLEMENTED
1495
`define OR1200_UPR_DUP                  1'b1
1496
`else
1497
`define OR1200_UPR_DUP                  1'b0
1498
`endif
1499
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1500
`ifdef OR1200_PM_IMPLEMENTED
1501
`define OR1200_UPR_PMP                  1'b1
1502
`else
1503
`define OR1200_UPR_PMP                  1'b0
1504
`endif
1505
`ifdef OR1200_PIC_IMPLEMENTED
1506
`define OR1200_UPR_PICP                 1'b1
1507
`else
1508
`define OR1200_UPR_PICP                 1'b0
1509
`endif
1510
`ifdef OR1200_TT_IMPLEMENTED
1511
`define OR1200_UPR_TTP                  1'b1
1512
`else
1513
`define OR1200_UPR_TTP                  1'b0
1514
`endif
1515
`ifdef OR1200_FPU_IMPLEMENTED
1516
`define OR1200_UPR_FPP                  1'b1
1517
`else
1518
`define OR1200_UPR_FPP                  1'b0
1519
`endif
1520
`define OR1200_UPR_RES1                 12'h000
1521
`define OR1200_UPR_CUP                  8'h00
1522
 
1523
// CPUCFGR fields
1524
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1525
`define OR1200_CPUCFGR_HGF_BITS     4
1526
`define OR1200_CPUCFGR_OB32S_BITS       5
1527
`define OR1200_CPUCFGR_OB64S_BITS       6
1528
`define OR1200_CPUCFGR_OF32S_BITS       7
1529
`define OR1200_CPUCFGR_OF64S_BITS       8
1530
`define OR1200_CPUCFGR_OV64S_BITS       9
1531
`define OR1200_CPUCFGR_RES1_BITS        31:10
1532
 
1533
// CPUCFGR values
1534
`define OR1200_CPUCFGR_NSGF                 4'h0
1535
`ifdef OR1200_RFRAM_16REG
1536
    `define OR1200_CPUCFGR_HGF                  1'b1
1537
`else
1538
    `define OR1200_CPUCFGR_HGF                  1'b0
1539
`endif
1540
`define OR1200_CPUCFGR_OB32S            1'b1
1541
`define OR1200_CPUCFGR_OB64S            1'b0
1542
`ifdef OR1200_FPU_IMPLEMENTED
1543
 `define OR1200_CPUCFGR_OF32S           1'b1
1544
`else
1545
 `define OR1200_CPUCFGR_OF32S           1'b0
1546
`endif
1547
 
1548
`define OR1200_CPUCFGR_OF64S            1'b0
1549
`define OR1200_CPUCFGR_OV64S            1'b0
1550
`define OR1200_CPUCFGR_RES1             22'h000000
1551
 
1552
// DMMUCFGR fields
1553
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1554
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1555
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1556
`define OR1200_DMMUCFGR_CRI_BITS        8
1557
`define OR1200_DMMUCFGR_PRI_BITS        9
1558
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1559
`define OR1200_DMMUCFGR_HTR_BITS        11
1560
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1561
 
1562
// DMMUCFGR values
1563
`ifdef OR1200_NO_DMMU
1564
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1565
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1566
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1567
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1568
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1569
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1570
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1571
`define OR1200_DMMUCFGR_RES1            20'h00000
1572
`else
1573
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1574
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1575
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1576
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1577
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1578
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1579
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1580
`define OR1200_DMMUCFGR_RES1            20'h00000
1581
`endif
1582
 
1583
// IMMUCFGR fields
1584
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1585
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1586
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1587
`define OR1200_IMMUCFGR_CRI_BITS        8
1588
`define OR1200_IMMUCFGR_PRI_BITS        9
1589
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1590
`define OR1200_IMMUCFGR_HTR_BITS        11
1591
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1592
 
1593
// IMMUCFGR values
1594
`ifdef OR1200_NO_IMMU
1595
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1596
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1597
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1598
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1599
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1600
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1601
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1602
`define OR1200_IMMUCFGR_RES1            20'h00000
1603
`else
1604
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1605
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1606
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1607
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1608
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1609
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1610
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1611
`define OR1200_IMMUCFGR_RES1            20'h00000
1612
`endif
1613
 
1614
// DCCFGR fields
1615
`define OR1200_DCCFGR_NCW_BITS          2:0
1616
`define OR1200_DCCFGR_NCS_BITS          6:3
1617
`define OR1200_DCCFGR_CBS_BITS          7
1618
`define OR1200_DCCFGR_CWS_BITS          8
1619
`define OR1200_DCCFGR_CCRI_BITS         9
1620
`define OR1200_DCCFGR_CBIRI_BITS        10
1621
`define OR1200_DCCFGR_CBPRI_BITS        11
1622
`define OR1200_DCCFGR_CBLRI_BITS        12
1623
`define OR1200_DCCFGR_CBFRI_BITS        13
1624
`define OR1200_DCCFGR_CBWBRI_BITS       14
1625
`define OR1200_DCCFGR_RES1_BITS 31:15
1626
 
1627
// DCCFGR values
1628
`ifdef OR1200_NO_DC
1629
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1630
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1631
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1632
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1633
`define OR1200_DCCFGR_CCRI              1'b0    // Irrelevant
1634
`define OR1200_DCCFGR_CBIRI             1'b0    // Irrelevant
1635
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1636
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1637
`define OR1200_DCCFGR_CBFRI             1'b0    // Irrelevant
1638
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1639
`define OR1200_DCCFGR_RES1              17'h00000
1640
`else
1641
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1642
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1643
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
1644
`ifdef OR1200_DC_WRITETHROUGH
1645
 `define OR1200_DCCFGR_CWS              1'b0    // Write-through strategy
1646
`else
1647
 `define OR1200_DCCFGR_CWS              1'b1    // Write-back strategy
1648
`endif
1649
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1650
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1651
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1652
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1653
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1654
`ifdef OR1200_DC_WRITETHROUGH
1655
 `define OR1200_DCCFGR_CBWBRI           1'b0    // Cache block WB reg not impl.
1656
`else
1657
 `define OR1200_DCCFGR_CBWBRI           1'b1    // Cache block WB reg impl.
1658
`endif
1659
`define OR1200_DCCFGR_RES1              17'h00000
1660
`endif
1661
 
1662
// ICCFGR fields
1663
`define OR1200_ICCFGR_NCW_BITS          2:0
1664
`define OR1200_ICCFGR_NCS_BITS          6:3
1665
`define OR1200_ICCFGR_CBS_BITS          7
1666
`define OR1200_ICCFGR_CWS_BITS          8
1667
`define OR1200_ICCFGR_CCRI_BITS         9
1668
`define OR1200_ICCFGR_CBIRI_BITS        10
1669
`define OR1200_ICCFGR_CBPRI_BITS        11
1670
`define OR1200_ICCFGR_CBLRI_BITS        12
1671
`define OR1200_ICCFGR_CBFRI_BITS        13
1672
`define OR1200_ICCFGR_CBWBRI_BITS       14
1673
`define OR1200_ICCFGR_RES1_BITS 31:15
1674
 
1675
// ICCFGR values
1676
`ifdef OR1200_NO_IC
1677
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1678
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1679
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1680
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1681
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1682
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1683
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1684
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1685
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1686
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1687
`define OR1200_ICCFGR_RES1              17'h00000
1688
`else
1689
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1690
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1691
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1  // 16 byte cache block
1692
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1693
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1694
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1695
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1696
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1697
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1698
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1699
`define OR1200_ICCFGR_RES1              17'h00000
1700
`endif
1701
 
1702
// DCFGR fields
1703
`define OR1200_DCFGR_NDP_BITS           3:0
1704
`define OR1200_DCFGR_WPCI_BITS          4
1705
`define OR1200_DCFGR_RES1_BITS          31:5
1706
 
1707
// DCFGR values
1708
`ifdef OR1200_DU_HWBKPTS
1709
`define OR1200_DCFGR_NDP                4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1710
`ifdef OR1200_DU_DWCR0
1711
`define OR1200_DCFGR_WPCI               1'b1
1712
`else
1713
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1714
`endif
1715
`else
1716
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
1717
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1718
`endif
1719
`define OR1200_DCFGR_RES1               27'd0
1720
 
1721
///////////////////////////////////////////////////////////////////////////////
1722
// Boot Address Selection                                                    //
1723
// This only changes where the initial reset occurs. EPH setting is still    //
1724
// used to determine where vectors are located.                              //
1725
///////////////////////////////////////////////////////////////////////////////
1726
 // Boot from 0xf0000100
1727
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
1728
`define OR1200_BOOT_ADR 32'hf0000100
1729
// Boot from 0x100
1730
// `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
1731
// `define OR1200_BOOT_ADR 32'h00000100

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