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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] [orpsoc-params.v] - Blame information for rev 408

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1 408 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// orpsoc-params                                                ////
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////                                                              ////
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//// Top level ORPSoC parameters file                             ////
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////                                                              ////
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//// Included in toplevel and testbench                           ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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///////////////////////////
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//                       //
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// Peripheral parameters //
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//                       //
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///////////////////////////
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// SPI 0 params
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parameter spi0_ss_width = 1;
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parameter spi0_wb_adr = 8'hb0;
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parameter wbs_d_spi0_data_width = 8;
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parameter spi0_wb_adr_width = 3;
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// SPI 1 params
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parameter spi1_ss_width = 1;
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parameter spi1_wb_adr = 8'hb1;
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parameter spi1_wb_adr_width = 3;
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parameter wbs_d_spi1_data_width = 8;
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// SPI 2 params
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parameter spi2_ss_width = 1;
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parameter spi2_wb_adr = 8'hb2;
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parameter spi2_wb_adr_width = 3;
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parameter wbs_d_spi2_data_width = 8;
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// i2c master slave params
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// Slave addresses
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parameter HV0_SADR  = 8'h44;
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parameter HV1_SADR  = 8'h45;
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parameter HV2_SADR  = 8'h46;
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parameter HV3_SADR  = 8'h47;
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// i2c 0 params
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parameter i2c_0_wb_adr = 8'ha0;
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parameter i2c_0_wb_adr_width = 3;
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parameter wbs_d_i2c0_data_width = 8;
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// i2c 1 params
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parameter i2c_1_wb_adr = 8'ha1;
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parameter i2c_1_wb_adr_width = 3;
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parameter wbs_d_i2c1_data_width = 8;
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// i2c 2 params
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parameter i2c_2_wb_adr = 8'ha2;
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parameter i2c_2_wb_adr_width = 3;
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parameter wbs_d_i2c2_data_width = 8;
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// i2c 3 params
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parameter i2c_3_wb_adr = 8'ha3;
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parameter i2c_3_wb_adr_width = 3;
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parameter wbs_d_i2c3_data_width = 8;
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// GPIO 0 params
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parameter wbs_d_gpio0_data_width = 8;
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parameter gpio0_wb_adr_width = 3;
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parameter gpio0_io_width = 8;
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parameter gpio0_wb_adr = 8'h91;
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parameter gpio0_dir_reset_val = 0;
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parameter gpio0_o_reset_val = 0;
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// UART 0 params
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parameter wbs_d_uart0_data_width = 8;
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parameter uart0_wb_adr = 8'h90;
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parameter uart0_data_width = 8;
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parameter uart0_addr_width = 3;
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// USB slave 0 params
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parameter wbs_d_usb0_data_width = 8;
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parameter wbs_d_usb0_adr_width = 8;
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parameter usb0_wb_adr = 8'h9c; // USB0
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// USB slave 1 params
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parameter wbs_d_usb1_data_width = 8;
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parameter wbs_d_usb1_adr_width = 8;
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parameter usb1_wb_adr = 8'h9d; // USB1
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// Flash ROM (Actel 1Kbit internal flash)
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parameter flashrom_wb_data_width = 8;
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parameter flashrom_wb_adr_width = 7;
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parameter flashrom_wb_adr = 8'hcf;
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// ROM
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parameter wbs_i_rom0_data_width = 32;
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parameter wbs_i_rom0_addr_width = 6;
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parameter rom0_wb_adr = 4'hf;
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// MC0 (SDRAM, or other)
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parameter wbs_i_mc0_data_width = 32;
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parameter wbs_d_mc0_data_width = 32;
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// Memory sizing for synthesis (small)
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parameter sdram_ba_width = 2;
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// For 8MB part, mt16lc4m16a2
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parameter sdram_row_width = 12;
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parameter sdram_col_width = 8;
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// For 32MB part, mt16lc4m16a2
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//parameter sdram_row_width = 13;
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//parameter sdram_col_width = 9;
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// ETH0 defines
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parameter eth0_wb_adr = 8'h92;
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parameter wbs_d_eth0_data_width = 32;
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parameter wbs_d_eth0_addr_width = 12;
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parameter wbm_eth0_data_width = 32;
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parameter wbm_eth0_addr_width = 32;
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// Memory sizing for synthesis (small)
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parameter internal_sram_mem_span = 32'h0080_0000;
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parameter internal_sram_adr_width_for_span = 23;
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//////////////////////////////////////////////////////
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//                                                  //
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// Wishbone bus parameters                          //
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//                                                  //
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//////////////////////////////////////////////////////
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////////////////////////
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//                    //
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// Arbiter parameters //
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//                    // 
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////////////////////////
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parameter wb_dw = 32; // Default Wishbone full word width
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parameter wb_aw = 32; // Default Wishbone full address width
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///////////////////////////
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//                       //
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// Instruction bus       //
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//                       //
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///////////////////////////
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parameter ibus_arb_addr_match_width = 4;
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// Slave addresses
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parameter ibus_arb_slave0_adr = rom0_wb_adr; // FLASH ROM
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parameter ibus_arb_slave1_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)
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///////////////////////////
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//                       //
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// Data bus              //
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//                       //
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///////////////////////////
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// Has auto foward to last slave when no address hits
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parameter dbus_arb_wb_addr_match_width = 8;
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parameter dbus_arb_wb_num_slaves = 5;
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// Slave addresses
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parameter dbus_arb_slave0_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)
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parameter dbus_arb_slave1_adr = eth0_wb_adr; // Ethernet 0
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///////////////////////////////
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//                           //
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// Byte-wide peripheral bus  //
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//                           //
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///////////////////////////////
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parameter bbus_arb_wb_addr_match_width = 8;
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parameter bbus_arb_wb_num_slaves = 12; // Update this when changing slaves!
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// Slave addresses
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parameter bbus_arb_slave0_adr  = uart0_wb_adr;
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parameter bbus_arb_slave1_adr  = gpio0_wb_adr;
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parameter bbus_arb_slave2_adr  = usb0_wb_adr;
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parameter bbus_arb_slave3_adr  = i2c_0_wb_adr;
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parameter bbus_arb_slave4_adr  = i2c_1_wb_adr;
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parameter bbus_arb_slave5_adr  = i2c_2_wb_adr;
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parameter bbus_arb_slave6_adr  = i2c_3_wb_adr;
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parameter bbus_arb_slave7_adr  = spi0_wb_adr;
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parameter bbus_arb_slave8_adr  = spi1_wb_adr;
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parameter bbus_arb_slave9_adr  = spi2_wb_adr;
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parameter bbus_arb_slave10_adr = flashrom_wb_adr;
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parameter bbus_arb_slave11_adr = usb1_wb_adr;
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parameter bbus_arb_slave12_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave13_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave14_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave15_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave16_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave17_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave18_adr = 0 /* UNASSIGNED */;
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parameter bbus_arb_slave19_adr = 0 /* UNASSIGNED */;
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