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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_bd.v] - Blame information for rev 544

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`include "sd_defines.v"
 
 
 
module sd_bd (
input clk,
input rst,
//input stb_m,
input we_m,
 
input [`RAM_MEM_WIDTH-1:0] dat_in_m,
 
output reg [`BD_WIDTH-1 :0] free_bd,
 
input  re_s,
output reg ack_o_s,
input a_cmp,
output reg[`RAM_MEM_WIDTH-1:0] dat_out_s
);
 
 reg new_bw;
reg last_a_cmp;
 
`ifdef RAM_MEM_WIDTH_32
`ifdef ACTEL
reg [`RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0]  /*synthesis syn_ramstyle = "no_rw_check"*/ ;
`else
reg [`RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0];
`endif
 
reg write_cnt;
reg read_cnt;
reg [`BD_WIDTH -1 :0] m_wr_pnt;
 
reg [`BD_WIDTH -1 :0] s_rd_pnt ;
 
 //Main side read/write  
always @(posedge clk or posedge rst )
begin
   new_bw <=0;
 
  if (rst) begin
    m_wr_pnt<=0;
 
    write_cnt<=0;
    new_bw <=0;
 
 
  end
  else if (we_m) begin
    if (free_bd >0) begin
      write_cnt <=~ write_cnt;
      m_wr_pnt<=m_wr_pnt+1;
      if (!write_cnt) begin  //First write indicate source buffer addr
        bd_mem[m_wr_pnt]<=dat_in_m;
      end
      else begin        //Second write indicate SD card block addr
        bd_mem[m_wr_pnt]<=dat_in_m;
        new_bw <=1;
      end
     end
  end
 
 
 
 
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst) begin
    free_bd <=(`BD_SIZE  /2);
  end
  else if (new_bw ) begin
    free_bd <= free_bd-1;
  end
  else if  (a_cmp) begin
     free_bd <= free_bd+1;
 
  end
 
end
 
 
//Second side read
always @(posedge clk or posedge rst)
begin
 
  if (rst) begin
    s_rd_pnt<=0;
 
  end
  else if (re_s) begin
    s_rd_pnt<=s_rd_pnt+1;
    dat_out_s<= bd_mem[s_rd_pnt];
 
 
  end
end
 
`else `ifdef RAM_MEM_WIDTH_16
`ifdef ACTEL
reg [ `RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0];  //synthesis syn_ramstyle = "no_rw_check"
`else
reg [ `RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0];
`endif
 
reg [1:0]write_cnt;
reg [1:0]read_s_cnt;
reg read_cnt;
 
reg [`BD_WIDTH -1 :0] m_wr_pnt;
 
reg [`BD_WIDTH -1 :0] s_rd_pnt ;
 
 //Main side read/write  
always @(posedge clk or posedge rst )
begin
   new_bw <=0;
 
  if (rst) begin
    m_wr_pnt<=0;
 
    write_cnt<=0;
    new_bw <=0;
    read_cnt<=0;
 
  end
  else if (we_m) begin
    if (free_bd >0) begin
      write_cnt <=write_cnt+1;
      m_wr_pnt<=m_wr_pnt+1;
      if (!write_cnt[1]) begin      //First write indicate source buffer addr (2x16)
        bd_mem[m_wr_pnt]<=dat_in_m;
      end
      else begin        //Second write indicate SD card block addr (2x16)
        bd_mem[m_wr_pnt]<=dat_in_m;
        new_bw <=write_cnt[0];      //Second 16 bytes writen, complete BD
      end
     end
  end
 
 
 
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    free_bd <=(`BD_SIZE  /4);
    last_a_cmp<=0;
  end
  else if (new_bw ) begin
    free_bd <= free_bd-1;
  end
  else if  (a_cmp) begin
    last_a_cmp <=a_cmp;
    if (!last_a_cmp)
     free_bd <= free_bd+1;
 
  end
 else
  last_a_cmp <=a_cmp;
end
 
 
//Second side read
always @(posedge clk or posedge rst)
begin
 
  if (rst) begin
    s_rd_pnt<=0;
          read_s_cnt<=0;
          ack_o_s<=0;
  end
  else if (re_s) begin
    read_s_cnt <=read_s_cnt+1;
    s_rd_pnt<=s_rd_pnt+1;
    ack_o_s<=1;
     if (!read_s_cnt[1])       //First read indicate source buffer addr (2x16)
        dat_out_s<= bd_mem[s_rd_pnt];
 
      else         //Second read indicate SD card block addr (2x16)
        dat_out_s<= bd_mem[s_rd_pnt];
 
  end
  else
    ack_o_s<=0;
end
 
 `endif
 
`endif
 
 
endmodule
 

Line No.	Rev	Author	Line
1	544	julius
2			`include "sd_defines.v"
3
4
5
6			`module sd_bd (`
7			`input clk,`
8			`input rst,`
9			`//input stb_m,`
10			`input we_m,`
11
12			input [`RAM_MEM_WIDTH-1:0] dat_in_m,
13
14			output reg [`BD_WIDTH-1 :0] free_bd,
15
16			`input re_s,`
17			`output reg ack_o_s,`
18			`input a_cmp,`
19			output reg[`RAM_MEM_WIDTH-1:0] dat_out_s
20			`);`
21
22			`reg new_bw;`
23			`reg last_a_cmp;`
24
25			`ifdef RAM_MEM_WIDTH_32
26			`ifdef ACTEL
27			reg [`RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0] /synthesis syn_ramstyle = "no_rw_check"/ ;
28			`else
29			reg [`RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0];
30			`endif
31
32			`reg write_cnt;`
33			`reg read_cnt;`
34			reg [`BD_WIDTH -1 :0] m_wr_pnt;
35
36			reg [`BD_WIDTH -1 :0] s_rd_pnt ;
37
38			`//Main side read/write`
39			`always @(posedge clk or posedge rst )`
40			`begin`
41			`new_bw <=0;`
42
43			`if (rst) begin`
44			`m_wr_pnt<=0;`
45
46			`write_cnt<=0;`
47			`new_bw <=0;`
48
49
50			`end`
51			`else if (we_m) begin`
52			`if (free_bd >0) begin`
53			`write_cnt <=~ write_cnt;`
54			`m_wr_pnt<=m_wr_pnt+1;`
55			`if (!write_cnt) begin //First write indicate source buffer addr`
56			`bd_mem[m_wr_pnt]<=dat_in_m;`
57			`end`
58			`else begin //Second write indicate SD card block addr`
59			`bd_mem[m_wr_pnt]<=dat_in_m;`
60			`new_bw <=1;`
61			`end`
62			`end`
63			`end`
64
65
66
67
68			`end`
69
70
71
72			`always @ (posedge clk or posedge rst)`
73			`begin`
74			`if (rst) begin`
75			free_bd <=(`BD_SIZE /2);
76			`end`
77			`else if (new_bw ) begin`
78			`free_bd <= free_bd-1;`
79			`end`
80			`else if (a_cmp) begin`
81			`free_bd <= free_bd+1;`
82
83			`end`
84
85			`end`
86
87
88			`//Second side read`
89			`always @(posedge clk or posedge rst)`
90			`begin`
91
92			`if (rst) begin`
93			`s_rd_pnt<=0;`
94
95			`end`
96			`else if (re_s) begin`
97			`s_rd_pnt<=s_rd_pnt+1;`
98			`dat_out_s<= bd_mem[s_rd_pnt];`
99
100
101			`end`
102			`end`
103
104			`else `ifdef RAM_MEM_WIDTH_16
105			`ifdef ACTEL
106			reg [ `RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0]; //synthesis syn_ramstyle = "no_rw_check"
107			`else
108			reg [ `RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0];
109			`endif
110
111			`reg [1:0]write_cnt;`
112			`reg [1:0]read_s_cnt;`
113			`reg read_cnt;`
114
115			reg [`BD_WIDTH -1 :0] m_wr_pnt;
116
117			reg [`BD_WIDTH -1 :0] s_rd_pnt ;
118
119			`//Main side read/write`
120			`always @(posedge clk or posedge rst )`
121			`begin`
122			`new_bw <=0;`
123
124			`if (rst) begin`
125			`m_wr_pnt<=0;`
126
127			`write_cnt<=0;`
128			`new_bw <=0;`
129			`read_cnt<=0;`
130
131			`end`
132			`else if (we_m) begin`
133			`if (free_bd >0) begin`
134			`write_cnt <=write_cnt+1;`
135			`m_wr_pnt<=m_wr_pnt+1;`
136			`if (!write_cnt[1]) begin //First write indicate source buffer addr (2x16)`
137			`bd_mem[m_wr_pnt]<=dat_in_m;`
138			`end`
139			`else begin //Second write indicate SD card block addr (2x16)`
140			`bd_mem[m_wr_pnt]<=dat_in_m;`
141			`new_bw <=write_cnt[0]; //Second 16 bytes writen, complete BD`
142			`end`
143			`end`
144			`end`
145
146
147
148			`end`
149
150			`always @(posedge clk or posedge rst)`
151			`begin`
152			`if (rst) begin`
153			free_bd <=(`BD_SIZE /4);
154			`last_a_cmp<=0;`
155			`end`
156			`else if (new_bw ) begin`
157			`free_bd <= free_bd-1;`
158			`end`
159			`else if (a_cmp) begin`
160			`last_a_cmp <=a_cmp;`
161			`if (!last_a_cmp)`
162			`free_bd <= free_bd+1;`
163
164			`end`
165			`else`
166			`last_a_cmp <=a_cmp;`
167			`end`
168
169
170			`//Second side read`
171			`always @(posedge clk or posedge rst)`
172			`begin`
173
174			`if (rst) begin`
175			`s_rd_pnt<=0;`
176			`read_s_cnt<=0;`
177			`ack_o_s<=0;`
178			`end`
179			`else if (re_s) begin`
180			`read_s_cnt <=read_s_cnt+1;`
181			`s_rd_pnt<=s_rd_pnt+1;`
182			`ack_o_s<=1;`
183			`if (!read_s_cnt[1]) //First read indicate source buffer addr (2x16)`
184			`dat_out_s<= bd_mem[s_rd_pnt];`
185
186			`else //Second read indicate SD card block addr (2x16)`
187			`dat_out_s<= bd_mem[s_rd_pnt];`
188
189			`end`
190			`else`
191			`ack_o_s<=0;`
192			`end`
193
194			`endif
195
196			`endif
197
198
199			`endmodule`
200

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_bd.v] - Blame information for rev 544