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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_cmd_master.v] - Blame information for rev 544

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Line No. Rev Author Line
1 544 julius 
`include "sd_defines.v"
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module sd_cmd_master(
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input CLK_PAD_IO,
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input RST_PAD_I,
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input New_CMD,
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input data_write,
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input data_read,
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input [31:0]ARG_REG,
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input [13:0]CMD_SET_REG,
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input [15:0] TIMEOUT_REG,
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output reg [15:0] STATUS_REG,
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output reg [31:0] RESP_1_REG,
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output reg [4:0] ERR_INT_REG,
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output reg [15:0] NORMAL_INT_REG,
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input ERR_INT_RST,
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input NORMAL_INT_RST,
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output reg [15:0] settings,
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output reg go_idle_o,
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output reg  [39:0] cmd_out,
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output reg req_out,
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output reg ack_out,
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input req_in,
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input ack_in,
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input [39:0] cmd_in,
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input [7:0] serial_status,
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input card_detect
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);
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42 
 
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`define dat_ava status[6]
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`define crc_valid status[5]
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`define small_rsp 7'b0101000
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`define big_rsp 7'b1111111
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`define CMDI CMD_SET_REG[13:8]
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`define WORD_SELECT CMD_SET_REG[7:6]
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`define CICE CMD_SET_REG[4]
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`define CRCE CMD_SET_REG[3]
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`define RTS CMD_SET_REG[1:0]
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`define CTE ERR_INT_REG[0]
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`define CCRCE ERR_INT_REG[1]
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`define CIE  ERR_INT_REG[3]
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`define EI NORMAL_INT_REG[15]
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`define CC  NORMAL_INT_REG[0]
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`define CICMD STATUS_REG[0]
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60 
 
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//-----------Types--------------------------------------------------------
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reg CRC_check_enable;
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reg index_check_enable;
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reg [6:0]response_size;
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reg card_present;
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reg [3:0]debounce;
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reg [15:0]status;
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reg [15:0]  Watchdog_Cnt;
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reg complete;
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parameter SIZE = 3;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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parameter IDLE   =  3'b001;
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parameter SETUP   =  3'b010;
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parameter EXECUTE  =  3'b100;
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reg ack_in_int;
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reg ack_q;
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reg req_q;
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reg req_in_int;
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always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
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begin
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  if (RST_PAD_I) begin
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    req_q<=0;
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    req_in_int<=0;
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 end
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else begin
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  req_q<=req_in;
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  req_in_int<=req_q;
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end
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end
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//---------------Input ports---------------
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always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
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begin
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  if (RST_PAD_I) begin
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    debounce<=0;
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    card_present<=0;
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 end
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else begin
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        if (!card_detect) begin//Card present
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                if (debounce!=4'b1111)
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                        debounce<=debounce+1'b1;
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        end
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        else
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                 debounce<=0;
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        if (debounce==4'b1111)
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       card_present<=1'b1;
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        else
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           card_present<=1'b0;
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end
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end
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always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
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begin
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  if (RST_PAD_I) begin
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    ack_q<=0;
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    ack_in_int<=0;
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 end
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else begin
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  ack_q<=ack_in;
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  ack_in_int<=ack_q;
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end
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end
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always @ ( state or New_CMD or complete or ack_in_int )
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begin : FSM_COMBO
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    next_state = 0;
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 case(state)
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 IDLE:   begin
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      if (New_CMD) begin
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          next_state = SETUP;
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      end
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      else begin
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         next_state = IDLE;
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      end
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 end
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 SETUP:begin
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    if (ack_in_int)
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       next_state = EXECUTE;
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     else
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       next_state = SETUP;
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   end
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 EXECUTE:    begin
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       if (complete) begin
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          next_state = IDLE;
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      end
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      else begin
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         next_state = EXECUTE;
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      end
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 end
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 default : next_state  = IDLE;
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 endcase
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end
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always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
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begin : FSM_SEQ
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  if (RST_PAD_I ) begin
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    state <= #1 IDLE;
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 end
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 else begin
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    state <= #1 next_state;
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 end
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end
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always @ (posedge CLK_PAD_IO or posedge RST_PAD_I   )
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begin
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 if (RST_PAD_I ) begin
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    CRC_check_enable=0;
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    complete =0;
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    RESP_1_REG = 0;
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    ERR_INT_REG =0;
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    NORMAL_INT_REG=0;
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    STATUS_REG=0;
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    status=0;
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    cmd_out =0 ;
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    settings=0;
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    response_size=0;
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    req_out=0;
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    index_check_enable=0;
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    ack_out=0;
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    Watchdog_Cnt=0;
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    `CCRCE=0;
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    `EI = 0;
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    `CC = 0;
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     go_idle_o=0;
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 end
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 else begin
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 NORMAL_INT_REG[1] = 0;
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 NORMAL_INT_REG[2] =0;
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 complete=0;
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 case(state)
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 IDLE: begin
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    go_idle_o=0;
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    req_out=0;
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                ack_out =0;
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                `CICMD =0;
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    if ( req_in_int == 1) begin     //Status change
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        status=serial_status;
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        ack_out = 1;
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    end
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 end
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 SETUP:  begin
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     NORMAL_INT_REG=0;
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     ERR_INT_REG =0;
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     index_check_enable = `CICE;
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     CRC_check_enable = `CRCE;
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    if ( (`RTS  == 2'b10 ) || ( `RTS == 2'b11)) begin
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      response_size =  7'b0101000;
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    end
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    else if (`RTS == 2'b01) begin
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      response_size = 7'b1111111;
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    end
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    else begin
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       response_size=0;
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    end
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    cmd_out[39:38]=2'b01;
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    cmd_out[37:32]=`CMDI;  //CMD_INDEX
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    cmd_out[31:0]= ARG_REG;           //CMD_Argument
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    settings[14:13]=`WORD_SELECT;             //Reserved
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    settings[12] = data_read; //Type of command
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    settings[11] = data_write;
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    settings[10:8]=3'b111;            //Delay
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    settings[7]=`CRCE;         //CRC-check
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    settings[6:0]=response_size;   //response size
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    Watchdog_Cnt = 0;
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    `CICMD =1;
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 end
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 EXECUTE: begin
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    Watchdog_Cnt = Watchdog_Cnt +1;
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    if (Watchdog_Cnt>TIMEOUT_REG) begin
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      `CTE=1;
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      `EI = 1;
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      if (ack_in == 1) begin
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         complete=1;
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      end
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      go_idle_o=1;
277 
    end
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    //Default
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    req_out=0;
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                ack_out =0;
282 
 
283 
    //Start sending when serial module is ready
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        if (ack_in_int == 1) begin
285 
                        req_out =1;
286 
          end
287 
           //Incoming New Status
288 
          else if ( req_in_int == 1) begin
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        status=serial_status;
290 
 
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        ack_out = 1;
292 
        if ( `dat_ava ) begin //Data avaible
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           complete=1;
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            `EI = 0;
295 
 
296 
           if (CRC_check_enable & ~`crc_valid) begin
297 
            `CCRCE=1;
298 
            `EI = 1;
299 
 
300 
           end
301 
           if (index_check_enable &  (cmd_out[37:32] != cmd_in [37:32]) ) begin
302 
            `CIE=1;
303 
            `EI = 1;
304 
 
305 
           end
306 
 
307 
 
308 
             `CC = 1;
309 
 
310 
             if (response_size !=0)
311 
              RESP_1_REG=cmd_in[31:0];
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313 
          // end
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         end ////Data avaible
315 
       end //Status change
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     end //EXECUTE state
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   endcase
318 
   if (ERR_INT_RST)
319 
     ERR_INT_REG=0;
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   if (NORMAL_INT_RST)
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     NORMAL_INT_REG=0;
322 
  end
323 
end
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endmodule

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