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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_data_serial_host.v] - Blame information for rev 544

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`include "sd_defines.v"
 
 
module sd_data_serial_host(
input sd_clk,
input rst,
//Tx Fifo
input [31:0] data_in ,
 
output reg rd,
//Rx Fifo
output  reg  [`SD_BUS_W-1:0] data_out ,
output reg we,
//tristate data
output reg DAT_oe_o,
output reg[`SD_BUS_W-1:0] DAT_dat_o,
input  [`SD_BUS_W-1:0] DAT_dat_i,
//Controll signals
input [1:0] start_dat,
input ack_transfer,
 
output reg busy_n,
output reg transm_complete,
output reg crc_ok
);
 
//CRC16 
reg [`SD_BUS_W-1:0] crc_in;
reg crc_en;
reg crc_rst;
wire [15:0] crc_out [`SD_BUS_W-1:0];
reg  [`SD_BUS_W-1:0] temp_in;
 
reg [10:0] transf_cnt;
parameter SIZE = 6;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE        = 6'b000001;
parameter WRITE_DAT   = 6'b000010;
parameter WRITE_CRC   = 6'b000100;
parameter WRITE_BUSY  = 6'b001000;
parameter READ_WAIT   = 6'b010000;
parameter READ_DAT    = 6'b100000;
reg [2:0] crc_status;
reg busy_int;
 
genvar i;
generate
for(i=0; i<`SD_BUS_W; i=i+1) begin:CRC_16_gen
  sd_crc_16 CRC_16_i (crc_in[i],crc_en, sd_clk, crc_rst, crc_out[i]);
end
endgenerate
 
reg ack_transfer_int;
reg ack_q;
always @ (posedge sd_clk or posedge rst   )
begin: ACK_SYNC
if (rst) begin
  ack_transfer_int <=0;
  ack_q<=0;end
else begin
  ack_q<=ack_transfer;
  ack_transfer_int<=ack_q;
  end
end
 
reg q_start_bit;
always @ (state or start_dat or q_start_bit or  transf_cnt or crc_status or busy_int or DAT_dat_i or ack_transfer_int)
begin : FSM_COMBO
 next_state  = 0;
case(state)
  IDLE: begin
   if (start_dat == 2'b01)
      next_state=WRITE_DAT;
    else if  (start_dat == 2'b10)
      next_state=READ_WAIT;
    else
      next_state=IDLE;
    end
  WRITE_DAT: begin
    if (transf_cnt >= `BIT_BLOCK)
       next_state= WRITE_CRC;
   else if (start_dat == 2'b11)
        next_state=IDLE;
    else
       next_state=WRITE_DAT;
  end
 
  WRITE_CRC: begin
    if (crc_status ==0)
       next_state= WRITE_BUSY;
    else
       next_state=WRITE_CRC;
 
  end
  WRITE_BUSY: begin
      if ( (busy_int ==1)  & ack_transfer_int)
       next_state= IDLE;
    else
       next_state  = WRITE_BUSY;
  end
 
  READ_WAIT: begin
    if (q_start_bit== 0 )
       next_state= READ_DAT;
    else
       next_state=READ_WAIT;
  end
 
  READ_DAT: begin
    if ( ack_transfer_int)  //Startbit consumed...
       next_state= IDLE;
    else if (start_dat == 2'b11)
        next_state=IDLE;
    else
       next_state=READ_DAT;
    end
 
 
 
 
 
 endcase
end
 
always @ (posedge sd_clk or posedge rst   )
 begin :START_SYNC
  if (rst ) begin
    q_start_bit<=1;
 end
 else begin
    if (!DAT_dat_i[0] & state == READ_WAIT)
    q_start_bit <= 0;
    else
    q_start_bit <= 1;
 
 end
end
 
 
//----------------Seq logic------------
always @ (posedge sd_clk or posedge rst   )
begin : FSM_SEQ
  if (rst ) begin
    state <= #1 IDLE;
 end
 else begin
    state <= #1 next_state;
 end
end
 
reg [4:0] crc_c;
reg [3:0] last_din;
reg [2:0] crc_s ;
reg [31:0] write_buf_0,write_buf_1, sd_data_out;
reg out_buff_ptr,in_buff_ptr;
reg [2:0] data_send_index;
 
always @ (negedge sd_clk or posedge rst   )
begin  : FSM_OUT
 if (rst) begin
write_buf_0<=0;
write_buf_1<=0;
   DAT_oe_o<=0;
   crc_en<=0;
   crc_rst<=1;
   transf_cnt<=0;
   crc_c<=15;
   rd<=0;
   last_din<=0;
   crc_c<=0;
   crc_in<=0;
   DAT_dat_o<=0;
   crc_status<=7;
   crc_s<=0;
   transm_complete<=0;
   busy_n<=1;
   we<=0;
   data_out<=0;
   crc_ok<=0;
   busy_int<=0;
     data_send_index<=0;
        out_buff_ptr<=0;
        in_buff_ptr<=0;
 end
 else begin
 case(state)
   IDLE: begin
      DAT_oe_o<=0;
      DAT_dat_o<=4'b1111;
      crc_en<=0;
      crc_rst<=1;
      transf_cnt<=0;
      crc_c<=16;
      crc_status<=7;
      crc_s<=0;
      we<=0;
      rd<=0;
      busy_n<=1;
          data_send_index<=0;
          out_buff_ptr<=0;
          in_buff_ptr<=0;
          transm_complete <=0;
 
   end
   WRITE_DAT: begin
 
      busy_n<=0;
      crc_ok<=0;
      transf_cnt<=transf_cnt+1;
       rd<=0;
 
 
 
      if ( (in_buff_ptr != out_buff_ptr) ||  (!transf_cnt) ) begin
        rd <=1;
       if (!in_buff_ptr)
         write_buf_0<=data_in;
       else
        write_buf_1 <=data_in;
 
       in_buff_ptr<=in_buff_ptr+1;
     end
 
      if (!out_buff_ptr)
        sd_data_out<=write_buf_0;
      else
       sd_data_out<=write_buf_1;
 
        if (transf_cnt==1) begin
 
          crc_rst<=0;
          crc_en<=1;
          `ifdef LITLE_ENDIAN
                last_din <=write_buf_0[3:0];
                crc_in<= write_buf_0[3:0];
          `endif
          `ifdef BIG_ENDIAN
                last_din <=write_buf_0[31:28];
                crc_in<= write_buf_0[31:28];
          `endif
 
          DAT_oe_o<=1;
          DAT_dat_o<=0;
 
          data_send_index<=1;
        end
        else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
          DAT_oe_o<=1;
        case (data_send_index)
          `ifdef LITLE_ENDIAN
           0:begin
              last_din <=sd_data_out[3:0];
              crc_in <=sd_data_out[3:0];
           end
           1:begin
              last_din <=sd_data_out[7:4];
              crc_in <=sd_data_out[7:4];
           end
           2:begin
              last_din <=sd_data_out[11:8];
              crc_in <=sd_data_out[11:8];
           end
           3:begin
              last_din <=sd_data_out[15:12];
              crc_in <=sd_data_out[15:12];
           end
           4:begin
              last_din <=sd_data_out[19:16];
              crc_in <=sd_data_out[19:16];
           end
           5:begin
              last_din <=sd_data_out[23:20];
              crc_in <=sd_data_out[23:20];
           end
           6:begin
              last_din <=sd_data_out[27:24];
              crc_in <=sd_data_out[27:24];
              out_buff_ptr<=out_buff_ptr+1;
           end
           7:begin
              last_din <=sd_data_out[31:28];
              crc_in <=sd_data_out[31:28];
           end
          `endif
          `ifdef BIG_ENDIAN
           0:begin
              last_din <=sd_data_out[31:28];
              crc_in <=sd_data_out[31:28];
           end
           1:begin
              last_din <=sd_data_out[27:24];
              crc_in <=sd_data_out[27:24];
           end
           2:begin
              last_din <=sd_data_out[23:20];
              crc_in <=sd_data_out[23:20];
           end
           3:begin
              last_din <=sd_data_out[19:16];
              crc_in <=sd_data_out[19:16];
           end
           4:begin
              last_din <=sd_data_out[15:12];
              crc_in <=sd_data_out[15:12];
           end
           5:begin
              last_din <=sd_data_out[11:8];
              crc_in <=sd_data_out[11:8];
           end
           6:begin
              last_din <=sd_data_out[7:4];
              crc_in <=sd_data_out[7:4];
              out_buff_ptr<=out_buff_ptr+1;
           end
           7:begin
              last_din <=sd_data_out[3:0];
              crc_in <=sd_data_out[3:0];
           end
          `endif
 
 
         endcase
          data_send_index<=data_send_index+1;
 
          DAT_dat_o<= last_din;
 
 
 
          if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
             crc_en<=0;
         end
       end
       else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
        rd<=0;
         crc_en<=0;
         crc_c<=crc_c-1;
         DAT_oe_o<=1;
         DAT_dat_o[0]<=crc_out[0][crc_c-1];
         DAT_dat_o[1]<=crc_out[1][crc_c-1];
         DAT_dat_o[2]<=crc_out[2][crc_c-1];
         DAT_dat_o[3]<=crc_out[3][crc_c-1];
       end
       else if (transf_cnt==`BIT_BLOCK-2) begin
          DAT_oe_o<=1;
          DAT_dat_o<=4'b1111;
           rd<=0;
      end
       else if (transf_cnt !=0) begin
         DAT_oe_o<=0;
         rd<=0;
         end
   end
   WRITE_CRC : begin
      rd<=0;
      DAT_oe_o<=0;
      crc_status<=crc_status-1;
      if  (( crc_status<=4) && ( crc_status>=2) )
      crc_s[crc_status-2] <=DAT_dat_i[0];
   end
   WRITE_BUSY : begin
       transm_complete <=1;
     if (crc_s == 3'b010)
       crc_ok<=1;
     else
       crc_ok<=0;
 
       busy_int<=DAT_dat_i[0];
 
 
   end
   READ_WAIT:begin
      DAT_oe_o<=0;
      crc_rst<=0;
      crc_en<=1;
      crc_in<=0;
      crc_c<=15;// end 
      busy_n<=0;
      transm_complete<=0;
   end
 
   READ_DAT: begin
 
 
     if (transf_cnt<`BIT_BLOCK_REC) begin
       we<=1;
 
       data_out<=DAT_dat_i;
       crc_in<=DAT_dat_i;
       crc_ok<=1;
       transf_cnt<=transf_cnt+1;
 
     end
     else if  ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin
       transf_cnt<=transf_cnt+1;
       crc_en<=0;
       last_din <=DAT_dat_i;
 
       if (transf_cnt> `BIT_BLOCK_REC) begin
        crc_c<=crc_c-1;
          we<=0;
        `ifdef SD_BUS_WIDTH_1
         if  (crc_out[0][crc_status] == last_din[0])
           crc_ok<=0;
        `endif
 
       `ifdef SD_BUS_WIDTH_4
          if  (crc_out[0][crc_c] != last_din[0])
           crc_ok<=0;
          if  (crc_out[1][crc_c] != last_din[1])
           crc_ok<=0;
          if  (crc_out[2][crc_c] != last_din[2])
           crc_ok<=0;
          if  (crc_out[3][crc_c] != last_din[3])
           crc_ok<=0;
 
        `endif
         `ifdef SIM
          crc_ok<=1;
       `endif
         if (crc_c==0) begin
          transm_complete <=1;
          busy_n<=0;
           we<=0;
         end
      end
    end
 
 
 
  end
 
 
 
 endcase
 
 end
 
end
 
 
 
 
 
 
 
 
 
//Sync
 
 
 
 
 
 
 
endmodule
 
 
 
 
 

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_data_serial_host.v] - Blame information for rev 544

Line No.	Rev	Author	Line
1	544	julius
2
3			`include "sd_defines.v"
4
5
6			`module sd_data_serial_host(`
7			`input sd_clk,`
8			`input rst,`
9			`//Tx Fifo`
10			`input [31:0] data_in ,`
11
12			`output reg rd,`
13			`//Rx Fifo`
14			output reg [`SD_BUS_W-1:0] data_out ,
15			`output reg we,`
16			`//tristate data`
17			`output reg DAT_oe_o,`
18			output reg[`SD_BUS_W-1:0] DAT_dat_o,
19			input [`SD_BUS_W-1:0] DAT_dat_i,
20			`//Controll signals`
21			`input [1:0] start_dat,`
22			`input ack_transfer,`
23
24			`output reg busy_n,`
25			`output reg transm_complete,`
26			`output reg crc_ok`
27			`);`
28
29			`//CRC16`
30			reg [`SD_BUS_W-1:0] crc_in;
31			`reg crc_en;`
32			`reg crc_rst;`
33			wire [15:0] crc_out [`SD_BUS_W-1:0];
34			reg [`SD_BUS_W-1:0] temp_in;
35
36			`reg [10:0] transf_cnt;`
37			`parameter SIZE = 6;`
38			`reg [SIZE-1:0] state;`
39			`reg [SIZE-1:0] next_state;`
40			`parameter IDLE = 6'b000001;`
41			`parameter WRITE_DAT = 6'b000010;`
42			`parameter WRITE_CRC = 6'b000100;`
43			`parameter WRITE_BUSY = 6'b001000;`
44			`parameter READ_WAIT = 6'b010000;`
45			`parameter READ_DAT = 6'b100000;`
46			`reg [2:0] crc_status;`
47			`reg busy_int;`
48
49			`genvar i;`
50			`generate`
51			for(i=0; i<`SD_BUS_W; i=i+1) begin:CRC_16_gen
52			`sd_crc_16 CRC_16_i (crc_in[i],crc_en, sd_clk, crc_rst, crc_out[i]);`
53			`end`
54			`endgenerate`
55
56			`reg ack_transfer_int;`
57			`reg ack_q;`
58			`always @ (posedge sd_clk or posedge rst )`
59			`begin: ACK_SYNC`
60			`if (rst) begin`
61			`ack_transfer_int <=0;`
62			`ack_q<=0;end`
63			`else begin`
64			`ack_q<=ack_transfer;`
65			`ack_transfer_int<=ack_q;`
66			`end`
67			`end`
68
69			`reg q_start_bit;`
70			`always @ (state or start_dat or q_start_bit or transf_cnt or crc_status or busy_int or DAT_dat_i or ack_transfer_int)`
71			`begin : FSM_COMBO`
72			`next_state = 0;`
73			`case(state)`
74			`IDLE: begin`
75			`if (start_dat == 2'b01)`
76			`next_state=WRITE_DAT;`
77			`else if (start_dat == 2'b10)`
78			`next_state=READ_WAIT;`
79			`else`
80			`next_state=IDLE;`
81			`end`
82			`WRITE_DAT: begin`
83			if (transf_cnt >= `BIT_BLOCK)
84			`next_state= WRITE_CRC;`
85			`else if (start_dat == 2'b11)`
86			`next_state=IDLE;`
87			`else`
88			`next_state=WRITE_DAT;`
89			`end`
90
91			`WRITE_CRC: begin`
92			`if (crc_status ==0)`
93			`next_state= WRITE_BUSY;`
94			`else`
95			`next_state=WRITE_CRC;`
96
97			`end`
98			`WRITE_BUSY: begin`
99			`if ( (busy_int ==1) & ack_transfer_int)`
100			`next_state= IDLE;`
101			`else`
102			`next_state = WRITE_BUSY;`
103			`end`
104
105			`READ_WAIT: begin`
106			`if (q_start_bit== 0 )`
107			`next_state= READ_DAT;`
108			`else`
109			`next_state=READ_WAIT;`
110			`end`
111
112			`READ_DAT: begin`
113			`if ( ack_transfer_int) //Startbit consumed...`
114			`next_state= IDLE;`
115			`else if (start_dat == 2'b11)`
116			`next_state=IDLE;`
117			`else`
118			`next_state=READ_DAT;`
119			`end`
120
121
122
123
124
125			`endcase`
126			`end`
127
128			`always @ (posedge sd_clk or posedge rst )`
129			`begin :START_SYNC`
130			`if (rst ) begin`
131			`q_start_bit<=1;`
132			`end`
133			`else begin`
134			`if (!DAT_dat_i[0] & state == READ_WAIT)`
135			`q_start_bit <= 0;`
136			`else`
137			`q_start_bit <= 1;`
138
139			`end`
140			`end`
141
142
143			`//----------------Seq logic------------`
144			`always @ (posedge sd_clk or posedge rst )`
145			`begin : FSM_SEQ`
146			`if (rst ) begin`
147			`state <= #1 IDLE;`
148			`end`
149			`else begin`
150			`state <= #1 next_state;`
151			`end`
152			`end`
153
154			`reg [4:0] crc_c;`
155			`reg [3:0] last_din;`
156			`reg [2:0] crc_s ;`
157			`reg [31:0] write_buf_0,write_buf_1, sd_data_out;`
158			`reg out_buff_ptr,in_buff_ptr;`
159			`reg [2:0] data_send_index;`
160
161			`always @ (negedge sd_clk or posedge rst )`
162			`begin : FSM_OUT`
163			`if (rst) begin`
164			`write_buf_0<=0;`
165			`write_buf_1<=0;`
166			`DAT_oe_o<=0;`
167			`crc_en<=0;`
168			`crc_rst<=1;`
169			`transf_cnt<=0;`
170			`crc_c<=15;`
171			`rd<=0;`
172			`last_din<=0;`
173			`crc_c<=0;`
174			`crc_in<=0;`
175			`DAT_dat_o<=0;`
176			`crc_status<=7;`
177			`crc_s<=0;`
178			`transm_complete<=0;`
179			`busy_n<=1;`
180			`we<=0;`
181			`data_out<=0;`
182			`crc_ok<=0;`
183			`busy_int<=0;`
184			`data_send_index<=0;`
185			`out_buff_ptr<=0;`
186			`in_buff_ptr<=0;`
187			`end`
188			`else begin`
189			`case(state)`
190			`IDLE: begin`
191			`DAT_oe_o<=0;`
192			`DAT_dat_o<=4'b1111;`
193			`crc_en<=0;`
194			`crc_rst<=1;`
195			`transf_cnt<=0;`
196			`crc_c<=16;`
197			`crc_status<=7;`
198			`crc_s<=0;`
199			`we<=0;`
200			`rd<=0;`
201			`busy_n<=1;`
202			`data_send_index<=0;`
203			`out_buff_ptr<=0;`
204			`in_buff_ptr<=0;`
205			`transm_complete <=0;`
206
207			`end`
208			`WRITE_DAT: begin`
209
210			`busy_n<=0;`
211			`crc_ok<=0;`
212			`transf_cnt<=transf_cnt+1;`
213			`rd<=0;`
214
215
216
217			`if ( (in_buff_ptr != out_buff_ptr) \|\| (!transf_cnt) ) begin`
218			`rd <=1;`
219			`if (!in_buff_ptr)`
220			`write_buf_0<=data_in;`
221			`else`
222			`write_buf_1 <=data_in;`
223
224			`in_buff_ptr<=in_buff_ptr+1;`
225			`end`
226
227			`if (!out_buff_ptr)`
228			`sd_data_out<=write_buf_0;`
229			`else`
230			`sd_data_out<=write_buf_1;`
231
232			`if (transf_cnt==1) begin`
233
234			`crc_rst<=0;`
235			`crc_en<=1;`
236			`ifdef LITLE_ENDIAN
237			`last_din <=write_buf_0[3:0];`
238			`crc_in<= write_buf_0[3:0];`
239			`endif
240			`ifdef BIG_ENDIAN
241			`last_din <=write_buf_0[31:28];`
242			`crc_in<= write_buf_0[31:28];`
243			`endif
244
245			`DAT_oe_o<=1;`
246			`DAT_dat_o<=0;`
247
248			`data_send_index<=1;`
249			`end`
250			else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
251			`DAT_oe_o<=1;`
252			`case (data_send_index)`
253			`ifdef LITLE_ENDIAN
254			`0:begin`
255			`last_din <=sd_data_out[3:0];`
256			`crc_in <=sd_data_out[3:0];`
257			`end`
258			`1:begin`
259			`last_din <=sd_data_out[7:4];`
260			`crc_in <=sd_data_out[7:4];`
261			`end`
262			`2:begin`
263			`last_din <=sd_data_out[11:8];`
264			`crc_in <=sd_data_out[11:8];`
265			`end`
266			`3:begin`
267			`last_din <=sd_data_out[15:12];`
268			`crc_in <=sd_data_out[15:12];`
269			`end`
270			`4:begin`
271			`last_din <=sd_data_out[19:16];`
272			`crc_in <=sd_data_out[19:16];`
273			`end`
274			`5:begin`
275			`last_din <=sd_data_out[23:20];`
276			`crc_in <=sd_data_out[23:20];`
277			`end`
278			`6:begin`
279			`last_din <=sd_data_out[27:24];`
280			`crc_in <=sd_data_out[27:24];`
281			`out_buff_ptr<=out_buff_ptr+1;`
282			`end`
283			`7:begin`
284			`last_din <=sd_data_out[31:28];`
285			`crc_in <=sd_data_out[31:28];`
286			`end`
287			`endif
288			`ifdef BIG_ENDIAN
289			`0:begin`
290			`last_din <=sd_data_out[31:28];`
291			`crc_in <=sd_data_out[31:28];`
292			`end`
293			`1:begin`
294			`last_din <=sd_data_out[27:24];`
295			`crc_in <=sd_data_out[27:24];`
296			`end`
297			`2:begin`
298			`last_din <=sd_data_out[23:20];`
299			`crc_in <=sd_data_out[23:20];`
300			`end`
301			`3:begin`
302			`last_din <=sd_data_out[19:16];`
303			`crc_in <=sd_data_out[19:16];`
304			`end`
305			`4:begin`
306			`last_din <=sd_data_out[15:12];`
307			`crc_in <=sd_data_out[15:12];`
308			`end`
309			`5:begin`
310			`last_din <=sd_data_out[11:8];`
311			`crc_in <=sd_data_out[11:8];`
312			`end`
313			`6:begin`
314			`last_din <=sd_data_out[7:4];`
315			`crc_in <=sd_data_out[7:4];`
316			`out_buff_ptr<=out_buff_ptr+1;`
317			`end`
318			`7:begin`
319			`last_din <=sd_data_out[3:0];`
320			`crc_in <=sd_data_out[3:0];`
321			`end`
322			`endif
323
324
325			`endcase`
326			`data_send_index<=data_send_index+1;`
327
328			`DAT_dat_o<= last_din;`
329
330
331
332			if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
333			`crc_en<=0;`
334			`end`
335			`end`
336			else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
337			`rd<=0;`
338			`crc_en<=0;`
339			`crc_c<=crc_c-1;`
340			`DAT_oe_o<=1;`
341			`DAT_dat_o[0]<=crc_out[0][crc_c-1];`
342			`DAT_dat_o[1]<=crc_out[1][crc_c-1];`
343			`DAT_dat_o[2]<=crc_out[2][crc_c-1];`
344			`DAT_dat_o[3]<=crc_out[3][crc_c-1];`
345			`end`
346			else if (transf_cnt==`BIT_BLOCK-2) begin
347			`DAT_oe_o<=1;`
348			`DAT_dat_o<=4'b1111;`
349			`rd<=0;`
350			`end`
351			`else if (transf_cnt !=0) begin`
352			`DAT_oe_o<=0;`
353			`rd<=0;`
354			`end`
355			`end`
356			`WRITE_CRC : begin`
357			`rd<=0;`
358			`DAT_oe_o<=0;`
359			`crc_status<=crc_status-1;`
360			`if (( crc_status<=4) && ( crc_status>=2) )`
361			`crc_s[crc_status-2] <=DAT_dat_i[0];`
362			`end`
363			`WRITE_BUSY : begin`
364			`transm_complete <=1;`
365			`if (crc_s == 3'b010)`
366			`crc_ok<=1;`
367			`else`
368			`crc_ok<=0;`
369
370			`busy_int<=DAT_dat_i[0];`
371
372
373			`end`
374			`READ_WAIT:begin`
375			`DAT_oe_o<=0;`
376			`crc_rst<=0;`
377			`crc_en<=1;`
378			`crc_in<=0;`
379			`crc_c<=15;// end`
380			`busy_n<=0;`
381			`transm_complete<=0;`
382			`end`
383
384			`READ_DAT: begin`
385
386
387			if (transf_cnt<`BIT_BLOCK_REC) begin
388			`we<=1;`
389
390			`data_out<=DAT_dat_i;`
391			`crc_in<=DAT_dat_i;`
392			`crc_ok<=1;`
393			`transf_cnt<=transf_cnt+1;`
394
395			`end`
396			else if ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin
397			`transf_cnt<=transf_cnt+1;`
398			`crc_en<=0;`
399			`last_din <=DAT_dat_i;`
400
401			if (transf_cnt> `BIT_BLOCK_REC) begin
402			`crc_c<=crc_c-1;`
403			`we<=0;`
404			`ifdef SD_BUS_WIDTH_1
405			`if (crc_out[0][crc_status] == last_din[0])`
406			`crc_ok<=0;`
407			`endif
408
409			`ifdef SD_BUS_WIDTH_4
410			`if (crc_out[0][crc_c] != last_din[0])`
411			`crc_ok<=0;`
412			`if (crc_out[1][crc_c] != last_din[1])`
413			`crc_ok<=0;`
414			`if (crc_out[2][crc_c] != last_din[2])`
415			`crc_ok<=0;`
416			`if (crc_out[3][crc_c] != last_din[3])`
417			`crc_ok<=0;`
418
419			`endif
420			`ifdef SIM
421			`crc_ok<=1;`
422			`endif
423			`if (crc_c==0) begin`
424			`transm_complete <=1;`
425			`busy_n<=0;`
426			`we<=0;`
427			`end`
428			`end`
429			`end`
430
431
432
433			`end`
434
435
436
437			`endcase`
438
439			`end`
440
441			`end`
442
443
444
445
446
447
448
449
450
451			`//Sync`
452
453
454
455
456
457
458
459			`endmodule`
460
461
462
463
464