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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_fifo_rx_filler.v] - Blame information for rev 544

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1 544 julius
`include "sd_defines.v"
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module sd_fifo_rx_filler
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(
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input clk,
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input rst,
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//WB Signals
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output  [31:0]  m_wb_adr_o,
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output  reg        m_wb_we_o,
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output reg [31:0]  m_wb_dat_o,
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output    reg      m_wb_cyc_o,
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output   reg       m_wb_stb_o,
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input           m_wb_ack_i,
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output  reg     [2:0] m_wb_cti_o,
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output  reg [1:0]         m_wb_bte_o,
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//Data Master Control signals
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input en,
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input [31:0] adr,
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//Data Serial signals 
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input sd_clk,
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input [`SD_BUS_W-1:0] dat_i,
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input wr,
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output full
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//
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);
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 wire [31:0] dat_o;
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reg rd;
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reg reset_rx_fifo;
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sd_rx_fifo Rx_Fifo (
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.d ( dat_i ),
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.wr  (  wr ),
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.wclk  (sd_clk),
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.q ( dat_o),
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.rd (rd),
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.full (full),
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.empty (empty),
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.mem_empt (),
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.rclk (clk),
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.rst  (rst | reset_rx_fifo)
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);
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//reg [31:0] tmp_dat;
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reg [8:0] offset;
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assign  m_wb_adr_o = adr+offset;
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//assign  m_wb_dat_o = dat_o;
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reg wb_free;
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always @(posedge clk or posedge rst )begin
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 if (rst) begin
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  offset<=0;
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  m_wb_we_o <=0;
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        m_wb_cyc_o <= 0;
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        m_wb_stb_o <= 0;
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        wb_free<=1;
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        m_wb_dat_o<=0;
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        rd<=0;
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        reset_rx_fifo<=1;
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        m_wb_bte_o <= 2'b00;
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                m_wb_cti_o <= 3'b000;
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 end
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 else if (en)  begin//Start filling the RX buffer
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    rd<=0;
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    reset_rx_fifo<=0;
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  if (!empty & wb_free) begin
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    rd<=1;
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    m_wb_dat_o<=#1 dat_o;
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    m_wb_we_o <=#1 1;
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                m_wb_cyc_o <=#1 1;
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                m_wb_stb_o <=#1 1;
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    wb_free<=0;
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  end
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  if(  !wb_free & m_wb_ack_i) begin
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    m_wb_we_o <=0;
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                m_wb_cyc_o <= 0;
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                m_wb_stb_o <= 0;
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                offset<=offset+`MEM_OFFSET;
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                wb_free<=1;
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        end
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end
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else begin
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   reset_rx_fifo<=1;
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    rd<=0;
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   offset<=0;
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        m_wb_cyc_o <= 0;
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                        m_wb_stb_o <= 0;
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                        m_wb_we_o <=0;
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                        wb_free<=1;
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  end
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end
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endmodule
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