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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_rx_fifo.v] - Blame information for rev 544

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1 544 julius
`include "sd_defines.v"
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`include "timescale.v"
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module sd_rx_fifo
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  (
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   input [4-1:0] d,
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   input wr,
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   input wclk,
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   output [32-1:0] q,
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   input rd,
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   output full,
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   output empty,
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   output [1:0] mem_empt,
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   input rclk,
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   input rst
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   );
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   reg [32-1:0] ram [0:`FIFO_RX_MEM_DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
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   reg [`FIFO_RX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
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   wire ram_we;
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   wire [32-1:0] ram_din;
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   reg [8-1:0] we;
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   reg [4*(8)-1:0] tmp;
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   reg ft;
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   always @ (posedge wclk or posedge rst)
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     if (rst)
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       we <= 8'h1;
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     else
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       if (wr)
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         we <= {we[8-2:0],we[8-1]};
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   always @ (posedge wclk or posedge rst)
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     if (rst) begin
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       tmp <= {4*(8-1){1'b0}};
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         ft<=0;
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   end
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     else
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       begin
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         `ifdef BIG_ENDIAN
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          if (wr & we[7]) begin
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            tmp[4*1-1:4*0] <= d;
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            ft<=1; end
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          if (wr & we[6])
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            tmp[4*2-1:4*1] <= d;
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          if (wr & we[5])
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            tmp[4*3-1:4*2] <= d;
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          if (wr & we[4])
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            tmp[4*4-1:4*3] <= d;
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          if (wr & we[3])
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            tmp[4*5-1:4*4] <= d;
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          if (wr & we[2])
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            tmp[4*6-1:4*5] <= d;
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          if (wr & we[1])
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            tmp[4*7-1:4*6] <= d;
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          if (wr & we[0])
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            tmp[4*8-1:4*7] <= d;
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         `endif
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         `ifdef LITTLE_ENDIAN
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          if (wr & we[0])
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           tmp[4*1-1:4*0] <= d;
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          if (wr & we[1])
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            tmp[4*2-1:4*1] <= d;
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          if (wr & we[2])
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            tmp[4*3-1:4*2] <= d;
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          if (wr & we[3])
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           tmp[4*4-1:4*3] <= d;
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          if (wr & we[4])
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           tmp[4*5-1:4*4] <= d;
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          if (wr & we[5])
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           tmp[4*6-1:4*5] <= d;
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          if (wr & we[6])
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           tmp[4*7-1:4*6] <= d;
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          if (wr & we[7]) begin
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           tmp[4*8-1:4*7] <= d;
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               ft<=1;
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     end
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      `endif
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  end
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   assign ram_we = wr & we[0] &ft;
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   assign ram_din = tmp;
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   always @ (posedge wclk)
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     if (ram_we)
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       ram[adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0]] <= ram_din;
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   always @ (posedge wclk or posedge rst)
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     if (rst)
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       adr_i <= `FIFO_RX_MEM_ADR_SIZE'h0;
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     else
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       if (ram_we)
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         if (adr_i == `FIFO_RX_MEM_DEPTH-1) begin
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           adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
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           adr_i[`FIFO_RX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_RX_MEM_ADR_SIZE-1];
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         end
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         else
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           adr_i <= adr_i + `FIFO_RX_MEM_ADR_SIZE'h1;
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   always @ (posedge rclk or posedge rst)
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     if (rst)
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       adr_o <= `FIFO_RX_MEM_ADR_SIZE'h0;
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     else
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       if (!empty & rd)
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         if (adr_o == `FIFO_RX_MEM_DEPTH-1) begin
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            adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
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            adr_o[`FIFO_RX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_RX_MEM_ADR_SIZE-1];
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         end
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         else
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           adr_o <= adr_o + `FIFO_RX_MEM_ADR_SIZE'h1;
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//------------------------------------------------------------------
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// Simplified version of the three necessary full-tests:
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// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
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// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
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// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
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//------------------------------------------------------------------
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   assign full =  (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;
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   assign empty = (adr_i == adr_o) ;
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   assign mem_empt = ( adr_i-adr_o);
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   assign q = ram[adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0]];
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endmodule

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