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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_rx_fifo.v] - Blame information for rev 707

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`include "sd_defines.v"
`include "timescale.v"
module sd_rx_fifo
  (
   input [4-1:0] d,
   input wr,
   input wclk,
   output [32-1:0] q,
   input rd,
   output full,
   output empty,
   output [1:0] mem_empt,
   input rclk,
   input rst
   );
   reg [32-1:0] ram [0:`FIFO_RX_MEM_DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
   reg [`FIFO_RX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
   wire ram_we;
   wire [32-1:0] ram_din;
   reg [8-1:0] we;
   reg [4*(8)-1:0] tmp;
   reg ft;
   always @ (posedge wclk or posedge rst)
     if (rst)
       we <= 8'h1;
     else
       if (wr)
         we <= {we[8-2:0],we[8-1]};
 
   always @ (posedge wclk or posedge rst)
     if (rst) begin
       tmp <= {4*(8-1){1'b0}};
         ft<=0;
   end
     else
       begin
         `ifdef BIG_ENDIAN
 
          if (wr & we[7]) begin
            tmp[4*1-1:4*0] <= d;
            ft<=1; end
          if (wr & we[6])
            tmp[4*2-1:4*1] <= d;
          if (wr & we[5])
            tmp[4*3-1:4*2] <= d;
          if (wr & we[4])
            tmp[4*4-1:4*3] <= d;
          if (wr & we[3])
            tmp[4*5-1:4*4] <= d;
          if (wr & we[2])
            tmp[4*6-1:4*5] <= d;
          if (wr & we[1])
            tmp[4*7-1:4*6] <= d;
          if (wr & we[0])
            tmp[4*8-1:4*7] <= d;
         `endif
         `ifdef LITTLE_ENDIAN
          if (wr & we[0])
           tmp[4*1-1:4*0] <= d;
          if (wr & we[1])
            tmp[4*2-1:4*1] <= d;
          if (wr & we[2])
            tmp[4*3-1:4*2] <= d;
          if (wr & we[3])
           tmp[4*4-1:4*3] <= d;
          if (wr & we[4])
           tmp[4*5-1:4*4] <= d;
          if (wr & we[5])
           tmp[4*6-1:4*5] <= d;
          if (wr & we[6])
           tmp[4*7-1:4*6] <= d;
          if (wr & we[7]) begin
           tmp[4*8-1:4*7] <= d;
               ft<=1;
     end
      `endif
  end
 
   assign ram_we = wr & we[0] &ft;
   assign ram_din = tmp;
   always @ (posedge wclk)
     if (ram_we)
       ram[adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0]] <= ram_din;
   always @ (posedge wclk or posedge rst)
     if (rst)
       adr_i <= `FIFO_RX_MEM_ADR_SIZE'h0;
     else
       if (ram_we)
         if (adr_i == `FIFO_RX_MEM_DEPTH-1) begin
           adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
           adr_i[`FIFO_RX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_RX_MEM_ADR_SIZE-1];
         end
         else
           adr_i <= adr_i + `FIFO_RX_MEM_ADR_SIZE'h1;
 
   always @ (posedge rclk or posedge rst)
     if (rst)
       adr_o <= `FIFO_RX_MEM_ADR_SIZE'h0;
     else
       if (!empty & rd)
 
         if (adr_o == `FIFO_RX_MEM_DEPTH-1) begin
            adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
            adr_o[`FIFO_RX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_RX_MEM_ADR_SIZE-1];
         end
         else
           adr_o <= adr_o + `FIFO_RX_MEM_ADR_SIZE'h1;
 
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
 
   assign full =  (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;
   assign empty = (adr_i == adr_o) ;
 
   assign mem_empt = ( adr_i-adr_o);
   assign q = ram[adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0]];
endmodule

Line No.	Rev	Author	Line
1	544	julius	`include "sd_defines.v"
2			`include "timescale.v"
3			`module sd_rx_fifo`
4			`(`
5			`input [4-1:0] d,`
6			`input wr,`
7			`input wclk,`
8			`output [32-1:0] q,`
9			`input rd,`
10			`output full,`
11			`output empty,`
12			`output [1:0] mem_empt,`
13			`input rclk,`
14			`input rst`
15			`);`
16			reg [32-1:0] ram [0:`FIFO_RX_MEM_DEPTH-1] /synthesis syn_ramstyle = "no_rw_check"/ ;
17			reg [`FIFO_RX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
18			`wire ram_we;`
19			`wire [32-1:0] ram_din;`
20			`reg [8-1:0] we;`
21			`reg [4*(8)-1:0] tmp;`
22			`reg ft;`
23			`always @ (posedge wclk or posedge rst)`
24			`if (rst)`
25			`we <= 8'h1;`
26			`else`
27			`if (wr)`
28			`we <= {we[8-2:0],we[8-1]};`
29
30			`always @ (posedge wclk or posedge rst)`
31			`if (rst) begin`
32			`tmp <= {4*(8-1){1'b0}};`
33			`ft<=0;`
34			`end`
35			`else`
36			`begin`
37			`ifdef BIG_ENDIAN
38
39			`if (wr & we[7]) begin`
40			`tmp[41-1:40] <= d;`
41			`ft<=1; end`
42			`if (wr & we[6])`
43			`tmp[42-1:41] <= d;`
44			`if (wr & we[5])`
45			`tmp[43-1:42] <= d;`
46			`if (wr & we[4])`
47			`tmp[44-1:43] <= d;`
48			`if (wr & we[3])`
49			`tmp[45-1:44] <= d;`
50			`if (wr & we[2])`
51			`tmp[46-1:45] <= d;`
52			`if (wr & we[1])`
53			`tmp[47-1:46] <= d;`
54			`if (wr & we[0])`
55			`tmp[48-1:47] <= d;`
56			`endif
57			`ifdef LITTLE_ENDIAN
58			`if (wr & we[0])`
59			`tmp[41-1:40] <= d;`
60			`if (wr & we[1])`
61			`tmp[42-1:41] <= d;`
62			`if (wr & we[2])`
63			`tmp[43-1:42] <= d;`
64			`if (wr & we[3])`
65			`tmp[44-1:43] <= d;`
66			`if (wr & we[4])`
67			`tmp[45-1:44] <= d;`
68			`if (wr & we[5])`
69			`tmp[46-1:45] <= d;`
70			`if (wr & we[6])`
71			`tmp[47-1:46] <= d;`
72			`if (wr & we[7]) begin`
73			`tmp[48-1:47] <= d;`
74			`ft<=1;`
75			`end`
76			`endif
77			`end`
78
79			`assign ram_we = wr & we[0] &ft;`
80			`assign ram_din = tmp;`
81			`always @ (posedge wclk)`
82			`if (ram_we)`
83			ram[adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0]] <= ram_din;
84			`always @ (posedge wclk or posedge rst)`
85			`if (rst)`
86			adr_i <= `FIFO_RX_MEM_ADR_SIZE'h0;
87			`else`
88			`if (ram_we)`
89			if (adr_i == `FIFO_RX_MEM_DEPTH-1) begin
90			adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
91			adr_i[`FIFO_RX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_RX_MEM_ADR_SIZE-1];
92			`end`
93			`else`
94			adr_i <= adr_i + `FIFO_RX_MEM_ADR_SIZE'h1;
95
96			`always @ (posedge rclk or posedge rst)`
97			`if (rst)`
98			adr_o <= `FIFO_RX_MEM_ADR_SIZE'h0;
99			`else`
100			`if (!empty & rd)`
101
102			if (adr_o == `FIFO_RX_MEM_DEPTH-1) begin
103			adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
104			adr_o[`FIFO_RX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_RX_MEM_ADR_SIZE-1];
105			`end`
106			`else`
107			adr_o <= adr_o + `FIFO_RX_MEM_ADR_SIZE'h1;
108
109			`//------------------------------------------------------------------`
110			`// Simplified version of the three necessary full-tests:`
111			`// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&`
112			`// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&`
113			`// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));`
114			`//------------------------------------------------------------------`
115
116			assign full = (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;
117			`assign empty = (adr_i == adr_o) ;`
118
119			`assign mem_empt = ( adr_i-adr_o);`
120			assign q = ram[adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0]];
121			`endmodule`

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_rx_fifo.v] - Blame information for rev 707