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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [sdc_controller/] [sd_rx_fifo_tb.v] - Blame information for rev 544

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1 544 julius
// module name
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`define MODULE_NAME sd_rx_fifo
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module sd_rx_fifo_tb ( );
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   reg [4-1:0] d;
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   reg wr;
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   reg wclk;
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   wire [32-1:0] q;
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   reg rd;
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   wire fe;
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   reg rclk;
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   reg rst;
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   wire  empty;
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   reg [31:0] slask;
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   wire [1:0] mem_empt;
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  sd_rx_fifo sd_rx_fifo_1(
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   .d (d),
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   .wr (wr),
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   .wclk (wclk),
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   .q (q),
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   .rd (rd),
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   .full (fe),
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   .empty (empty),
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   .mem_empt (mem_empt),
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   .rclk (rclk),
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   .rst (rst)
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   );
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event reset_trigger;
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event  reset_done_trigger;
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event start_trigger;
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event start_done_trigger;
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reg [3:0] send [16:0];
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reg [3:0] send_c;
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reg start;
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reg sw;
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initial
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   begin
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     wclk=0;
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     rst=0;
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     rclk=0;
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     d =0;
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     rst=0;
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     wr=0;
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     #5 ->reset_trigger;
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     send [0] = 4'ha;
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     send [1] = 4'hb;
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     send [2] = 4'hc;
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     send [3] = 4'hd;
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     send [4] = 4'he;
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     send [5] = 4'hf;
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     send [6] = 4'hd;
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     send [7] = 4'hc;
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     send [8] = 4'hf;
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     send [9] = 4'he;
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     send [10] = 4'hd;
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     send [11] = 4'hc;
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     send [12] = 4'hb;
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     send [13] = 4'ha;
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     send [14] = 4'ha;
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     send [15] = 4'hb;
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     send_c =0;
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     sw=0;
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     start=0;
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end
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always begin
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  #5 rclk = !rclk;
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 end
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always begin
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  #10 wclk = !wclk;
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 end
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 initial begin
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    forever begin
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      @ (reset_trigger);
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      @ (posedge wclk);
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      rst =1 ;
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      @ (posedge wclk);
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      rst = 0;
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      #20
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      start=1;
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      -> reset_done_trigger;
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    end
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  end
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always @ (posedge rclk)
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if (!empty) begin
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     rd=1;
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    slask =q;
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end
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else
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  rd=0;
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always @ (posedge wclk)
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begin
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if(start)
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   sw=~sw;
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   if (sw) begin
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   d=send[send_c];
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   wr=1;
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   send_c=send_c+1;  end
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   else begin
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     wr=0;
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   end
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 //  if (!rd) begin
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  //    @ (posedge rclk);
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//       slask =q; 
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//   rd=1;
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//  @ (posedge rclk);
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//   rd=0;
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//  end
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end
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endmodule
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