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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [rtl/] [verilog/] [cke_delay_counter_defines.v] - Blame information for rev 411

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Line No. Rev Author Line
1 408 julius 
// module name
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`define CNT_MODULE_NAME cke_delay_counter
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// counter type = [BINARY, GRAY, LFSR]
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`define CNT_TYPE_BINARY
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//`define CNT_TYPE_GRAY
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//`define CNT_TYPE_LFSR
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// q as output
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`define CNT_Q
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// for gray type counter optional binary output
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//`define CNT_Q_BIN
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// number of CNT bins
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`define CNT_LENGTH 15
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// clear
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//`define CNT_CLEAR
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// async reset
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`define CNT_RESET_VALUE `CNT_LENGTH'h0
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// set
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//`define CNT_SET
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`define CNT_SET_VALUE `CNT_LENGTH'h0
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// wrap around creates shorter cycle than maximum length
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//`define CNT_WRAP
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`define CNT_WRAP_VALUE `CNT_LENGTH'h6200
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// clock enable
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`define CNT_CE
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// q_next as an output
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//`define CNT_QNEXT
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// q=0 as an output
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//`define CNT_Z
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// q_next=0 as a registered output
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//`define CNT_ZQ
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