OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [rtl/] [verilog/] [dcm_pll.v] - Blame information for rev 411

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius 
`include "versatile_mem_ctrl_defines.v"
2 
 
3 
module dcm_pll
4 
  (
5 
   input  rst,          // reset
6 
   input  clk_in,       // clock in
7 
   input  clkfb_in,     // feedback clock in
8 
   output clk0_out,     // clock out
9 
   output clk90_out,    // clock out, 90 degree phase shift
10 
   output clk180_out,   // clock out, 180 degree phase shift
11 
   output clk270_out,   // clock out, 270 degree phase shift
12 
   output clkfb_out     // feedback clock out
13 
   );
14 
 
15 
`ifdef XILINX
16 
   wire clk_in_ibufg;
17 
   wire clk0_bufg, clk90_bufg, clk180_bufg, clk270_bufg;
18 
   // DCM with internal feedback
19 
   DCM #(
20 
      .CLKDV_DIVIDE(2.0),
21 
      .CLKFX_DIVIDE(1),
22 
      .CLKFX_MULTIPLY(4),
23 
      .CLKIN_DIVIDE_BY_2("FALSE"),
24 
      .CLKIN_PERIOD(8.0),
25 
      .CLKOUT_PHASE_SHIFT("NONE"),
26 
      .CLK_FEEDBACK("1X"),
27 
      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
28 
      .DLL_FREQUENCY_MODE("LOW"),
29 
      .DUTY_CYCLE_CORRECTION("TRUE"),
30 
      .PHASE_SHIFT(0),
31 
      .STARTUP_WAIT("FALSE"))
32 
   DCM_internal (
33 
      .CLK0(clk0_bufg),
34 
      .CLK180(clk180_bufg),
35 
      .CLK270(clk270_bufg),
36 
      .CLK2X(),
37 
      .CLK2X180(),
38 
      .CLK90(clk90_bufg),
39 
      .CLKDV(),
40 
      .CLKFX(),
41 
      .CLKFX180(),
42 
      .LOCKED(),
43 
      .PSDONE(),
44 
      .STATUS(),
45 
      .CLKFB(clk0_out),
46 
      .CLKIN(clk_in_ibufg),
47 
      .DSSEN(),
48 
      .PSCLK(),
49 
      .PSEN(),
50 
      .PSINCDEC(),
51 
      .RST(rst)
52 
   );
53 
   // DCM with external feedback
54 
   DCM #(
55 
      .CLKDV_DIVIDE(2.0),
56 
      .CLKFX_DIVIDE(1),
57 
      .CLKFX_MULTIPLY(4),
58 
      .CLKIN_DIVIDE_BY_2("FALSE"),
59 
      .CLKIN_PERIOD(8.0),
60 
      .CLKOUT_PHASE_SHIFT("NONE"),
61 
      .CLK_FEEDBACK("1X"),
62 
      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
63 
      .DLL_FREQUENCY_MODE("LOW"),
64 
      .DUTY_CYCLE_CORRECTION("TRUE"),
65 
      .PHASE_SHIFT(0),
66 
      .STARTUP_WAIT("FALSE"))
67 
   DCM_external (
68 
      .CLK0(clkfb_bufg),
69 
      .CLK180(),
70 
      .CLK270(),
71 
      .CLK2X(),
72 
      .CLK2X180(),
73 
      .CLK90(),
74 
      .CLKDV(),
75 
      .CLKFX(),
76 
      .CLKFX180(),
77 
      .LOCKED(),
78 
      .PSDONE(),
79 
      .STATUS(),
80 
      .CLKFB(clkfb_ibufg),
81 
      .CLKIN(clk_in_ibufg),
82 
      .DSSEN(),
83 
      .PSCLK(),
84 
      .PSEN(),
85 
      .PSINCDEC(),
86 
      .RST(rst)
87 
   );
88 
 
89 
   // Input buffer on DCM clock source
90 
   IBUFG IBUFG_clk (
91 
     .I(clk_in),
92 
     .O(clk_in_ibufg));
93 
 
94 
   // Global buffers on DCM generated clocks
95 
   BUFG BUFG_0 (
96 
     .I(clk0_bufg),
97 
     .O(clk0_out));
98 
   BUFG BUFG_90 (
99 
     .I(clk90_bufg),
100 
     .O(clk90_out));
101 
   BUFG BUFG_180 (
102 
     .I(clk180_bufg),
103 
     .O(clk180_out));
104 
   BUFG BUFG_270 (
105 
     .I(clk270_bufg),
106 
     .O(clk270_out));
107 
 
108 
   // External feedback to DCM
109 
   IBUFG IBUFG_clkfb (
110 
     .I(clkfb_in),
111 
     .O(clkfb_ibufg));
112 
   OBUF OBUF_clkfb (
113 
     .I(clkfb_bufg),
114 
     .O(clkfb_out));
115 
`endif   // XILINX
116 
 
117 
 
118 
`ifdef ALTERA
119 
   wire [9:0] sub_wire0;
120 
   wire [0:0] sub_wire8 = 1'h0;
121 
   wire [3:3] sub_wire4 = sub_wire0[3:3];
122 
   wire [2:2] sub_wire3 = sub_wire0[2:2];
123 
   wire [1:1] sub_wire2 = sub_wire0[1:1];
124 
   wire [0:0] sub_wire1 = sub_wire0[0:0];
125 
   wire       sub_wire6 = clk_in;
126 
   wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
127 
 
128 
   assign clk0_out   = sub_wire1;
129 
   assign clk90_out  = sub_wire2;
130 
   assign clk180_out = sub_wire3;
131 
   assign clk270_out = sub_wire4;
132 
 
133 
   // PLL with external feedback
134 
   altpll #(
135 
     .bandwidth_type("AUTO"),
136 
     .clk0_divide_by(1),
137 
     .clk0_duty_cycle(50),
138 
     .clk0_multiply_by(1),
139 
     .clk0_phase_shift("0"),
140 
     .clk1_divide_by(1),
141 
     .clk1_duty_cycle(50),
142 
     .clk1_multiply_by(1),
143 
     .clk1_phase_shift("1250"),
144 
     .clk2_divide_by(1),
145 
     .clk2_duty_cycle(50),
146 
     .clk2_multiply_by(1),
147 
     .clk2_phase_shift("2500"),
148 
     .clk3_divide_by(1),
149 
     .clk3_duty_cycle(50),
150 
     .clk3_multiply_by(1),
151 
     .clk3_phase_shift("3750"),
152 
     .compensate_clock("CLK0"),
153 
     .inclk0_input_frequency(5000),
154 
     .intended_device_family("Stratix III"),
155 
     .lpm_hint("UNUSED"),
156 
     .lpm_type("altpll"),
157 
     .operation_mode("NORMAL"),
158 
//   .operation_mode("SOURCE_SYNCHRONOUS"),
159 
     .pll_type("AUTO"),
160 
     .port_activeclock("PORT_UNUSED"),
161 
     .port_areset("PORT_USED"),
162 
     .port_clkbad0("PORT_UNUSED"),
163 
     .port_clkbad1("PORT_UNUSED"),
164 
     .port_clkloss("PORT_UNUSED"),
165 
     .port_clkswitch("PORT_UNUSED"),
166 
     .port_configupdate("PORT_UNUSED"),
167 
     .port_fbin("PORT_USED"),
168 
     .port_fbout("PORT_USED"),
169 
     .port_inclk0("PORT_USED"),
170 
     .port_inclk1("PORT_UNUSED"),
171 
     .port_locked("PORT_UNUSED"),
172 
     .port_pfdena("PORT_UNUSED"),
173 
     .port_phasecounterselect("PORT_UNUSED"),
174 
     .port_phasedone("PORT_UNUSED"),
175 
     .port_phasestep("PORT_UNUSED"),
176 
     .port_phaseupdown("PORT_UNUSED"),
177 
     .port_pllena("PORT_UNUSED"),
178 
     .port_scanaclr("PORT_UNUSED"),
179 
     .port_scanclk("PORT_UNUSED"),
180 
     .port_scanclkena("PORT_UNUSED"),
181 
     .port_scandata("PORT_UNUSED"),
182 
     .port_scandataout("PORT_UNUSED"),
183 
     .port_scandone("PORT_UNUSED"),
184 
     .port_scanread("PORT_UNUSED"),
185 
     .port_scanwrite("PORT_UNUSED"),
186 
     .port_clk0("PORT_USED"),
187 
     .port_clk1("PORT_USED"),
188 
     .port_clk2("PORT_USED"),
189 
     .port_clk3("PORT_USED"),
190 
     .port_clk4("PORT_UNUSED"),
191 
     .port_clk5("PORT_UNUSED"),
192 
     .port_clk6("PORT_UNUSED"),
193 
     .port_clk7("PORT_UNUSED"),
194 
     .port_clk8("PORT_UNUSED"),
195 
     .port_clk9("PORT_UNUSED"),
196 
     .port_clkena0("PORT_UNUSED"),
197 
     .port_clkena1("PORT_UNUSED"),
198 
     .port_clkena2("PORT_UNUSED"),
199 
     .port_clkena3("PORT_UNUSED"),
200 
     .port_clkena4("PORT_UNUSED"),
201 
     .port_clkena5("PORT_UNUSED"),
202 
     .using_fbmimicbidir_port("OFF"),
203 
     .width_clock(10))
204 
   altpll_internal (
205 
     .fbin (),//(clkfb_in),
206 
     .inclk (sub_wire7),
207 
     .areset (rst),
208 
     .clk (sub_wire0),
209 
     .fbout (),//(clkfb_out),
210 
     .activeclock (),
211 
     .clkbad (),
212 
     .clkena ({6{1'b1}}),
213 
     .clkloss (),
214 
     .clkswitch (1'b0),
215 
     .configupdate (1'b0),
216 
     .enable0 (),
217 
     .enable1 (),
218 
     .extclk (),
219 
     .extclkena ({4{1'b1}}),
220 
     .fbmimicbidir (),
221 
     .locked (),
222 
     .pfdena (1'b1),
223 
     .phasecounterselect ({4{1'b1}}),
224 
     .phasedone (),
225 
     .phasestep (1'b1),
226 
     .phaseupdown (1'b1),
227 
     .pllena (1'b1),
228 
     .scanaclr (1'b0),
229 
     .scanclk (1'b0),
230 
     .scanclkena (1'b1),
231 
     .scandata (1'b0),
232 
     .scandataout (),
233 
     .scandone (),
234 
     .scanread (1'b0),
235 
     .scanwrite (1'b0),
236 
     .sclkout0 (),
237 
     .sclkout1 (),
238 
     .vcooverrange (),
239 
     .vcounderrange ()
240 
   );
241 
`endif   // ALTERA
242 
 
243 
//`ifdef GENERIC_PRIMITIVES
244 
//`endif   // GENERIC_PRIMITIVES
245 
 
246 
 
247 
endmodule   // dcm_pll
248 
 
249 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.