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`include "versatile_mem_ctrl_defines.v"
 
module ddr_ff_in
  (
   input  C0,   // clock
   input  C1,   // clock
   input  D,    // data input
   input  CE,   // clock enable
   output Q0,   // data output
   output Q1,   // data output
   input  R,    // reset
   input  S     // set
   );
 
`ifdef XILINX
   IDDR2 #(
     .DDR_ALIGNMENT("NONE"),
     .INIT_Q0(1'b0),
     .INIT_Q1(1'b0),
     .SRTYPE("SYNC"))
   IDDR2_inst (
     .Q0(Q0),
     .Q1(Q1),
     .C0(C0),
     .C1(C1),
     .CE(CE),
     .D(D),
     .R(R),
     .S(S)
   );
`endif   // XILINX
 
`ifdef ALTERA
   altddio_in #(
     .WIDTH(1),
     .POWER_UP_HIGH("OFF"),
     .INTENDED_DEVICE_FAMILY("Stratix III"))
   altddio_in_inst (
     .aset(),
     .datain(D),
     .inclocken(CE),
     .inclock(C0),
     .aclr(R),
     .dataout_h(Q0),
     .dataout_l(Q1)
   );
`endif   // ALTERA
 
`ifdef GENERIC_PRIMITIVES
   reg Q0_i, Q1_i;
   always @ (posedge R or posedge C0)
     if (R)
       Q0_i <= 1'b0;
     else
       Q0_i <= D;
 
   assign Q0 = Q0_i;
 
   always @ (posedge R or posedge C1)
     if (R)
       Q1_i <= 1'b0;
     else
       Q1_i <= D;
 
   assign Q1 = Q1_i;
`endif   // GENERIC_PRIMITIVES
 
endmodule   // ddr_ff_in
 
 
module ddr_ff_out
  (
   input  C0,   // clock
   input  C1,   // clock
   input  D0,   // data input
   input  D1,   // data input
   input  CE,   // clock enable
   output Q,    // data output
   input  R,    // reset
   input  S     // set
   );
 
`ifdef XILINX
   ODDR2 #(
     .DDR_ALIGNMENT("NONE"),
     .INIT(1'b0),
     .SRTYPE("SYNC"))
   ODDR2_inst (
     .Q(Q),
     .C0(C0),
     .C1(C1),
     .CE(CE),
     .D0(D0),
     .D1(D1),
     .R(R),
     .S(S)
   );
`endif   // XILINX
 
`ifdef ALTERA
   altddio_out #(
     .WIDTH(1),
     .POWER_UP_HIGH("OFF"),
     .INTENDED_DEVICE_FAMILY("Stratix III"),
     .OE_REG("UNUSED"))
   altddio_out_inst (
     .aset(),
     .datain_h(D0),
     .datain_l(D1),
     .outclocken(CE),
     .outclock(C0),
     .aclr(R),
     .dataout(Q)
   );
`endif   // ALTERA
 
`ifdef GENERIC_PRIMITIVES
   reg Q0, Q1;
   always @ (posedge R or posedge C0)
     if (R)
       Q0 <= 1'b0;
     else
       Q0 <= D0;
 
   always @ (posedge R or posedge C1)
     if (R)
       Q1 <= 1'b0;
     else
       Q1 <= D1;
 
   assign Q = C0 ? Q0 : Q1;
`endif   // GENERIC_PRIMITIVES
 
endmodule   // ddr_ff_out
 

Line No.	Rev	Author	Line
1	408	julius	`include "versatile_mem_ctrl_defines.v"
2
3			`module ddr_ff_in`
4			`(`
5			`input C0, // clock`
6			`input C1, // clock`
7			`input D, // data input`
8			`input CE, // clock enable`
9			`output Q0, // data output`
10			`output Q1, // data output`
11			`input R, // reset`
12			`input S // set`
13			`);`
14
15			`ifdef XILINX
16			`IDDR2 #(`
17			`.DDR_ALIGNMENT("NONE"),`
18			`.INIT_Q0(1'b0),`
19			`.INIT_Q1(1'b0),`
20			`.SRTYPE("SYNC"))`
21			`IDDR2_inst (`
22			`.Q0(Q0),`
23			`.Q1(Q1),`
24			`.C0(C0),`
25			`.C1(C1),`
26			`.CE(CE),`
27			`.D(D),`
28			`.R(R),`
29			`.S(S)`
30			`);`
31			`endif // XILINX
32
33			`ifdef ALTERA
34			`altddio_in #(`
35			`.WIDTH(1),`
36			`.POWER_UP_HIGH("OFF"),`
37			`.INTENDED_DEVICE_FAMILY("Stratix III"))`
38			`altddio_in_inst (`
39			`.aset(),`
40			`.datain(D),`
41			`.inclocken(CE),`
42			`.inclock(C0),`
43			`.aclr(R),`
44			`.dataout_h(Q0),`
45			`.dataout_l(Q1)`
46			`);`
47			`endif // ALTERA
48
49			`ifdef GENERIC_PRIMITIVES
50			`reg Q0_i, Q1_i;`
51			`always @ (posedge R or posedge C0)`
52			`if (R)`
53			`Q0_i <= 1'b0;`
54			`else`
55			`Q0_i <= D;`
56
57			`assign Q0 = Q0_i;`
58
59			`always @ (posedge R or posedge C1)`
60			`if (R)`
61			`Q1_i <= 1'b0;`
62			`else`
63			`Q1_i <= D;`
64
65			`assign Q1 = Q1_i;`
66			`endif // GENERIC_PRIMITIVES
67
68			`endmodule // ddr_ff_in`
69
70
71			`module ddr_ff_out`
72			`(`
73			`input C0, // clock`
74			`input C1, // clock`
75			`input D0, // data input`
76			`input D1, // data input`
77			`input CE, // clock enable`
78			`output Q, // data output`
79			`input R, // reset`
80			`input S // set`
81			`);`
82
83			`ifdef XILINX
84			`ODDR2 #(`
85			`.DDR_ALIGNMENT("NONE"),`
86			`.INIT(1'b0),`
87			`.SRTYPE("SYNC"))`
88			`ODDR2_inst (`
89			`.Q(Q),`
90			`.C0(C0),`
91			`.C1(C1),`
92			`.CE(CE),`
93			`.D0(D0),`
94			`.D1(D1),`
95			`.R(R),`
96			`.S(S)`
97			`);`
98			`endif // XILINX
99
100			`ifdef ALTERA
101			`altddio_out #(`
102			`.WIDTH(1),`
103			`.POWER_UP_HIGH("OFF"),`
104			`.INTENDED_DEVICE_FAMILY("Stratix III"),`
105			`.OE_REG("UNUSED"))`
106			`altddio_out_inst (`
107			`.aset(),`
108			`.datain_h(D0),`
109			`.datain_l(D1),`
110			`.outclocken(CE),`
111			`.outclock(C0),`
112			`.aclr(R),`
113			`.dataout(Q)`
114			`);`
115			`endif // ALTERA
116
117			`ifdef GENERIC_PRIMITIVES
118			`reg Q0, Q1;`
119			`always @ (posedge R or posedge C0)`
120			`if (R)`
121			`Q0 <= 1'b0;`
122			`else`
123			`Q0 <= D0;`
124
125			`always @ (posedge R or posedge C1)`
126			`if (R)`
127			`Q1 <= 1'b0;`
128			`else`
129			`Q1 <= D1;`
130
131			`assign Q = C0 ? Q0 : Q1;`
132			`endif // GENERIC_PRIMITIVES
133
134			`endmodule // ddr_ff_out`
135

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [rtl/] [verilog/] [ddr_ff.v] - Blame information for rev 724