OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] [rtl/] [verilog/] [latency_counter_defines.v] - Blame information for rev 408

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius
// module name
2
`define CNT_MODULE_NAME latency_counter
3
 
4
// counter type = [BINARY, GRAY, LFSR]
5
`define CNT_TYPE_BINARY
6
//`define CNT_TYPE_GRAY
7
//`define CNT_TYPE_LFSR
8
 
9
// q as output
10
//`define CNT_Q
11
// for gray type counter optional binary output
12
//`define CNT_Q_BIN
13
 
14
// number of CNT bins
15
`define CNT_LENGTH 4
16
 
17
// clear
18
//`define CNT_CLEAR
19
 
20
// async reset
21
`define CNT_RESET_VALUE `CNT_LENGTH'h0
22
 
23
// set
24
//`define CNT_SET
25
`define CNT_SET_VALUE `CNT_LENGTH'h0
26
 
27
// wrap around creates shorter cycle than maximum length
28
`define CNT_WRAP
29
`define CNT_WRAP_VALUE `CNT_LENGTH'd3
30
 
31
// clock enable
32
`define CNT_CE
33
 
34
// q_next as an output
35
//`define CNT_QNEXT
36
 
37
// q=0 as an output
38
//`define CNT_Z
39
 
40
// q_next=0 as a registered output
41
`define CNT_ZQ
42
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.