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408 |
julius |
######################################################################
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#### ####
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#### ORPSoCv2 Testbenches Makefile ####
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#### ####
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#### Description ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### configuring and running different tests on the current ####
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#### ORPSoC(v2) design. ####
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#### ####
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#### To do: ####
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#### ####
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#### Author(s): ####
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#### - Julius Baxter, julius@opencores.org ####
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#### ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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# Name of the directory we're currently in
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CUR_DIR=$(shell pwd)
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# The root path of the whole project
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PROJECT_ROOT ?=$(CUR_DIR)/../../../../..
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DESIGN_NAME=orpsoc
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RTL_TESTBENCH_TOP=$(DESIGN_NAME)_testbench
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# Hardset the board name, even though we could probably determine it
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FPGA_VENDOR=actel
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BOARD_NAME=ordb1a3pe1500
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BOARD_DIR=$(PROJECT_ROOT)/boards/$(FPGA_VENDOR)/$(BOARD_NAME)
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# Export BOARD_PATH for the software makefiles
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468 |
julius |
BOARD=$(FPGA_VENDOR)/$(BOARD_NAME)
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export BOARD
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408 |
julius |
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# Paths to other important parts of this test suite
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COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl
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COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog
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#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
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BOARD_RTL_DIR=$(BOARD_DIR)/rtl
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BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
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# Only 1 include path for board builds - their own!
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BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
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BOARD_BENCH_DIR=$(BOARD_DIR)/bench
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BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
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BOARD_BENCH_VERILOG_INCLUDE_DIR=$(BOARD_BENCH_VERILOG_DIR)/include
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COMMON_BENCH_DIR=$(PROJECT_ROOT)
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COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog
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COMMON_BENCH_VERILOG_INCLUDE_DIR=$(COMMON_BENCH_VERILOG_DIR)/include
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# Top level files for DUT and testbench
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DUT_TOP=$(BOARD_RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v
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BENCH_TOP=$(BOARD_BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
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# Software tests we'll run
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# Need this for individual test variables to not break
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TEST ?= or1200-simple
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TESTS ?= or1200-simple or1200-cbasic or1200-dctest or1200-float or1200-mmu or1200-basic or1200-except or1200-tick or1200-ticksyscall uart-simple
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# Gets turned into verilog `define
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SIM_TYPE=RTL
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# Main defines file is from board include path
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PROJECT_VERILOG_DEFINES=$(BOARD_RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
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# Detect technology to use for the simulation
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DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
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# Rule to look at what defines are being extracted from main file
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print-defines:
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@echo echo; echo "\t### Design defines ###"; echo;
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@echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
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@echo $(DESIGN_DEFINES)
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print-tests:
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@echo; echo; echo "\t### Software tests to be run ###"; echo;
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@echo $(TESTS)
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@echo
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# Simulation directories
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SIM_DIR ?=$(BOARD_DIR)/sim
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RTL_SIM_DIR=$(SIM_DIR)
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RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
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RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
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RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
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# Testbench paths
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BOARD_BENCH_DIR=$(BOARD_DIR)/bench
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BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
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COMMON_BENCH_DIR=$(PROJECT_ROOT)/bench
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COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog
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#BENCH_VHDL_DIR=$(BENCH_DIR)/vhdl
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# No SystemC or Verilator support for this build
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#BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
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#BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
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#BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
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# Backend directories
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# This one is the board build's backend dir.
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BOARD_BACKEND_DIR=$(BOARD_DIR)/backend
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BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog
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TECHNOLOGY_BACKEND_DIR=$(BOARD_DIR)/../backend
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# This path is for the technology library
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TECHNOLOGY_BACKEND_VERILOG_DIR=$(TECHNOLOGY_BACKEND_DIR)/rtl/verilog
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411 |
julius |
# Synthesis directory for board
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BOARD_SYN_DIR=$(BOARD_DIR)/syn/synplify
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BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out
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408 |
julius |
# System software dir
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COMMON_SW_DIR=$(PROJECT_ROOT)/sw
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BOARD_SW_DIR=$(BOARD_DIR)/sw
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# BootROM code, which generates a verilog array select values
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BOOTROM_FILE=bootrom.v
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BOOTROM_SW_DIR=$(BOARD_SW_DIR)/bootrom
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BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
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BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
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bootrom: $(BOOTROM_VERILOG)
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$(BOOTROM_VERILOG): $(BOOTROM_SRC)
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$(Q)echo; echo "\t### Generating bootup ROM ###"; echo
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$(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
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# Suffix of file to check after each test for the string
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TEST_OUT_FILE_SUFFIX=-general.log
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TEST_OK_STRING=8000000d
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# Dynamically generated verilog file defining configuration for various things
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# Rule actually generating this is found in definesgen.inc file.
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TEST_DEFINES_VLG=test-defines.v
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# Set V=1 when calling make to enable verbose output
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# mainly for debugging purposes.
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ifeq ($(V), 1)
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Q=
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QUIET=
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else
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Q ?=@
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QUIET=-quiet
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endif
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# Modelsim variables
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MGC_VSIM=vsim
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MGC_VLOG_COMP=vlog
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MGC_VHDL_COMP=vcom
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MODELSIM=modelsim
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# Default simulator is Modelsim here as we're using the ProASIC3
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# libraries which are not compilable with Icarus.
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# Set SIMULATOR=modelsim to use Modelsim (Default)
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# Set SIMULATOR=ncverilog to use Cadence's NC-Verilog - TODO
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# Set SIMULATOR=icarus to use Icarus Verilog (Not supported for this board)
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SIMULATOR ?= $(MODELSIM)
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#
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# Modelsim-specific settings
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#
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VOPT_ARGS=$(QUIET) -suppress 2241
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# If VCD dump is desired, tell Modelsim not to optimise
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# away everything.
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ifeq ($(VCD), 1)
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#VOPT_ARGS=-voptargs="+acc=rnp"
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VOPT_ARGS=+acc=rnpqv
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endif
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# VSIM commands
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# Suppressed warnings - 3009: Failed to open $readmemh() file
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# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
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# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
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VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
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# Modelsim VPI settings
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ifeq ($(VPI), 1)
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VPI_LIBS=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
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VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
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endif
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# Rule to make the VPI library for modelsim
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$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB): $(VPI_SRCS)
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$(MAKE) -C $(VPI_SRC_C_DIR) $(MODELTECH_VPILIB)
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#
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# Verilog DUT source variables
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#
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411 |
julius |
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# First consider any modules we'll use gatelevel descriptions of.
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# These will have to be set on the command line
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GATELEVEL_MODULES ?=
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408 |
julius |
# First we get a list of modules in the RTL path of the board's path.
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# Next we check which modules not in the board's RTL path are in the root RTL
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# path (modules which can be commonly instantiated, but over which board
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# build-specific versions take precedence.)
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# Paths under board/***/rtl/verilog we wish to exclude when getting modules
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411 |
julius |
BOARD_VERILOG_MODULES_EXCLUDE= include $(GATELEVEL_MODULES)
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408 |
julius |
BOARD_VERILOG_MODULES_DIR_LIST=$(shell ls $(BOARD_RTL_VERILOG_DIR))
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# Apply exclude to list of modules
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BOARD_RTL_VERILOG_MODULES=$(filter-out $(BOARD_VERILOG_MODULES_EXCLUDE),$(BOARD_VERILOG_MODULES_DIR_LIST))
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# Rule for debugging this script
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print-board-modules:
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@echo echo; echo "\t### Board verilog modules ###"; echo
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@echo $(BOARD_RTL_VERILOG_MODULES)
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# Now get list of modules that we don't have a version of in the board path
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COMMON_VERILOG_MODULES_EXCLUDE= include
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COMMON_VERILOG_MODULES_EXCLUDE += $(BOARD_RTL_VERILOG_MODULES)
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411 |
julius |
COMMON_VERILOG_MODULES_EXCLUDE += $(GATELEVEL_MODULES)
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240 |
408 |
julius |
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COMMON_RTL_VERILOG_MODULES_DIR_LIST=$(shell ls $(COMMON_RTL_VERILOG_DIR))
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COMMON_RTL_VERILOG_MODULES=$(filter-out $(COMMON_VERILOG_MODULES_EXCLUDE), $(COMMON_RTL_VERILOG_MODULES_DIR_LIST))
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244 |
411 |
julius |
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# Add these to exclude their RTL directories from being included in scripts
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408 |
julius |
# Rule for debugging this script
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print-common-modules-exclude:
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@echo echo; echo "\t### Common verilog modules being excluded due to board versions ###"; echo
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@echo "$(COMMON_VERILOG_MODULES_EXCLUDE)"
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print-common-modules:
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@echo echo; echo "\t### Verilog modules from common RTL dir ###"; echo
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@echo $(COMMON_RTL_VERILOG_MODULES)
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# List of verilog source files (only .v files!)
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# Board RTL modules first
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RTL_VERILOG_SRC=$(shell for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then ls $(BOARD_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
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# Common RTL module source
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RTL_VERILOG_SRC +=$(shell for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then ls $(COMMON_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
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# List of verilog includes from board RTL path - only for rule sensitivity
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RTL_VERILOG_INCLUDES=$(shell ls $(BOARD_RTL_VERILOG_INCLUDE_DIR)/*.*)
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print-verilog-src:
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@echo echo; echo "\t### Verilog source ###"; echo
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@echo $(RTL_VERILOG_SRC)
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# Rules to make RTL we might need
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# Expects modules, if they need making, to have their top verilog file to
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# correspond to their module name, and the directory should have a make file
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# and rule which works for this command.
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# Add name of module to this list, currently only does verilog ones.
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# Rule 'rtl' is called just before generating DUT modelsim compilation script
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RTL_TO_CHECK=
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rtl:
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$(Q)for module in $(RTL_TO_CHECK); do \
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$(MAKE) -C $(RTL_VERILOG_DIR)/$$module $$module.v; \
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done
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282 |
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#
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# VHDL DUT source variables
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#
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# VHDL modules
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#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
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# VHDL sources
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#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do if [ -d $(RTL_VHDL_DIR)/$$module ]; then ls $(RTL_VHDL_DIR)/$$module/*.vhd; fi; done)
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#print-vhdl-src:
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# @echo echo; echo "\t### VHDL modules and source ###"; echo
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# @echo "modules: "; echo $(RTL_VHDL_MODULES); echo
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# @echo "source: "$(RTL_VHDL_SRC)
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#
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# Testbench source
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#
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BOARD_BENCH_VERILOG_SRC=$(shell ls $(BOARD_BENCH_VERILOG_DIR)/*.v | grep -v $(DESIGN_NAME)_testbench )
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BOARD_BENCH_VERILOG_SRC_FILES=$(notdir $(BOARD_BENCH_VERILOG_SRC))
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300 |
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301 |
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# Now only take the source from the common path that we don't already have in
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302 |
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# our board's
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COMMON_BENCH_VERILOG_DIR_LS=$(shell ls $(COMMON_BENCH_VERILOG_DIR)/*.v)
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COMMON_BENCH_VERILOG_SRC_FILES=$(notdir $(COMMON_BENCH_VERILOG_DIR_LS))
|
305 |
|
|
COMMON_BENCH_VERILOG_SRC_FILTERED=$(filter-out $(BOARD_BENCH_VERILOG_SRC_FILES) $(DESIGN_NAME)_testbench.v,$(COMMON_BENCH_VERILOG_SRC_FILES))
|
306 |
|
|
COMMON_BENCH_VERILOG_SRC=$(addprefix $(COMMON_BENCH_VERILOG_DIR)/, $(COMMON_BENCH_VERILOG_SRC_FILTERED))
|
307 |
|
|
|
308 |
|
|
print-board-bench-src:
|
309 |
|
|
$(Q)echo "\tBoard bench verilog source"; \
|
310 |
|
|
echo $(BOARD_BENCH_VERILOG_SRC)
|
311 |
|
|
|
312 |
|
|
print-common-bench-src:
|
313 |
|
|
$(Q)echo "\Common bench verilog source"; \
|
314 |
|
|
echo $(COMMON_BENCH_VERILOG_SRC)
|
315 |
|
|
|
316 |
|
|
# Testbench source subdirectory detection (exclude include, we always use
|
317 |
|
|
# board bench include directory!)
|
318 |
|
|
BOARD_BENCH_VERILOG_SUBDIRS=$(shell cd $(BOARD_BENCH_VERILOG_DIR) && ls -d */ | grep -v include)
|
319 |
|
|
COMMON_BENCH_VERILOG_SUBDIRS=$(shell cd $(COMMON_BENCH_VERILOG_DIR) && ls -d */ | grep -v include)
|
320 |
|
|
|
321 |
|
|
# Get rid of ones we have a copy of locally
|
322 |
|
|
COMMON_BENCH_VERILOG_SUBDIRS_EXCLUDE_BOARDS=$(filter-out $(BOARD_BENCH_VERILOG_SUBDIRS),$(COMMON_BENCH_VERILOG_SUBDIRS))
|
323 |
|
|
|
324 |
|
|
# Construct list of paths we will want to include
|
325 |
|
|
BENCH_VERILOG_SUBDIRS=$(addprefix $(COMMON_BENCH_VERILOG_DIR)/,$(COMMON_BENCH_VERILOG_SUBDIRS_EXCLUDE_BOARDS))
|
326 |
|
|
BENCH_VERILOG_SUBDIRS += $(addprefix $(BOARD_BENCH_VERILOG_DIR)/,$(BOARD_BENCH_VERILOG_SUBDIRS))
|
327 |
|
|
|
328 |
|
|
# Finally, add include path from local bench path
|
329 |
|
|
BENCH_VERILOG_SUBDIRS += $(BOARD_BENCH_VERILOG_DIR)/include
|
330 |
|
|
|
331 |
|
|
print-board-bench-subdirs:
|
332 |
|
|
$(Q)echo "\tBoard bench subdirectories"; \
|
333 |
|
|
echo $(BOARD_BENCH_VERILOG_SUBDIRS)
|
334 |
|
|
|
335 |
|
|
print-common-bench-subdirs:
|
336 |
|
|
$(Q)echo "\tCommon bench subdirectories"; \
|
337 |
|
|
echo $(COMMON_BENCH_VERILOG_SUBDIRS)
|
338 |
|
|
|
339 |
|
|
print-bench-subdirs:
|
340 |
|
|
$(Q)echo "\tBench subdirectories"; \
|
341 |
|
|
echo $(BENCH_VERILOG_SUBDIRS)
|
342 |
|
|
|
343 |
|
|
|
344 |
|
|
# Backend technology library files
|
345 |
|
|
# We don't do this for the board backend stuff - that should all be properly
|
346 |
|
|
# named, and so we only need to pass the "-y" option for that path.
|
347 |
|
|
BACKEND_TECHNOLOGY_VERILOG_SRC=$(shell ls $(TECHNOLOGY_BACKEND_VERILOG_DIR)/*.v )
|
348 |
|
|
BOARD_BACKEND_VERILOG_SRC=$(shell ls $(BOARD_BACKEND_VERILOG_DIR)/*.v )
|
349 |
|
|
|
350 |
|
|
#
|
351 |
|
|
# Compile script generation rules:
|
352 |
|
|
#
|
353 |
|
|
|
354 |
|
|
# Modelsim library compilation rules
|
355 |
|
|
|
356 |
|
|
# Backend script generation - make these rules sensitive to source and includes
|
357 |
|
|
modelsim_backend.scr: $(BOARD_BACKEND_VERILOG_SRC)
|
358 |
|
|
$(Q)echo "+incdir+"$(TECHNOLOGY_BACKEND_VERILOG_DIR) > $@;
|
359 |
|
|
$(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@
|
360 |
|
|
$(Q)echo "+libext+.v" >> $@;
|
361 |
|
|
$(Q)for vsrc in $(BACKEND_TECHNOLOGY_VERILOG_SRC); do echo $$vsrc >> $@; done
|
362 |
|
|
$(Q)echo >> $@;
|
363 |
|
|
|
364 |
|
|
# DUT compile script
|
365 |
|
|
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
|
366 |
|
|
$(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) > $@;
|
367 |
|
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
368 |
|
|
$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) >> $@;
|
369 |
|
|
$(Q)echo "+libext+.v" >> $@;
|
370 |
|
|
$(Q)for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(BOARD_RTL_VERILOG_DIR)/$$module >> $@; fi; done
|
371 |
|
|
$(Q)for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(COMMON_RTL_VERILOG_DIR)/$$module >> $@; fi; done
|
372 |
|
|
$(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@;
|
373 |
411 |
julius |
$(Q)if [ ! -z "$$GATELEVEL_MODULES" ]; \
|
374 |
|
|
then echo "-y " $(BOARD_SYN_OUT_DIR) >> $@; \
|
375 |
|
|
echo "+libext+.vm" >> $@; \
|
376 |
|
|
fi
|
377 |
408 |
julius |
$(Q)echo >> $@
|
378 |
|
|
|
379 |
|
|
modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC)
|
380 |
|
|
$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) > $@;
|
381 |
|
|
$(Q)echo "+incdir+"$(COMMON_BENCH_VERILOG_INCLUDE_DIR) >> $@;
|
382 |
|
|
$(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "+incdir+"$$path >> $@; done
|
383 |
|
|
$(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "-y "$$path >> $@; done
|
384 |
|
|
$(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) >> $@;
|
385 |
|
|
$(Q)echo "+libext+.v" >> $@;
|
386 |
|
|
$(Q)for vsrc in $(BOARD_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
|
387 |
|
|
$(Q)for vsrc in $(COMMON_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
|
388 |
|
|
$(Q)echo >> $@
|
389 |
|
|
|
390 |
|
|
# Modelsim library compilation rules
|
391 |
|
|
# Actel backend library
|
392 |
|
|
BACKEND_LIB=lib_backend
|
393 |
|
|
$(BACKEND_LIB): modelsim_backend.scr
|
394 |
|
|
$(Q)if [ ! -e $@ ]; then vlib $@; fi
|
395 |
|
|
$(Q)echo; echo "\t### Compiling Actel backend library ###"; echo
|
396 |
|
|
$(Q)vlog -nologo $(QUIET) -work $@ -f $<
|
397 |
|
|
|
398 |
|
|
# Compile DUT into "work" library
|
399 |
|
|
work: modelsim_dut.scr
|
400 |
|
|
$(Q)if [ ! -e $@ ]; then vlib $@; fi
|
401 |
|
|
$(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
|
402 |
|
|
$(Q)vlog $(QUIET) -f $< $(DUT_TOP)
|
403 |
|
|
|
404 |
|
|
# Single compile rule
|
405 |
|
|
.PHONY : $(MODELSIM)
|
406 |
|
|
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
|
407 |
|
|
$(Q)echo; echo "\t### Compiling testbench ###"; echo
|
408 |
|
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
|
409 |
|
|
$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -L $(BACKEND_LIB) \
|
410 |
|
|
-o tb
|
411 |
|
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
412 |
|
|
$(Q)vsim $(VSIM_ARGS) tb
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
.PHONY: rtl-test
|
416 |
|
|
rtl-test: clean-sim-test-sw sw clean-test-defines $(TEST_DEFINES_VLG) \
|
417 |
|
|
$(SIMULATOR)
|
418 |
|
|
|
419 |
|
|
# Run an RTL test followed by checking of generated results
|
420 |
|
|
rtl-test-with-check: rtl-test
|
421 |
|
|
$(Q)$(MAKE) check-test-log; \
|
422 |
|
|
if [ $$? -ne 0 ]; then \
|
423 |
|
|
echo; echo "\t### "$(TEST)" test FAIL ###"; echo; \
|
424 |
|
|
else \
|
425 |
|
|
echo; echo "\t### "$(TEST)" test OK ###"; echo; \
|
426 |
|
|
fi
|
427 |
|
|
|
428 |
|
|
# Do check, don't print anything out
|
429 |
|
|
rtl-test-with-check-no-print: rtl-test check-test-log
|
430 |
|
|
|
431 |
|
|
# Main RTL test loop
|
432 |
|
|
rtl-tests:
|
433 |
|
|
$(Q)for test in $(TESTS); do \
|
434 |
|
|
export TEST=$$test; \
|
435 |
|
|
$(MAKE) rtl-test-with-check-no-print; \
|
436 |
|
|
if [ $$? -ne 0 ]; then break; fi; \
|
437 |
|
|
echo; echo "\t### $$test test OK ###"; echo; \
|
438 |
|
|
done
|
439 |
|
|
|
440 |
|
|
|
441 |
|
|
.PHONY: check-test-log
|
442 |
|
|
check-test-log:
|
443 |
|
|
$(Q)echo "#!/bin/bash" > $@
|
444 |
|
|
$(Q)echo "function check-test-log { if [ \`grep -c -i "$(TEST_OK_STRING)" "$(RTL_SIM_RESULTS_DIR)"/"$(TEST)$(TEST_OUT_FILE_SUFFIX)"\` -gt 0 ]; then return 0; else return 1; fi; }" >> $@
|
445 |
|
|
$(Q)echo "check-test-log" >> $@
|
446 |
|
|
$(Q)chmod +x $@
|
447 |
|
|
$(Q) echo; echo "\t### Checking simulation results for "$(TEST)" test ###"; echo;
|
448 |
|
|
$(Q)./$@
|
449 |
|
|
|
450 |
|
|
# Include the test-defines.v generation rule
|
451 |
|
|
include $(PROJECT_ROOT)/sim/bin/definesgen.inc
|
452 |
|
|
|
453 |
|
|
#
|
454 |
|
|
# Software make rules (called recursively)
|
455 |
|
|
#
|
456 |
|
|
|
457 |
|
|
# Path for the current test
|
458 |
|
|
# First check for a local copy of the test. If it doesn't exist then we
|
459 |
|
|
# default to the software tests in the root directory
|
460 |
|
|
TEST_MODULE=$(shell echo $(TEST) | cut -d "-" -f 1)
|
461 |
|
|
BOARD_SW_TEST_DIR=$(BOARD_SW_DIR)/tests/$(TEST_MODULE)/sim
|
462 |
|
|
COMMON_SW_TEST_DIR=$(COMMON_SW_DIR)/tests/$(TEST_MODULE)/sim
|
463 |
|
|
# Do this by testing for the file's existence
|
464 |
|
|
SW_TEST_DIR=$(shell if [ -e $(BOARD_SW_TEST_DIR)/$(TEST).[cS] ]; then echo $(BOARD_SW_TEST_DIR); else echo $(COMMON_SW_TEST_DIR); fi)
|
465 |
|
|
|
466 |
|
|
print-test-sw-dir:
|
467 |
|
|
@echo; echo "\tTest software is in the following path"; echo;
|
468 |
|
|
@echo $(BOARD_SW_DIR); echo;
|
469 |
|
|
@echo $(BOARD_SW_TEST_DIR); echo;
|
470 |
|
|
@echo $(SW_TEST_DIR); echo;
|
471 |
|
|
|
472 |
|
|
print-sw-tests:
|
473 |
|
|
$(Q) $(MAKE) -C $(COMMON_SW_DIR)/lib print-sw-tests
|
474 |
|
|
$(Q) $(MAKE) -C $(COMMON_SW_DIR)/lib print-sw-tests-subdirs
|
475 |
|
|
|
476 |
|
|
|
477 |
|
|
# Name of the image the RAM model will attempt to load via Verilog $readmemh
|
478 |
|
|
# system function.
|
479 |
|
|
|
480 |
|
|
# Set PRELOAD_RAM=1 to preload the system memory - be sure the bootROM program
|
481 |
|
|
# chosen in board.h is the one booting from the reset vector.
|
482 |
|
|
ifeq ($(PRELOAD_RAM), 1)
|
483 |
|
|
SIM_SW_IMAGE ?=sram.vmem
|
484 |
|
|
else
|
485 |
|
|
SIM_SW_IMAGE ?=flash.in
|
486 |
|
|
endif
|
487 |
|
|
|
488 |
|
|
.PHONY : sw
|
489 |
|
|
sw: $(SIM_SW_IMAGE)
|
490 |
|
|
|
491 |
411 |
julius |
|
492 |
408 |
julius |
flash.in: $(SW_TEST_DIR)/$(TEST).flashin
|
493 |
|
|
$(Q)if [ -L $@ ]; then unlink $@; fi
|
494 |
|
|
$(Q)ln -s $< $@
|
495 |
|
|
|
496 |
|
|
sram.vmem: $(SW_TEST_DIR)/$(TEST).vmem
|
497 |
|
|
$(Q)if [ -L $@ ]; then unlink $@; fi
|
498 |
|
|
$(Q)ln -s $< $@
|
499 |
|
|
|
500 |
|
|
.PHONY: $(SW_TEST_DIR)/$(TEST).flashin
|
501 |
|
|
$(SW_TEST_DIR)/$(TEST).flashin:
|
502 |
|
|
$(Q) echo; echo "\t### Compiling software ###"; echo;
|
503 |
|
|
$(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).flashin
|
504 |
|
|
|
505 |
|
|
.PHONY: $(SW_TEST_DIR)/$(TEST).vmem
|
506 |
|
|
$(SW_TEST_DIR)/$(TEST).vmem:
|
507 |
|
|
$(Q) echo; echo "\t### Compiling software ###"; echo;
|
508 |
|
|
$(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).vmem
|
509 |
|
|
|
510 |
411 |
julius |
# Create test software disassembly
|
511 |
|
|
|
512 |
|
|
sw-dis: $(SW_TEST_DIR)/$(TEST).dis
|
513 |
|
|
$(Q)cp -v $< .
|
514 |
|
|
|
515 |
|
|
$(SW_TEST_DIR)/$(TEST).dis:
|
516 |
|
|
$(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).dis
|
517 |
|
|
|
518 |
408 |
julius |
#
|
519 |
|
|
# Cleaning rules
|
520 |
|
|
#
|
521 |
|
|
clean: clean-sim clean-sim-test-sw clean-bootrom clean-out clean-sw
|
522 |
|
|
|
523 |
|
|
clean-sim:
|
524 |
|
|
$(Q) echo; echo "\t### Cleaning simulation run directory ###"; echo;
|
525 |
|
|
$(Q)rm -rf *.* lib_* work transcript check-test-log
|
526 |
|
|
# No VPI support for now. $(Q) if [ -e $(VPI_SRC_C_DIR) ]; then $(MAKE) -C $(VPI_SRC_C_DIR) clean; fi
|
527 |
|
|
|
528 |
|
|
clean-bootrom:
|
529 |
|
|
$(MAKE) -C $(BOOTROM_SW_DIR) clean
|
530 |
|
|
|
531 |
|
|
clean-out:
|
532 |
|
|
$(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
|
533 |
|
|
|
534 |
|
|
clean-test-defines:
|
535 |
|
|
$(Q)rm -f $(TEST_DEFINES_VLG)
|
536 |
|
|
|
537 |
|
|
clean-sim-test-sw:
|
538 |
|
|
$(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi
|
539 |
|
|
|
540 |
|
|
clean-sw:
|
541 |
|
|
$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
|
542 |
449 |
julius |
$(Q) $(MAKE) -C $(COMMON_SW_DIR)/lib distclean
|
543 |
408 |
julius |
|
544 |
|
|
clean-rtl:
|
545 |
|
|
$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
|
546 |
|
|
for module in $(RTL_TO_CHECK); do \
|
547 |
|
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
|
548 |
|
|
done
|
549 |
|
|
|
550 |
|
|
# Removes any checked out RTL
|
551 |
|
|
distclean: clean
|
552 |
|
|
$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
|
553 |
|
|
$(Q)for module in $(RTL_TO_CHECK); do \
|
554 |
|
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module distclean; \
|
555 |
|
|
done
|