OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sim/] [bin/] [Makefile] - Blame information for rev 475

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius
######################################################################
2
####                                                              ####
3
####  ORPSoCv2 Testbenches Makefile                               ####
4
####                                                              ####
5
####  Description                                                 ####
6
####  ORPSoCv2 Testbenches Makefile, containing rules for         ####
7
####  configuring and running different tests on the current      ####
8
####  ORPSoC(v2) design.                                          ####
9
####                                                              ####
10
####  To do:                                                      ####
11
####                                                              ####
12
####  Author(s):                                                  ####
13
####      - Julius Baxter, julius@opencores.org                   ####
14
####                                                              ####
15
####                                                              ####
16
######################################################################
17
####                                                              ####
18
#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG            ####
19
####                                                              ####
20
#### This source file may be used and distributed without         ####
21
#### restriction provided that this copyright statement is not    ####
22
#### removed from the file and that any derivative work contains  ####
23
#### the original copyright notice and the associated disclaimer. ####
24
####                                                              ####
25
#### This source file is free software; you can redistribute it   ####
26
#### and/or modify it under the terms of the GNU Lesser General   ####
27
#### Public License as published by the Free Software Foundation; ####
28
#### either version 2.1 of the License, or (at your option) any   ####
29
#### later version.                                               ####
30
####                                                              ####
31
#### This source is distributed in the hope that it will be       ####
32
#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
33
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
34
#### PURPOSE.  See the GNU Lesser General Public License for more ####
35
#### details.                                                     ####
36
####                                                              ####
37
#### You should have received a copy of the GNU Lesser General    ####
38
#### Public License along with this source; if not, download it   ####
39
#### from http://www.opencores.org/lgpl.shtml                     ####
40
####                                                              ####
41
######################################################################
42
 
43
# Name of the directory we're currently in
44
CUR_DIR=$(shell pwd)
45
 
46
# The root path of the whole project
47
PROJECT_ROOT ?=$(CUR_DIR)/../../../../..
48
 
49
DESIGN_NAME=orpsoc
50
RTL_TESTBENCH_TOP=$(DESIGN_NAME)_testbench
51
 
52
# Hardset the board name, even though we could probably determine it
53
FPGA_VENDOR=actel
54
BOARD_NAME=ordb1a3pe1500
55
BOARD_DIR=$(PROJECT_ROOT)/boards/$(FPGA_VENDOR)/$(BOARD_NAME)
56
 
57
# Export BOARD_PATH for the software makefiles
58 468 julius
BOARD=$(FPGA_VENDOR)/$(BOARD_NAME)
59
export BOARD
60 408 julius
 
61
# Paths to other important parts of this test suite
62
COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl
63
COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog
64
#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
65
 
66
BOARD_RTL_DIR=$(BOARD_DIR)/rtl
67
BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
68
# Only 1 include path for board builds - their own!
69
BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
70
 
71
BOARD_BENCH_DIR=$(BOARD_DIR)/bench
72
BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
73
BOARD_BENCH_VERILOG_INCLUDE_DIR=$(BOARD_BENCH_VERILOG_DIR)/include
74
 
75
COMMON_BENCH_DIR=$(PROJECT_ROOT)
76
COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog
77
COMMON_BENCH_VERILOG_INCLUDE_DIR=$(COMMON_BENCH_VERILOG_DIR)/include
78
 
79
# Top level files for DUT and testbench
80
DUT_TOP=$(BOARD_RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v
81
BENCH_TOP=$(BOARD_BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
82
 
83
# Software tests we'll run
84
 
85
# Need this for individual test variables to not break
86
TEST ?= or1200-simple
87
 
88
TESTS ?= or1200-simple or1200-cbasic or1200-dctest or1200-float or1200-mmu or1200-basic or1200-except or1200-tick or1200-ticksyscall uart-simple
89
 
90
# Gets turned into verilog `define
91
SIM_TYPE=RTL
92
 
93
# Main defines file is from board include path
94
PROJECT_VERILOG_DEFINES=$(BOARD_RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
95
 
96
# Detect technology to use for the simulation
97
DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
98
 
99
# Rule to look at what defines are being extracted from main file
100
print-defines:
101
        @echo echo; echo "\t### Design defines ###"; echo;
102
        @echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
103
        @echo $(DESIGN_DEFINES)
104
 
105
print-tests:
106
        @echo; echo; echo "\t### Software tests to be run ###"; echo;
107
        @echo $(TESTS)
108
        @echo
109
 
110
# Simulation directories
111
SIM_DIR ?=$(BOARD_DIR)/sim
112
RTL_SIM_DIR=$(SIM_DIR)
113
RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
114
RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
115
RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
116
 
117
# Testbench paths
118
BOARD_BENCH_DIR=$(BOARD_DIR)/bench
119
BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
120
COMMON_BENCH_DIR=$(PROJECT_ROOT)/bench
121
COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog
122
 
123
#BENCH_VHDL_DIR=$(BENCH_DIR)/vhdl
124
# No SystemC or Verilator support for this build
125
#BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
126
#BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
127
#BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
128
 
129
# Backend directories
130
# This one is the board build's backend dir.
131
BOARD_BACKEND_DIR=$(BOARD_DIR)/backend
132
BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog
133
TECHNOLOGY_BACKEND_DIR=$(BOARD_DIR)/../backend
134
# This path is for the technology library
135
TECHNOLOGY_BACKEND_VERILOG_DIR=$(TECHNOLOGY_BACKEND_DIR)/rtl/verilog
136
 
137 411 julius
# Synthesis directory for board
138
BOARD_SYN_DIR=$(BOARD_DIR)/syn/synplify
139
BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out
140
 
141 408 julius
# System software dir
142
COMMON_SW_DIR=$(PROJECT_ROOT)/sw
143
BOARD_SW_DIR=$(BOARD_DIR)/sw
144
 
145
# BootROM code, which generates a verilog array select values
146
BOOTROM_FILE=bootrom.v
147
BOOTROM_SW_DIR=$(BOARD_SW_DIR)/bootrom
148
BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
149
BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
150
 
151
bootrom: $(BOOTROM_VERILOG)
152
 
153
$(BOOTROM_VERILOG): $(BOOTROM_SRC)
154
        $(Q)echo; echo "\t### Generating bootup ROM ###"; echo
155
        $(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
156
 
157
# Suffix of file to check after each test for the string
158
TEST_OUT_FILE_SUFFIX=-general.log
159
TEST_OK_STRING=8000000d
160
 
161
# Dynamically generated verilog file defining configuration for various things
162
# Rule actually generating this is found in definesgen.inc file.
163
TEST_DEFINES_VLG=test-defines.v
164
# Set V=1 when calling make to enable verbose output
165
# mainly for debugging purposes.
166
ifeq ($(V), 1)
167
Q=
168
QUIET=
169
else
170
Q ?=@
171
QUIET=-quiet
172
endif
173
 
174
# Modelsim variables
175
MGC_VSIM=vsim
176
MGC_VLOG_COMP=vlog
177
MGC_VHDL_COMP=vcom
178
MODELSIM=modelsim
179
 
180
# Default simulator is Modelsim here as we're using the ProASIC3
181
# libraries which are not compilable with Icarus.
182
# Set SIMULATOR=modelsim to use Modelsim (Default)
183
# Set SIMULATOR=ncverilog to use Cadence's NC-Verilog - TODO
184
# Set SIMULATOR=icarus to use Icarus Verilog (Not supported for this board)
185
 
186
SIMULATOR ?= $(MODELSIM)
187
 
188
#
189
# Modelsim-specific settings
190
#
191
VOPT_ARGS=$(QUIET) -suppress 2241
192
# If VCD dump is desired, tell Modelsim not to optimise
193
# away everything.
194
ifeq ($(VCD), 1)
195
#VOPT_ARGS=-voptargs="+acc=rnp"
196
VOPT_ARGS=+acc=rnpqv
197
endif
198
# VSIM commands
199
# Suppressed warnings - 3009: Failed to open $readmemh() file
200
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
201
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
202
VSIM_ARGS=  -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
203
# Modelsim VPI settings
204
ifeq ($(VPI), 1)
205
VPI_LIBS=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
206
VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
207
endif
208
# Rule to make the VPI library for modelsim
209
$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB): $(VPI_SRCS)
210
        $(MAKE) -C $(VPI_SRC_C_DIR) $(MODELTECH_VPILIB)
211
 
212
#
213
# Verilog DUT source variables
214
#
215 411 julius
 
216
# First consider any modules we'll use gatelevel descriptions of.
217
# These will have to be set on the command line
218
GATELEVEL_MODULES ?=
219
 
220 408 julius
# First we get a list of modules in the RTL path of the board's path.
221
# Next we check which modules not in the board's RTL path are in the root RTL
222
# path (modules which can be commonly instantiated, but over which board
223
# build-specific versions take precedence.)
224
 
225
# Paths under board/***/rtl/verilog we wish to exclude when getting modules
226 411 julius
BOARD_VERILOG_MODULES_EXCLUDE= include $(GATELEVEL_MODULES)
227 408 julius
BOARD_VERILOG_MODULES_DIR_LIST=$(shell ls $(BOARD_RTL_VERILOG_DIR))
228
# Apply exclude to list of modules
229
BOARD_RTL_VERILOG_MODULES=$(filter-out $(BOARD_VERILOG_MODULES_EXCLUDE),$(BOARD_VERILOG_MODULES_DIR_LIST))
230
 
231
# Rule for debugging this script
232
print-board-modules:
233
        @echo echo; echo "\t### Board verilog modules ###"; echo
234
        @echo $(BOARD_RTL_VERILOG_MODULES)
235
 
236
# Now get list of modules that we don't have a version of in the board path
237
COMMON_VERILOG_MODULES_EXCLUDE= include
238
COMMON_VERILOG_MODULES_EXCLUDE += $(BOARD_RTL_VERILOG_MODULES)
239 411 julius
COMMON_VERILOG_MODULES_EXCLUDE += $(GATELEVEL_MODULES)
240 408 julius
 
241
COMMON_RTL_VERILOG_MODULES_DIR_LIST=$(shell ls $(COMMON_RTL_VERILOG_DIR))
242
COMMON_RTL_VERILOG_MODULES=$(filter-out $(COMMON_VERILOG_MODULES_EXCLUDE), $(COMMON_RTL_VERILOG_MODULES_DIR_LIST))
243
 
244 411 julius
 
245
# Add these to exclude their RTL directories from being included in scripts
246
 
247
 
248
 
249 408 julius
# Rule for debugging this script
250
print-common-modules-exclude:
251
        @echo echo; echo "\t### Common verilog modules being excluded due to board versions ###"; echo
252
        @echo "$(COMMON_VERILOG_MODULES_EXCLUDE)"
253
 
254
print-common-modules:
255
        @echo echo; echo "\t###  Verilog modules from common RTL dir ###"; echo
256
        @echo $(COMMON_RTL_VERILOG_MODULES)
257
 
258
# List of verilog source files (only .v files!)
259
# Board RTL modules first
260
RTL_VERILOG_SRC=$(shell for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then ls $(BOARD_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
261
# Common RTL module source
262
RTL_VERILOG_SRC +=$(shell for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then ls $(COMMON_RTL_VERILOG_DIR)/$$module/*.v; fi; done)
263
 
264
# List of verilog includes from board RTL path - only for rule sensitivity
265
RTL_VERILOG_INCLUDES=$(shell ls $(BOARD_RTL_VERILOG_INCLUDE_DIR)/*.*)
266
 
267
print-verilog-src:
268
        @echo echo; echo "\t### Verilog source ###"; echo
269
        @echo $(RTL_VERILOG_SRC)
270
 
271
# Rules to make RTL we might need
272
# Expects modules, if they need making, to have their top verilog file to
273
# correspond to their module name, and the directory should have a make file
274
# and rule which works for this command.
275
# Add name of module to this list, currently only does verilog ones.
276
# Rule 'rtl' is called just before generating DUT modelsim compilation script
277
RTL_TO_CHECK=
278
rtl:
279
        $(Q)for module in $(RTL_TO_CHECK); do \
280
                $(MAKE) -C $(RTL_VERILOG_DIR)/$$module $$module.v; \
281
        done
282
 
283
#
284
# VHDL DUT source variables
285
#
286
# VHDL modules
287
#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
288
# VHDL sources
289
#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do if [ -d $(RTL_VHDL_DIR)/$$module ]; then ls $(RTL_VHDL_DIR)/$$module/*.vhd; fi; done)
290
#print-vhdl-src:
291
#       @echo echo; echo "\t### VHDL modules and source ###"; echo
292
#       @echo "modules: "; echo $(RTL_VHDL_MODULES); echo
293
#       @echo "source: "$(RTL_VHDL_SRC)
294
 
295
#
296
# Testbench source
297
#
298
BOARD_BENCH_VERILOG_SRC=$(shell ls $(BOARD_BENCH_VERILOG_DIR)/*.v | grep -v $(DESIGN_NAME)_testbench )
299
BOARD_BENCH_VERILOG_SRC_FILES=$(notdir $(BOARD_BENCH_VERILOG_SRC))
300
 
301
# Now only take the source from the common path that we don't already have in
302
# our board's
303
COMMON_BENCH_VERILOG_DIR_LS=$(shell ls $(COMMON_BENCH_VERILOG_DIR)/*.v)
304
COMMON_BENCH_VERILOG_SRC_FILES=$(notdir $(COMMON_BENCH_VERILOG_DIR_LS))
305
COMMON_BENCH_VERILOG_SRC_FILTERED=$(filter-out $(BOARD_BENCH_VERILOG_SRC_FILES) $(DESIGN_NAME)_testbench.v,$(COMMON_BENCH_VERILOG_SRC_FILES))
306
COMMON_BENCH_VERILOG_SRC=$(addprefix $(COMMON_BENCH_VERILOG_DIR)/, $(COMMON_BENCH_VERILOG_SRC_FILTERED))
307
 
308
print-board-bench-src:
309
        $(Q)echo "\tBoard bench verilog source"; \
310
        echo $(BOARD_BENCH_VERILOG_SRC)
311
 
312
print-common-bench-src:
313
        $(Q)echo "\Common bench verilog source"; \
314
        echo $(COMMON_BENCH_VERILOG_SRC)
315
 
316
# Testbench source subdirectory detection (exclude include, we always use
317
# board bench include directory!)
318
BOARD_BENCH_VERILOG_SUBDIRS=$(shell cd $(BOARD_BENCH_VERILOG_DIR) && ls -d */ | grep -v include)
319
COMMON_BENCH_VERILOG_SUBDIRS=$(shell cd $(COMMON_BENCH_VERILOG_DIR) && ls -d */ | grep -v include)
320
 
321
# Get rid of ones we have a copy of locally
322
COMMON_BENCH_VERILOG_SUBDIRS_EXCLUDE_BOARDS=$(filter-out $(BOARD_BENCH_VERILOG_SUBDIRS),$(COMMON_BENCH_VERILOG_SUBDIRS))
323
 
324
# Construct list of paths we will want to include
325
BENCH_VERILOG_SUBDIRS=$(addprefix $(COMMON_BENCH_VERILOG_DIR)/,$(COMMON_BENCH_VERILOG_SUBDIRS_EXCLUDE_BOARDS))
326
BENCH_VERILOG_SUBDIRS += $(addprefix $(BOARD_BENCH_VERILOG_DIR)/,$(BOARD_BENCH_VERILOG_SUBDIRS))
327
 
328
# Finally, add include path from local bench path
329
BENCH_VERILOG_SUBDIRS += $(BOARD_BENCH_VERILOG_DIR)/include
330
 
331
print-board-bench-subdirs:
332
        $(Q)echo "\tBoard bench subdirectories"; \
333
        echo $(BOARD_BENCH_VERILOG_SUBDIRS)
334
 
335
print-common-bench-subdirs:
336
        $(Q)echo "\tCommon bench subdirectories"; \
337
        echo $(COMMON_BENCH_VERILOG_SUBDIRS)
338
 
339
print-bench-subdirs:
340
        $(Q)echo "\tBench subdirectories"; \
341
        echo $(BENCH_VERILOG_SUBDIRS)
342
 
343
 
344
# Backend technology library files
345
# We don't do this for the board backend stuff - that should all be properly
346
# named, and so we only need to pass the "-y" option for that path.
347
BACKEND_TECHNOLOGY_VERILOG_SRC=$(shell ls $(TECHNOLOGY_BACKEND_VERILOG_DIR)/*.v )
348
BOARD_BACKEND_VERILOG_SRC=$(shell ls $(BOARD_BACKEND_VERILOG_DIR)/*.v )
349
 
350
#
351
# Compile script generation rules:
352
#
353
 
354
# Modelsim library compilation rules
355
 
356
# Backend script generation - make these rules sensitive to source and includes
357
modelsim_backend.scr: $(BOARD_BACKEND_VERILOG_SRC)
358
        $(Q)echo "+incdir+"$(TECHNOLOGY_BACKEND_VERILOG_DIR) > $@;
359
        $(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@
360
        $(Q)echo "+libext+.v" >> $@;
361
        $(Q)for vsrc in $(BACKEND_TECHNOLOGY_VERILOG_SRC); do echo $$vsrc >> $@; done
362
        $(Q)echo >> $@;
363
 
364
# DUT compile script
365
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
366
        $(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) > $@;
367
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
368
        $(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) >> $@;
369
        $(Q)echo "+libext+.v" >> $@;
370
        $(Q)for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(BOARD_RTL_VERILOG_DIR)/$$module >> $@; fi; done
371
        $(Q)for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(COMMON_RTL_VERILOG_DIR)/$$module >> $@; fi; done
372
        $(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@;
373 411 julius
        $(Q)if [ ! -z "$$GATELEVEL_MODULES" ]; \
374
                then echo "-y " $(BOARD_SYN_OUT_DIR) >> $@; \
375
                echo "+libext+.vm" >> $@; \
376
        fi
377 408 julius
        $(Q)echo >> $@
378
 
379
modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC)
380
        $(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) > $@;
381
        $(Q)echo "+incdir+"$(COMMON_BENCH_VERILOG_INCLUDE_DIR) >> $@;
382
        $(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "+incdir+"$$path >> $@; done
383
        $(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "-y "$$path >> $@; done
384
        $(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) >> $@;
385
        $(Q)echo "+libext+.v" >> $@;
386
        $(Q)for vsrc in $(BOARD_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
387
        $(Q)for vsrc in $(COMMON_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
388
        $(Q)echo >> $@
389
 
390
# Modelsim library compilation rules
391
# Actel backend library
392
BACKEND_LIB=lib_backend
393
$(BACKEND_LIB): modelsim_backend.scr
394
        $(Q)if [ ! -e $@ ]; then vlib $@; fi
395
        $(Q)echo; echo "\t### Compiling Actel backend library ###"; echo
396
        $(Q)vlog -nologo $(QUIET) -work $@ -f $<
397
 
398
# Compile DUT into "work" library
399
work: modelsim_dut.scr
400
        $(Q)if [ ! -e $@ ]; then vlib $@; fi
401
        $(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
402
        $(Q)vlog $(QUIET) -f $< $(DUT_TOP)
403
 
404
# Single compile rule
405
.PHONY : $(MODELSIM)
406
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
407
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
408
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
409
        $(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -L $(BACKEND_LIB) \
410
        -o tb
411
        $(Q)echo; echo "\t### Launching simulation ###"; echo
412
        $(Q)vsim $(VSIM_ARGS) tb
413
 
414
 
415
.PHONY: rtl-test
416
rtl-test: clean-sim-test-sw sw clean-test-defines $(TEST_DEFINES_VLG) \
417
        $(SIMULATOR)
418
 
419
# Run an RTL test followed by checking of generated results
420
rtl-test-with-check: rtl-test
421
        $(Q)$(MAKE) check-test-log; \
422
        if [ $$? -ne 0 ]; then \
423
                echo; echo "\t### "$(TEST)" test FAIL ###"; echo; \
424
        else \
425
                echo; echo "\t### "$(TEST)" test OK ###"; echo; \
426
        fi
427
 
428
# Do check, don't print anything out
429
rtl-test-with-check-no-print: rtl-test check-test-log
430
 
431
# Main RTL test loop
432
rtl-tests:
433
        $(Q)for test in $(TESTS); do \
434
                export TEST=$$test; \
435
                $(MAKE) rtl-test-with-check-no-print; \
436
                if [ $$? -ne 0 ]; then break; fi; \
437
                echo; echo "\t### $$test test OK ###"; echo; \
438
        done
439
 
440
 
441
.PHONY: check-test-log
442
check-test-log:
443
        $(Q)echo "#!/bin/bash" > $@
444
        $(Q)echo "function check-test-log { if [ \`grep -c -i "$(TEST_OK_STRING)" "$(RTL_SIM_RESULTS_DIR)"/"$(TEST)$(TEST_OUT_FILE_SUFFIX)"\` -gt 0 ]; then return 0; else return 1; fi; }" >> $@
445
        $(Q)echo "check-test-log" >> $@
446
        $(Q)chmod +x $@
447
        $(Q) echo; echo "\t### Checking simulation results for "$(TEST)" test ###"; echo;
448
        $(Q)./$@
449
 
450
# Include the test-defines.v generation rule
451
include $(PROJECT_ROOT)/sim/bin/definesgen.inc
452
 
453
#
454
# Software make rules (called recursively)
455
#
456
 
457
# Path for the current test
458
# First check for a local copy of the test. If it doesn't exist then we
459
# default to the software tests in the root directory
460
TEST_MODULE=$(shell echo $(TEST) | cut -d "-" -f 1)
461
BOARD_SW_TEST_DIR=$(BOARD_SW_DIR)/tests/$(TEST_MODULE)/sim
462
COMMON_SW_TEST_DIR=$(COMMON_SW_DIR)/tests/$(TEST_MODULE)/sim
463
# Do this by testing for the file's existence
464
SW_TEST_DIR=$(shell if [ -e $(BOARD_SW_TEST_DIR)/$(TEST).[cS] ]; then echo $(BOARD_SW_TEST_DIR); else echo $(COMMON_SW_TEST_DIR); fi)
465
 
466
print-test-sw-dir:
467
        @echo; echo "\tTest software is in the following path"; echo;
468
        @echo $(BOARD_SW_DIR); echo;
469
        @echo $(BOARD_SW_TEST_DIR); echo;
470
        @echo $(SW_TEST_DIR); echo;
471
 
472
print-sw-tests:
473
        $(Q) $(MAKE) -C $(COMMON_SW_DIR)/lib print-sw-tests
474
        $(Q) $(MAKE) -C $(COMMON_SW_DIR)/lib print-sw-tests-subdirs
475
 
476
 
477
# Name of the image the RAM model will attempt to load via Verilog $readmemh
478
# system function.
479
 
480
# Set PRELOAD_RAM=1 to preload the system memory - be sure the bootROM program
481
# chosen in board.h is the one booting from the reset vector.
482
ifeq ($(PRELOAD_RAM), 1)
483
SIM_SW_IMAGE ?=sram.vmem
484
else
485
SIM_SW_IMAGE ?=flash.in
486
endif
487
 
488
.PHONY : sw
489
sw: $(SIM_SW_IMAGE)
490
 
491 411 julius
 
492 408 julius
flash.in: $(SW_TEST_DIR)/$(TEST).flashin
493
        $(Q)if [ -L $@ ]; then unlink $@; fi
494
        $(Q)ln -s $< $@
495
 
496
sram.vmem: $(SW_TEST_DIR)/$(TEST).vmem
497
        $(Q)if [ -L $@ ]; then unlink $@; fi
498
        $(Q)ln -s $< $@
499
 
500
.PHONY: $(SW_TEST_DIR)/$(TEST).flashin
501
$(SW_TEST_DIR)/$(TEST).flashin:
502
        $(Q) echo; echo "\t### Compiling software ###"; echo;
503
        $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).flashin
504
 
505
.PHONY: $(SW_TEST_DIR)/$(TEST).vmem
506
$(SW_TEST_DIR)/$(TEST).vmem:
507
        $(Q) echo; echo "\t### Compiling software ###"; echo;
508
        $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).vmem
509
 
510 411 julius
# Create test software disassembly
511
 
512
sw-dis: $(SW_TEST_DIR)/$(TEST).dis
513
        $(Q)cp -v $< .
514
 
515
$(SW_TEST_DIR)/$(TEST).dis:
516
        $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).dis
517
 
518 408 julius
#
519
# Cleaning rules
520
#
521
clean: clean-sim clean-sim-test-sw clean-bootrom clean-out clean-sw
522
 
523
clean-sim:
524
        $(Q) echo; echo "\t### Cleaning simulation run directory ###"; echo;
525
        $(Q)rm -rf *.* lib_* work transcript check-test-log
526
# No VPI support for now.       $(Q) if [ -e $(VPI_SRC_C_DIR) ]; then $(MAKE) -C $(VPI_SRC_C_DIR) clean; fi
527
 
528
clean-bootrom:
529
        $(MAKE) -C $(BOOTROM_SW_DIR) clean
530
 
531
clean-out:
532
        $(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
533
 
534
clean-test-defines:
535
        $(Q)rm -f $(TEST_DEFINES_VLG)
536
 
537
clean-sim-test-sw:
538
        $(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi
539
 
540
clean-sw:
541
        $(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
542 449 julius
        $(Q) $(MAKE) -C $(COMMON_SW_DIR)/lib distclean
543 408 julius
 
544
clean-rtl:
545
        $(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
546
        for module in $(RTL_TO_CHECK); do \
547
                $(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
548
        done
549
 
550
# Removes any checked out RTL
551
distclean: clean
552
        $(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
553
        $(Q)for module in $(RTL_TO_CHECK); do \
554
                $(MAKE) -C $(RTL_VERILOG_DIR)/$$module distclean; \
555
        done

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.